Chapter 7

Sequential Circuit Design

_____________________________________________
7.0 Introduction
The combinational circuit discussed in the previous chapter does not have the
capability to remember the event. Sequential circuit is consisting of a
combinational circuit as well as memory block in the feedback loop. This makes
the circuit to remember the event. In general sequential circuit has direct or
indirect feedback that is input connected to output. This case creates regenerative behavior of the circuit.
In this chapter, we discuss the various types of the sequential circuits. The
first one to be discussed is the bi-state circuit. Others are flip-flops and latches.
The memory circuits are discussed toward the end of the chapter.

7.1 Transistor Level Design of Flip-Flop

Flip-flop is the primitive memory element, which is shown in Fig. 7.1. It
contains two NOT gates where the outputs are fed to inputs of the opposite
NOT gate. The CMOS circuit of the bi-stable element is shown in Fig. 7.2.

Figure 7.1: A basic bi-stable element

When logic 1 is connected to input A, the output Q is at logic 0. The logic state
is input to second NOT gate and its output Q will be at logic 1, which is the
same state as the input A. In this manner, the output Q and Q would stay at its
respective logic state even if the logic 1 at input A is removed.
- 173 -

7 Sequential Circuit Design

Figure 7.2: CMOS circuit of a bi-stable element

When logic 0 is connected to input A, the output Q will be at logic 1. The logic
state is input to second NOT gate and its output Q will be at logic 0, which is
the same state as the input A. In this manner, the output Q and Q would remain
at its respective logic state even if the logic 0 at input A is removed. Combining
both conditions of logic states, the bi-stable element forms the basic memory
bit. The layout of the bi-stable element is shown in Fig. 7.3.

Figure 7.3: The layout of the bi-stable element

- 174 -

7 Sequential Circuit Design

The bi-state element has two stable states and one unstable state. The unstable
state occurs at the mid-point voltage. At this point all transistors are in
saturation mode and also at the highest potential energy.
The SR flip-flop is shown in Fig. 7.4. The output Q is Q = S CLK + Q and
Q = R CLK + Q . Using DeMorgans theorem, Q is also equal to Q =
(S + CLK ) Q , which forms the p-MOS transistor circuit of the output Q . Output
Q is also equal to (R + CLK ) Q , which forms the p-MOS transistor circuit of
output Q.

Figure 7.4: SR flip-flop

Based on p-MOS and n-MOS transistors equations of the SR flip-flop, the

CMOS circuit design of the SR flip-flop is shown in Fig. 7.5.

Figure 7.5: CMOS circuit of a SR flip-flop

- 175 -

7 Sequential Circuit Design

The D flip-flop is shown in Fig. 7.6. The output Q is Q = D + Q = D Q , whilst

the output Q is Q = Q + D = Q D .

Figure 7.6: A D flip-flop

The CMOS circuit of the D flip-flop shall be as shown in Fig. 7.7.

Figure 7.7: CMOS circuit of a D flip-flop

The transmission gate design of a basic D flip-flop is shown in Figure 7.8.

During the load operation, Load = 1 with D = 1, the first transmission gate is
switched on, while the second transmission gate is off. During the hold
operation whereby Load = 0, the first transmission gate is off, while the second
transmission gate is switched on. Thus, the data D = 1 is maintained at Q output.
The node X has logic function D Load . The feedback to node X has logic
function (D Load ) Load , which logic 0. This has no bearing effect at node X in
which it still has logic function D Load maintained.
- 176 -

7 Sequential Circuit Design

Figure 7.8: Transmission gate design of a D flip-flop

Another compact way to design a D flip-flop is shown in Fig. 7.9. The output at
node X is D Load + D Load , which is equal to D. Thus, data D is latched when
Load is equal to logic 1.

Figure 7.9: Compact design of D flip-flop

In order to avoid wrong data being latch into the D flip-flop, the D flip-flop can
be designed with master/slave operation that utilizing transmission gate and
NOT gates. Figure 7.10 shows the CMOS design of a master/slave D flip-flop.
Transmission gate B and D are used to prevent the output of master flip-flop
- 177 -

7 Sequential Circuit Design

and slave flip-flop from driving the output of transmission gate A and C. Unless
the output of transmission gate A and C is able to sink or source sufficient
current to overcome the output drive from output of master flip-flop and slave
flip-flop, wrong data latch would occur. Besides having transmission gate B and
D, the aspect ratio W/L of transmission gate A and C can be designed sufficient
large as compare with the aspect ratio of other transistor.
At node X, the logic function is Load D and the logic function at node Y is
Load D . The logic function at node Y is Load D Load = (Load D) + Load and
the logic function at node Z is (Load D) + Load = D, which is the data D.

Figure 7.10: A master/slave D flip-flop

The JK flip-flop is shown Fig. 7.11. The Boolean function of output Q is Q =

Q J CLK + Q , which is also equal to ( Q + J + CLK ) Q . The Boolean function of

Q is Q = Q K CLK + Q , which is also equal to ( Q + K + CLK ) Q .

- 178 -

7 Sequential Circuit Design

Figure 7.11: Logic circuit of a JK flip-flop

Based on the output equations mentioned above, the CMOS circuit design of the
JK flip-flop is shown in Fig. 7.12.

Figure 7.12: CMOS circuit design of a JK flip-flop

The T flip-flop is shown in Fig. 7.13. The Boolean function of output Q is Q =

Q T CLK + Q = ( Q + T + CLK ) Q and the Boolean function of output Q is Q

= Q T CLK + Q = ( Q + T + CLK ) Q .

- 179 -

7 Sequential Circuit Design

Figure 7.13: T flip-flop

Based on the output equations, the CMOS circuit design of the T flip-flop is
shown in Fig. 7.14.

Figure 7.14: CMOS circuit design of a T flip-flop

7.2 n-channel Pass-Transistor Storage Circuit

Transmission gate based storage element can be designed using n-channel MOS
pass-transistor instead of transmission gates. A basic D flip-flop is shown in
Fig. 7.15. When the load is at logic 1, the data D is passed to output Q. When
the load is at logic 0, the transistor M1 is switched off and transistor M2
switched on and maintained the data D at output Q. The similar explanation as
above is used for passing data D equal logic 0 to output Q.
- 180 -

7 Sequential Circuit Design

Figure 7.15: A basic D flip-flop design with n-channel MOS pass-transistor

Based on the design for a basic D-flip-flop, the design of a master-slave D flipflop is shown in Fig. 7.16. This design is used to avoid latching of wrong logic.

Figure 7.16: Master-slave D flip-flop designed with n-channel MOS pass-transistor

7.3 Random Access Memory Devices

In this section the designs of static RAM, dynamic RAM, and ROM will be
discusses. The block diagram of a 1kx8 SRAM is shown in Fig. 7.17.
- 181 -

7 Sequential Circuit Design

Figure 7.17: Block diagram of a 1kx8 SRAM

This memory device has 128 row addresses and 8 column addresses. The
memory has 8 matrix blocks and each block has 128x8 cells. The other main
parts of the memory are the sense amplifier, control unit, input/output data
control, output data control, address bus, and data bus.
We shall discuss the approaches used to design memory cell static and
dynamic cell, the sense amplifier, and the address decoders row and column
decoders, and I/O data control circuits.

7.3.1 RAM Memory Cell

There are many methods to design the static and dynamic random access
memory cells. In this section, three methods are presented. They are sixtransistor static memory cell, three-transistor dynamic memory cell, and onetransistor dynamic memory cell.
- 182 -

7 Sequential Circuit Design

7.3.2.1 Six-Transistor Static Memory Cell

The six-transistor static memory cell is shown in Fig. 7.18. MOS transistor M1,
M2, M3, and M4 forms the bi-stable memory element, whilst n-channel MOS
transistor M5 and M6 are served as pass-transistors.

Figure 7.18: The six-transistor static RAM cell

During the write cycle, the desired logics are placed on bit line and BIT line.
When the WORD line is asserted, the desired data will be latched into the bistable memory element. For an example, to write logic 1 into the memory, the
BIT line is set at logic 1, whilst the BIT line is at logic 0.
However, due to high pack density of the memory cell whereby many
column memory cells are connected in the same bit line, the total drain-bulk
capacitance of the pass-transistors is sufficiently large that the charging and
discharging of the bit lines would take long time. Thus, during read cycle, the
BIT and BIT lines are pre-charged to the pre-defined level, which is usually 0.5
of VDD voltage level. These lines are then allowed to float. When the WORD
line is asserted, the BIT line and BIT line begin to charge or discharge that
reflect the logic level stored in memory cell. The small change in voltage level
is passed to the sense amplifier for output user. The read cycle is a destructive
cycle whereby the data stored in the memory can be erased. Therefore, it is
necessary to refresh the memory. Other mean to prevent the bit data being
erased is to design the pass-transistor to have large width and length. But this is
not desired because in the modern design, scale down is necessary to save cost
and fast access time.
- 183 -

7 Sequential Circuit Design

7.3.2.2 Three-Transistor Dynamic Memory Cell

The three-transistor dynamic RAM structure is shown in Fig. 7.19. Transistor
M1 is used to write the BIT logic into the source of transistor M1 and gate of
transistor M2. With the present of source capacitance CS, depending on the logic
being written, the gate voltage of transistor M2 should be either at logic 0 or
logic 1 that has voltage (VDD Vtn(M2)).

Figure 7.19: A three-transistor dynamic RAM cell

The BIT value is logic 0 then the gate voltage shall be 0V. If the BIT value is at
logic 1 then the gate voltage will be at logic 1 that has voltage (VWrite Vtn(M2)).
This voltage is hold on as long as the Read transistor M3 is not switched on.
During the read cycle, transistor M3 is switched on and if the BIT value is
logic 1 then the BIT line would turn logic 0. Likewise, if the BIT value is logic
0 then upon reading the BIT line would turn logic 1 that has maximum value
(VRead Vtn(M3)).

- 184 -

7 Sequential Circuit Design

7.3.2.3 One-Transistor Dynamic Memory Cell

One-transistor dynamic RAM cell uses capacitor to temporarily store the charge
on a memory capacitor CM. A simple 1-bit dynamic RAM cell is shown in Fig.
7.20.
During the write cycle, the logic level is placed on the BIT line. The
WORD line is then asserted to charge or discharge the memory capacitor CM.
The capacitor is leaky and will not hold the charge for long time. Thus, it is
necessary to refresh it periodically.
During the read cycle, the BIT line is pre-charged and placed in tri-state
mode. When the WORD line is asserted, the BIT capacitor CBIT is either
charging or discharging depending on the charge stored in memory capacitor
CM. The sense amplifier is then used to detect small change in voltage level and
output the appropriate logic level.

Figure 7.20: A 1-bit dynamic RAM cell

Read cycle is a destructive operation. Thus, the data must be re-written into the
memory capacitor CM.

7.3.2 Sense Amplifier

The typical sense amplifier circuit for static RAM is shown in Fig. 7.21. MOS
transistor M1, M2, M3, and M4, and M5 form the differential amplifier. MOS
transistor M6 and M7 form the common source amplifier and MOS transistor M8
and M9 form the inverter.
- 185 -

7 Sequential Circuit Design

Figure 7.21: A sense amplifier for static memory cell

If logic 1 is stored in the memory, during the read cycle, BIT voltage shall be
larger than BIT voltage. The output of MOS transistor M2 is
g m2
ro 4 || r02 (VBIT VBIT ) , whilst the output of MOS transistor M6 is
2
g m 2 g m6
(ro 4 || r02 )r07 (VBIT VBIT ) . This voltage value is closed to 5V. Therefore, the
2

output of the inverter shall be at logic 0.

If logic 0 is stored in the memory, during the read cycle, BIT voltage shall
be smaller than BIT voltage. The output of MOS transistor M2 is
g m2
ro 4 || r02 (VBIT VBIT ) , which is a positive value, whilst the output of MOS
2
g g
transistor M6 is m 2 m 6 (ro 4 || r02 )r07 (VBIT VBIT ) , which is a negative value. This
2

voltage value is closed to 0V, thus, the output of the inverter shall be at logic 1.
The typical sense amplifier circuit for the dynamic RAM cell is shown in
Fig. 7.22. Timing is used to charge the capacitor C2 to approximately 5.0V
and the MOS transistor M3 is used during pre-charging the BIT line. The clamp
- 186 -

7 Sequential Circuit Design

voltage set the gate voltage of the MOS transistor M2 to be greater than the precharged value of the BIT line.
If the stored bit is a 1, during the read cycle, upon the WORD line is
asserted, the stored charge in memory capacitor CM would charge the CBIT to
higher voltage. This set the MOS transistor M2 to be remained off. As the result
the output is at logic 0.

Figure 7.22: The sense amplifier for a dynamic RAM cell

When the stored bit is a 0, upon the WORD line is asserted, the pre-charge BIT
lines capacitor CBIT would charge the memory capacitor CM. As the result, the
voltage of BIT line capacitor CBIT is lower than the pre-charged value. This
causes the MOS transistor M2 to switch on and capacitor C2 would transfer
charge to BIT line capacitor CBIT. This causes the voltage at input of inverter to
drop very fast due to the value of C2 is smaller than the value of CBIT. As the
result the output is at logic 1.
A cascode voltage switching logic CVSL sense amplifier is shown in Fig.
7.23. During the read cycle, the bit line BL and BL are directed to Output and
Output . Upon enable the sense amplifier SE, the logic of the bit line is sent to
output and Output .
- 187 -

7 Sequential Circuit Design

Figure 7.23: A CVSL sense amplifier circuit

7.3.3 Decoder
A 2-address line dynamic NOR row decoder is shown in Fig. 7.24. There are
two stages for the operation of this decoder. They are the pre-charge stage and
evaluate stage.
The pre-charge input is asserted low that switches on all p-channel MOS
transistors and all outputs WL 0 , WL1 , WL 2 , and WL 3 of the decoder go to logic
1. The decoder should not be read at this instant, since all the outputs are at VDD
logic 1.
The next stage after pre-charge stage is the evaluation stage. Once the precharge is done, the p-channel MOS transistors are switched off. The outputs will
stay at logic 1 because the charge will be stored on the capacitors. The inputs
are applied on two address lines. The corresponding n-channel MOS transistor
will be switched on and the charged capacitor on that line will be discharged to
- 188 -

7 Sequential Circuit Design

ground. All lines except one will go to logic 0. The line that remains logic 1 will
be the decoded line that will drive all the n-channel MOS transistors on that
line. Thus, the right data will be available on the data line. This data will be
given to the output data block, which will return the correct data to the outside
world when the output enable signal is asserted.

Figure 7.24: A 2-address line dynamic NOR decoder

A 2-address line dynamic NAND row decoder is shown in Fig. 7.25. There are
two stages for the operation of this decoder. They are the pre-charge stage and
evaluate stage.
The pre-charge input is asserted low that switches on all p-channel MOS
transistors and all outputs WL 0 , WL1 , WL 2 , and WL 3 of the decoder go to logic
1. The decoder should not be read at this instant, since all the outputs are at VDD
logic 1.
The next stage after pre-charge stage is evaluation stage. Once the precharge is done, the p-channel MOS transistors are switched off. The outputs will
stay at logic 1 because the charge will be stored on the capacitors. The inputs
- 189 -

7 Sequential Circuit Design

are applied on two address lines. The corresponding n-channel MOS transistor
will be switched on and the charged capacitor on that line will be discharged to
ground. All lines remain logic 1 except one will go to ground logic 0. The line
that remains logic 0 will be the decoded line. The right data will be available on
the data line. This data will be given to the output data block, which will return
the correct data to the outside world when the output enable signal is asserted.

Figure 7.25: A 2-address dynamic NAND row decoder

A 2-address pass-transistor type column decoder is shown in Fig. 7.26. It

consists of a dynamic NOR column decoder and p-channel MOS passtransistors. Data from the output of sense amplifier like BL0, BL 0 , BL1, BL1 ,
BL2, BL 2 , BL3, BL 3 , and BL3 are fed to the source of the p-channel passtransistor. Each time only one set of p-channel MOS pass-transistor is switched
on by the dynamic column decoder.
The advantage of this type of column decoder is fast with only one passtransistor set is used in the path of the data transfer.

- 190 -

7 Sequential Circuit Design

Figure 7.26: A 2-address pass-transistor column decoder

A tree-based column decoder is shown in Fig. 7.27. It consists of p-channel

pass-transistor and address lines. Data from the output of sense amplifier like
BL0, BL 0 , BL1, BL1 , BL2, BL 2 , BL3, BL 3 , and BL3 are fed to the source of the
p-channel pass-transistor addressed by A 0 , A0, A 1 , and A1.

Figure 7.27: A tree-base 2-address column decoder

The main advantage of this type of decoder is the number of transistors used is
drastically reduced. The major disadvantage is time delay, which increases four
times with the number of sections increases. Thus, this type of design is
prohibited for designing large decoder.
- 191 -

7 Sequential Circuit Design

7.3.4 Pre-Charge Circuit

The static pull-up pre-charge circuit for the memory circuit is shown in Fig.
7.28. This circuit works like a gate-ground p-channel MOS transistor. Upon
asserted, the internal capacitors of the p-channel MOS transistors are charged to
VDD. The bit line BL and BL are hold at VDD voltage. During evaluation cycle
the stored charge can be charged or hold depending on the access condition.

Figure 7.28: Static pull-up pre-charge circuit

The clock pre-charge circuit is shown in Fig. 7.29. Falling edge clock will
charge the capacitor of the p-channel MOS transistors VDD voltage. During
evaluation cycle the stored charge can be charged or hold depending on the
access condition. The center transistor is the equalization transistor. It is used to
speed up equalization of the two bit lines by allowing the capacitance and pullup device of the non-discharged bit line to assist in pre-charging the discharged
line.

Figure 7.29: Static pull-up pre-charge circuit

- 192 -

7 Sequential Circuit Design

7.3.5 Input Data Control Circuit

A typical input data control circuit is shown in Fig. 7.30. The input data control
block is basically a data router. Data from the I/O pins is passed into the block
and then transferred to the memory cell array via a buffer circuit and a passtransistor. The pass-transistor controls the flow of data into the memory cell
array.

Figure 7.30: A 4-input data control block

During a write cycle, the write enable line WR is low asserted, which switches
on all pass-transistors. Likewise, during the read cycle, all pass-transistors are
switched off preventing data from entering the memory cell array.
The two inverters before the pass-transistors are basically buffers used to
increase the current handling capacity of the input data control circuit especially
when passing data speedily to the pass-transistor.
One of the other approaches is to use transmission gate replacing passtransistors for passing strong logic 0 and logic 1. One may replace the entire
pass-transistor circuit each with an inverter and a tri-state inverter.

- 193 -

7 Sequential Circuit Design

7.3.6 Output Data Control Circuit

An output control circuit is a simple controlled buffer circuit as shown in Fig.
7.31. A tri-state inverter is used to control the flow of data to the I/O lines from
the SRAM cells. When the output enable line OE is set to logic 0, the data from
the memory array cell can be passes to the output. When the output enable line
is at logic 1, the tri-state inverters will switch off and prevent data on the I/O
lines from passing to the external data bus. This is needed because the data lines
are bi-directional type.

Figure 7.31: A 4-output data control circuit

7.4 Read Only Memory

The contents of read only memory ROM cells are permanently fixed. The cell is
designed so that a logic 0 or logic 1 is presented to the bit line upon activation
of its word line. The desired logic level is created during the fabrication of the
device. Figure 7.32 shows several ways to implement logic 0 and logic 1 for the
ROM cells.
- 194 -

7 Sequential Circuit Design

Diode ROM has default logic 0 at bit line. When the word line of ROM is
selected, it provides logic 1 at bit line due low forward voltage of the diode.

(a) Diode ROM

(b) MOS ROM 1
(c) MOS ROM 2
Figure 7.32: Different methods for implementing logic 0 and logic 1 ROM cells

The MOS ROM 1 has default logic 0 at bit line. When the word line is selected,
the n-MOS transistor switches on and provides logic 1 at bit line. The MOS
ROM 2 has default logic 1. When the word line is selected, it provides logic 0 at
bit line.
An example of a 4x4-bit NOR ROM is shown in Fig. 7.33. The pull-up pMOS transistor and the n-MOS bit-transistor forms a pseudo n-MOS NOR gate.
ROM is designed with background logic 1. When the WORD line is asserted
the cell that has n-MOS transistor would be switched on to provide logic 0 at the
BIT line upon switched on by CLK signal on p-MOS transistor. Normally the
clock CLK is pre-charged to half of VDD for enable fast access of the memory
cell. The WORD line and BIT line matrix that does not contain any n-MOS
transistor would provide logic 1 upon clock line is asserted. The one that
contains an n-MOS transistor would provide logic 0 because the n-MOS
transistor is a high-asserted low device. When it is selected, the output would be
at logic 0 simply because the transistor is switched on.
The ROM has data value WORD 0 = 0001, WORD 1 = 1000, WORD 2 =
0010, and WORD 3 = 0100.
- 195 -

7 Sequential Circuit Design

Figure 7.33: A 4x4-bits NOR ROM

Instead of having the pull-up p-MOS transistor, ROM design with pull-down nMOS transistor and n-MOS transistor cell tied to VDD is called OR ROM. Figure
7.34 shows a 4x4 bit OR ROM.

Figure 7.34: A 4x4 OR ROM

- 196 -

7 Sequential Circuit Design

The background bit of the OR ROM is logic 0. When a word line is selected, the
bit that has an n-MOS transistor would provide logic 1 at the bit line.
The 4x4 MOS NAND ROM is shown in Fig. 7.35. The background of the
ROM is logic 1. All the n-MOS transistors in the column have to be switched on
in order logic 0 is shown in bit line.

Figure 7.35: A 4x4 NAND ROM

ROM also can be designed using pseudo n-MOS gate both for the decoder and
the memory cell design, which is basically the n-MOS design technique. The
design example is shown in exercise 7.9. The logic to row or word is provided
by the pseudo n-MOS transistor, which act as decoder.

7.5 Flash Memory

Flash memory is a non-volatile memory that can be electrically erased and
reprogrammed. It is primarily used in memory cards and USB flash drives for
general storage and transfer of data between computers and other digital
products. It is a specific type of EEPROM that is erased and programmed in
large blocks. Example applications include PDAs, laptop computers, digital
audio players, digital cameras and mobile phones. It has also gained popularity
- 197 -

7 Sequential Circuit Design

in console video game hardware, where it is often used instead of EEPROMs or

battery-powered static RAM for game save data.
Flash memory cell using floating gate nonvolatile memory is shown in Fig.
7.36. It is a conventional memory that has a modified gate electrode. It has a
composite gate, which is control and floating gates. When a large positive
voltage is applied to the control gate, the charge will be injected from the
channel region through the gate oxide and store in the floating gate. Charge can
be removed by applying a large negative charge at the control gate. The charge
will be discharged back into the channel region.

Figure 7.36: Floating-gate nonvolatile memory

There are two types of flash memory namely the NOR flash and NAND flash.
In NOR gate flash, each cell has one end connected directly to ground and the
other end connected directly to a bit line as shown in Fig. 7.37. This
arrangement is called NOR flash because it acts like a NOR gate. When one of
the word lines is brought high, the corresponding storage transistor acts to pull
the output bit line low.

Figure 7.37: NOR flash memory

NAND flash also uses floating-gate transistors, but they are connected in a way
that resembles a NAND gate as shown in Fig. 7.3. Several transistors are
- 198 -

7 Sequential Circuit Design

connected in series and only if all word lines are pulled high, the bit line is
pulled low.

Figure 7.38: NAND flash memory

Exercises
7.1.

What is the difference between a combinational logic circuit and a

sequential circuit?

7.2.

Draw the VLSI layout of a simple D-latch.

7.3.

Draw the VLSI layout of a RS flip-flop.

7.4.

Describe how a basic D flip-flop as shown in Fig. 7.8 work.

7.5.

Describe how a logic 1 stored in the SRAM cell is read and interpreted by
the sense amplifier.

7.6.

Describe how the sense amplifier of DRAM works.

7.7.

Describe how a CVSL sense amplifier works.

7.8.

Design the layout of a column decoder as shown in Fig. 7.27.

7.9.

Determine the data stored in OR ROM shown in Fig. 7.34.

7.10. Determine the data stored in NAND ROM shown in Fig. 7.35.
7.11. A 4x4 ROM designed using pseudo n-MOS transistor concept is shown
in the figure below.
- 199 -

7 Sequential Circuit Design

(i).
(ii).

Derive the logic functions for the rows and output D3, D2, D1, and
D0.
Write down the content of the memory.

Bibliography
1.
2.
3.
4.
5.

Theodore F. Bogart Jr., Jeffrey S. Beasley, and Guillermo Rico,

Electronic Devices and Circuit, sixth edition, Prentice Hall, 2004.
John P. Uyemura, Introduction to VLSI Circuits and Systems, John
Wiley & Sons, Inc. 2002.
John P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic
Publishers, 2002.
M. Michael Vai, VLSI Design, first edition, CRC Press, 2000.
Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital
Integrated Circuits A Design Perspective, Second Eidtion, Prentice
Hall, 2003.

- 200 -