Experiment #3 - Introduction to Logic Gates

Experiment # 2

Introduction to Logic Gates

A. Objective

The main objective of this experiment is to study the working of the basic gates (AND, OR,
NOT) and verified the basic concepts of multiple inputs and propagation delay. Other gates
such as NAND, NOR, XOR will be examined.

B. Lab Lecture

https://www.youtube.com/watch?
v=D07IksUxL3I&list=PLoKOBYIH9linJYwL6vY8jUEK8FxtaE__1&index=2

C. Background

Binary logic consists of binary variables and logical operations. Each variable can have only
distinct possible values: 1 and 0. The basic logical operations are NOT, AND and OR.
These operations are represented by symbols, each symbols have inputs and output
variables. For each combination of the values of input variables (e.g X and Y), there is a
value of output Z specified by the definition of the logical operation, these definitions may
be listed in a compact form using truth tables. A truth table is a table of all possible
combinations of the variables showing the relation between the values that the input
variable may take and the result of operation.

AND: This operation is represented by a dot or by the absence of an operator, e.g.

X.Y=Z or X Y=Z, it read "X AND Y is equal to Z". This operation means that Z=1
if and only if X=1 and Y=1; otherwise Z=0.

OR: This operation is represented by a plus sign e.g. X+Y=Z, it reads "X OR Y is
equal to Z". This operation means that Z=1 if X=1 or Y=1 or both equal 1. If both
equal X=Y=0 then Z=0.

NOT: This operation is represented by prime ( some time by a bar ), e.g X=Z, it
reads " X NOT equal to Z", meaning that if X=1 then Z=0 but if X=0 then Z=1.

XOR: This operation is represented by plus inside circle e.g. X + Y =Z

NAND: This is an AND gate with inverted output.

NOR: This is an OR gate with a inverted output.

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 Experiment #3 - Introduction to Logic Gates

D. Data Sheet Specification of IC’s

a. DC Electrical Specifications

Data sheets give "worst case" values. "Worst case" is the manufacturer's guarantee of
performance. The worst case can be a minimum or maximum depending on which would
be less desirable. Typical values are sometimes given. These should be used for
comparisons only. Worst case values should be used when designing circuits

• High-level output voltage (VOH): the minimum voltage on the output pin when the input
condition establishes logic HIGH at the output.
• Low-level output voltage (VOL): the maximum voltage on the output pin when the input
condition establishes logic LOW at the output.
• Low-level input voltage (VIL): the maximum voltage applied at the input that is
recognized as a legal LOW level.
• High-level input voltage (VIH): the minimum voltage that needs to be applied at the input
to be recognized as a legal HIGH level.
• Output short circuit current (IOS): It is a troubleshooting technique to short a high level
output to ground temporarily to verify that a circuit is working correctly

b. DC Noise Immunity (Noise Margin)

It is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs
without changing its output state. In other words Noise margin is the maximum noise
voltage added to the input signal of a digital circuit that doesn't cause undesirable change in
the circuit output Noise margin is defines as the worst case difference between the low level
 Experiment #3 - Introduction to Logic Gates

input and output voltage, or between the high level input and output voltage. A large noise
margin is desirable

Example: What is the noise margin for 74HC00 and 74LS00?

Solution:
74HC with VCC = 4.7V, VOH = 4.4V, VOL = 0.1 V, VIH = 3.15V, VIL = 0.9 V
VNH = VOH – VIH = 4.4 – 3.15 = 1.75 V
VNL = VIL – VOL = 0.9 – 0.1 = 0.8 V
For a 74HC00, NM = smaller of {0.8 V, 1,75V} == 0.8V
For a 74LS00, NM = 0.2V

c. DC Fan-out

The "fan-out" of a logic gate refers to the maximum number of devices it can drive before
its output is loaded down to the point where logic levels are unrecognizable, or where the
logic levels begin to fall in the prohibited range. Since the current draw is different for logic
high and logic low levels, the fan out for each level must be calculated

The effect of loading an output with more than its rated fan-out is to increase its LOW-state
output voltage and decrease its HIGH-state output voltage. Because of TTL's DC noise
margins, a slightly overloaded circuit will still work in noise-free conditions, but of course
the noise margins are reduced.
Example: How many SN74ALS06 inputs can be driven by a single SN74LS00 output?
Solution:
The SN74ALS06 is the input chip whose IIL is -0.1mA, and IIH is 0.02mA. The
SN74LS00 is the output chip whose IOL is 8mA, and IOH is -0.4mA. Note that the
direction of the currents (their positive or negative sign) is ignored.
Fan-out Low = 8mA/.1mA = 80
Fan-out High = 0.4mA/0.02mA = 20
Because you don't want a current to exceed a specification that could damage an IC, choose
the lowest number. The number of SN74ALS06 inputs that can be driven by one
SN74LS00 is 20
 Experiment #3 - Introduction to Logic Gates

d. Switching Characteristics
• tPHL (propagation delay high to low): time delay between a specified level on the input
waveform and a specified level on the output waveform going low.
• tPLH (propagation delay low to low): time delay between a specified level on the input
waveform and a specified level on the output waveform going high.
• Propagation time delay (tD or tPD): the average delay of tPHL and tPLH

e. Power Requirements

Real ICs consume energy to operate. This energy is not used for external useful work. It is
wasted as heat. Typically, we would like this to be as small as possible. Power requirements
vary the most between logic families. IC power consumption is measured as Icc * Vcc with
outputs open. A 5 W power source can supply 100 74LS ICs at 50 mW each.

f. Vcc Ranges

TTL ICs are typically powered from a 5.00 V, +/- 5% source. The specified range of
operation for a 74LS00 is 4.75 V to 5.25 V. Correct operation is not guaranteed outside of
this range. HC devices can operate with a large range of supply voltages. Typically: 2.0 V
<Vcc < 6.0 V. Two, 3, or 4 AA batteries can supply several ICs. A phenomenon associated
with TTL devices is current spiking. When the output of a TTL device is HIGH, a constant
supply current ICCH is drawn from the power supply by the IC. When the output is LOW,
a constant supply current ICCL is drawn from the power supply. For a 7400 NAND gate,
ICCH = 4 mA and ICCL = 12 mA per IC. However, when the gate output changes state, a
short burst of current is drawn during the transition. The result is current spikes (narrow
pulses) in the power supply line. The largest spike occurs in the LOW to HIGH transition.
To prevent these current spikes from corrupting the power supply and ground and thus
appearing as noise, one decoupling capacitor (0.01 μF to 0.1 μF) for each five to ten IC
packages are generally connected from power to ground near the IC pins.

it was mentioned that the power supply should never be connected directly to gate inputs as
the gate could be destroyed if the input voltage ever exceeded the supply voltage to the IC: a
virtually unlimited amount of current is then allowed to flow backwards through the IC.
Current spiking can lead to just such a situation if power were connected directly to a gate's
inputs. Thus, another TTL gate should always be used to provide a constant HIGH voltage
if required.

D. Procedure
 Experiment #3 - Introduction to Logic Gates

PART-1: Operation of basic gates

A- The AND gate

1. Insert a 7408 quad ( four in one package ) 2-input AND gate into breadboard,
study its schematic diagram from its application sheet.

2. Wire as shown in fig.(1), connect pin 14 as usual to +5V, pin 7 to common

(GND).

3. Set the data switches to the different combinations to verify its truth table and
observe its output.

4. Construct the two level 3-input AND gate which implement the function
F=(AB)C or A.B.C using the 2-input AND gates. Study its truth table and verify
its output logic operation.

B- The OR gate

1. Insert a 7432 quad 2-input OR gate into the logic breadboard

2. Follow the above procedure (2-4) with 7432, as shown in fig(2)

C- The NOT gate

 Experiment #3 - Introduction to Logic Gates

1. insert the 7404 HEX invertor (six in one package) into the logic breadboard.

2. Connect it as shown in fig (3). Set the input to high and low and observe its
output (varify its truth table).

3. Construct a series of NOT gates as shown in fig.(4), connect the input of the
first gate to switch and the output of second gate (pin#4) to LED. Varify its truth
table

C- NAND gate

1. Insert a 7400 quad 2-input NAND gate, connect one of its gate as shown in fig.(5),
set the data switches for its input, verify its truth table (you may note that the NAND
is equivalent to a cascaded AND-NOT gates)

2. Connect the two inputs of or gate of 7400, shown in fig (6) to one data switch, set
the data switch to different contributions and verify the truth table. You may note
that the two connected input of the NAND is acting like an inverter.
 Experiment #3 - Introduction to Logic Gates

3. Construct the three level, 3-input NAND gate which implements the function f=
ABC as shown in fig (7), verify its truth table.

E- NOR gate

1. Insert a 7402 quad 2-input NOR gate into the logic breadboard

2. Follow the above procedure for the NOR gate according to the shown fig. (8).

3. Keep one of the input wires floating and check the output. Is the floating input
considered low or high for the gate output?

F- XOR gate
 Experiment #3 - Introduction to Logic Gates

1. Insert a 7486 quad 2-input XOR gate into the logic breadboard

2. Follow the above procedure for the NOR gate according to the shown fig. (9).

3. Keep one of the input wires floating and check the output. Is the floating input
considered low or high. for the gate output

PART-2: Truth tables of logic circuits

Connect the circuits of figure 10 and write the corresponding truth tables
 Experiment #3 - Introduction to Logic Gates

Questions
1. How many 2-input AND gate required to construct a 5-input AND gate?

a) 2 b) 3 c) 5 d) 4 e) none

2. Which is better for a 4-input AND gate. The connection of A or B, F why?

a) A b) B

3. If only 2-input OR gates are available, what is minimum gate level possible to
implement an 8-input OR gate 2.

a) 2 b) 3 c) 4 d) 6 e) 7

4. What is the propagation delay for Cout of the following circuit?

a) 30 ns b) 45 ns c) 35 ns d) 10 ns e) 20 ns

5. How many gates are loaded by gate A output?

a) 1 b) 2 c) 9 d) 16 e) 64

6. In the same fig. of question 5 how many gates input does gate A control?
 Experiment #3 - Introduction to Logic Gates

a) 1 b) 2 c) 9 d) 16 e) 64

7. If the fan-out of gate A is 10, can we connect the 16 input gate together directly
to A (without using the two series inverter), see above Figure.

a) True b) false c) undetermined

8. If a three NAND gate had two-inputs connected to +5Volts and the third input to
A. The output would be

a) A b) A c) high d) low

9. How many output states does a 3-input OR or AND or NOT gate have?
a) 1 b) 2 c) 3 d) 4 e) not determined

10. If one input to a NOR gate is high and the other inputs are unknown (may be
high or low), the output is
a) Low b) High c) Undetermined d) illegal combination

11. Construct a 3-input NOR circuit using only 2-input NOR gates?

12. Write a truth table for each circuit.

 Experiment #3 - Introduction to Logic Gates

Design Problem:

13. A burglar alarm for a car has a normally low switch on each of four doors. If
any door is opened the output of that switch goes HIGH. The alarm is set off
with an active-LOW output signal. What type of gate will provide this logic?
Support your answer with an explanation.

14. Write the equation of the alarm of a car that set when you are in the car and
it’s running and you didn’t put the belt assuming the following variables:

X=1 when you are in the car

Y=1 when the car is off
Z=1 when you put the belt
F=1 when alarm is on