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  • Assignment-1: Experiment:1

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    Ramadevi Daggubati
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    This document describes 4 experiments conducted in a digital logic design class. The experiments involve designing basic logic gates like AND, OR and XOR gates; half adders and full adders; multiplexers; and a single bit comparator using Verilog code in Vivado 2016.1 software. For each experiment, the design specifications, requirements, algorithms, code, simulation waveforms and RTL views are documented. The observations note that basic gates cannot be used directly as outputs, wires are needed for intermediate terms, and inputs must be given in the same order for full adders and multiplexers built using lower level components.

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    This document describes 4 experiments conducted in a digital logic design class. The experiments involve designing basic logic gates like AND, OR and XOR gates; half adders and full adders; multiplexers; and a single bit comparator using Verilog code in Vivado 2016.1 software. For each experiment, the design specifications, requirements, algorithms, code, simulation waveforms and RTL views are documented. The observations note that basic gates cannot be used directly as outputs, wires are needed for intermediate terms, and inputs must be given in the same order for full adders and multiplexers built using lower level components.

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    10 views18 pages

    Assignment-1: Experiment:1

    Uploaded by

    Ramadevi Daggubati
    This document describes 4 experiments conducted in a digital logic design class. The experiments involve designing basic logic gates like AND, OR and XOR gates; half adders and full adders; multiplexers; and a single bit comparator using Verilog code in Vivado 2016.1 software. For each experiment, the design specifications, requirements, algorithms, code, simulation waveforms and RTL views are documented. The observations note that basic gates cannot be used directly as outputs, wires are needed for intermediate terms, and inputs must be given in the same order for full adders and multiplexers built using lower level components.

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    © All Rights Reserved
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    of 18

    Date:22/08/2017 ID NO:N140263

    Roll no:33
    Class: SS-09
    ECE :03
    ASSIGNMENT-1
    EXPERIMENT :1
    BASIC GATES VERIFICATION
    1.AND GATE
    2. OR GATE
    3. EX-OR GATE

    DESIGN SPECIFICATIONS:
    We designed the AND,OR,EX-OR gates by using VIVADO 2016.1
    software
    REQUIREMENTS:-
    Xilink Vivado 2016.1 software
    AND
    OR,
    EX-OR
    ALGORITHM:
    If(a=1and b=1)
    Y1=1;
    Else
    Y1=0;
    Or gate:
    If(a=0 and b=0);
    Y2=0;
    Else
    Y2=1;
    X0R Gate:
    If(a==b)
    Y3=0;
    Else:
    Y3=1;
    CODE:
    AND GATE:

    OR GATE:

    EX-OR GATE:
    SIMULATION WAVEFORMS:

    AND

    RTL VIEW:
    PROJECT SUMMARY

    OR GATE:
    RTL

    VIEW:

    PROJECT SUMMARY:
    EX-OR GATE:
    RTL VIEW:

    PROJECT SUMMARY:
    EXPERIMENT:2
    1.Design of half adder
    2.Design of full adder using half adders

    DESIGN SPECIFICATIONS:
    We designed the HALF ADDER and FULL ADDER by using VIVADO
    2016.1 software
    REQUIREMENTS:-
    Xilink Vivado 2016.1 software
    AND
    OR,
    EX-OR

    CODE:
    HALF ADDER:

    FULL ADDER:

    SIMULATION WAVEFORMS:
    HALF ADDER
    FULL ADDER:

    RTL VIEW:
    HALF ADDER
    FULL ADDER:

    EXPERIMENT:3

    1.Design of 2:1 mux


    2.Design of 4:1 mux using 2:1 mux

    DESIGN SPECIFICATIONS:
    We designed the 2:1 mux and 4:1 mux by using VIVADO 2016.1 software
    REQUIREMENTS:-
    Xilink Vivado 2016.1 software
    AND
    OR,
    not gates

    Algorithm:
    2:1 MULTIPLXER:
    Input s, a ,b;
    Output y;
    If(~s)
    Y=a;
    Else
    Y=b;
    4:1 MULTIPLEXER

    Input a ,b ,c;
    Output sum,car;
    If(a=0 &b=0)
    Sum=c;
    Car=0;
    Else If(a=0&b=1)
    Sum=c’;
    Car=c;
    Else If(a=1&b=0)
    Sum=c’;
    Car=c;
    Else
    Sum=c;
    Car=1;

    CODE:

    2:1 mux
    4:1 mux

    SIMULATION WAVE FORMS:


    2:1 MUX

    4:1

    MUX
    RTL VIEW

    2:1 MUX
    4:1 MUX

    EXPERIMENT:4

    1.Design of SINGLE BIT COMPARATOR


    DESIGN SPECIFICATIONS:
    We designed the SINGLE BIT COMPARATOR by using VIVADO
    2016.1 software
    REQUIREMENTS:-
    Xilink Vivado 2016.1 software
    AND
    EX-NOR,
    not gates

    CODE:

    SIMULATION WAVE FORM:


    RTL VIEW
    OBSERVATIONS:
    By using Verilog code we can implement a gate level circuit and
    timing diagram and can implement complex circuits also.
    Basic gates are the inbuilt functions should not be given at the output.
    first we declare the output , and after we give the inputs we don’t give in
    this manner we get error, and don’t get the output.
    I observe that intermediate terms we declare by using wire, other wise
    we get error and don’t get the outputs.
    I observe that fulladder by using half adder if you give the inputs in half
    adder the same order give the inputs in fulladder otherwise get error and
    don’t get the output.Like wise in 4:1 mux using 2:1 mux.

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