DIGITAL LOGIC DESIGN LAB REPORT

SUBMITTED BY:
M. ANAS YUSUF
AMIN QURESHI
ARIJ NIAZ

REGISTRATION NUMBER:
FA22-BEE-136
FA22-BEE-135
FA22-BEE-139

SUBMITTED TO:

DIGITAL LOGIC
SIR NOMAN AHMED

DATE OF SUBMISSION:

DESIGN LAB
29TH MARCH, 2023

REPORT
LAB REPORT 3
 DIGITAL LOGIC DESIGN LAB REPORT

LAB # 03: Introduction to Verilog and Simulation using

XILINX ISE

VERILOG
Verilog is a hardware description language (HDL) which is used to design digital circuits, and
used in the verification of these circuits as well. Its syntax is similar to C/C++ languages. Xilinx
ISE is the simulation tool for Verilog.

XILINX ISE 14.5

➢ STEP-WISE PROCEDURE
1. Firstly, create a new project in ISE Design Suite. Set the following project specifications
(Figure 1):
• Family to Spartan3E
• Device to XC3S500E
• Package to FG320
• Speed to -4
2. Then create New Source of Type Verilog Module and give port names (Figure 2).
Press Finish and a module will form.
3. Then, type in the code for solving the provided function in the module.

Figure 1 Figure 2

➢ CODE
Explanation:
For the desired circuit, we required 4 inputs (in0, in1, in2,
in3) and 1 output (outf). We required 2 AND and 2 OR
logic gates. a, b, c are wires that connect the internal
outputs of gates.
a is assigned the result of AND gate on in0 and in1. b is assigned the result of OR gate
on a and in2. Whereas c is assigned the result of AND gate on in2 and in3. Final output
is calculated by applying OR gate on b and c wires.
 DIGITAL LOGIC DESIGN LAB REPORT

➢ TEST BENCH
1. For adding test bench file, create New Source of Type Verilog test fixture and enter file
name in format “TB_Module_Name”. (Figure 3)

Figure 3
2. Then, assign various values to the input variables for testing the main module (Here there
will be 16 combinations as 4 inputs are involved.). (Figure 4.1, 4.2)

Figure 4

Figure 4.1 Figure 4.2

➢ RESULTS
Timing diagram Schematic diagram

PROTEUS
➢ PROCEDURE
1. Search and select AND GATE (2 inputs), OR GATE (2 inputs), LOGICSTATE (for
input), and LED-RED (for output) from the Pick Device Menu.
2. Select and drop the tools on the circuit window.
3. Make required connections between AND gate, OR gate, 2 logic states and 1 LED.
 DIGITAL LOGIC DESIGN LAB REPORT

4. From Terminal Mode, select and connect GROUND to the end of LED (whose one end
is already connected to the OR gate); to complete the circuit.
5. Now, run the simulation and verify the results of truth table by changing the values (0
and 1) of logic states.

➢ CIRCUIT DIAGRAM:

Figure 5

Figure 6

Diagram Explanation:
These are two cases out of 16 cases. Figure 1 shows when all 4 inputs are OFF (0), the
output is also OFF (0). Whereas, Figure 2 shows when 2nd and 3rd inputs are ON (1) and
rest are OFF (0), output is ON (1). Other cases can also be verified in this way.

➢ PRECAUTIONS
ISE Simulator:
1. Ensure voltage coming from main power supply is 220.
2. Give files appropriate names, so they can be distinguished easily.
3. Must save the results so they can be reused later on.
4. While creating new project, make sure the correct specifications are set for ISE Design
suite to work properly.

Proteus:
1. Make sure the library files of Proteus are installed.
2. Make sure that correct device (2 input values) is picked from the PICK DEVICE menu.
3. The circuit must be grounded, to complete the circuit.
 DIGITAL LOGIC DESIGN LAB REPORT

COCLUSION (FA22-BEE-136) :-
The goal of the lab on "Introduction to Verilog and Simulation with XILINX
ISE" is to show us how to describe and simulate hardware with the Verilog language. Additionally,
the use of Xilinx ISE, an Integrated Development Environment (IDE) for designing and simulating
digital circuits, is the focus of the lab. The Verilog syntax, data types, operators, and control
structures are all explained in depth in the lab. Additionally, it discusses port mapping, instantiation,
and the use of modules, all of which are fundamental Verilog programming concepts. Verilog code
for a variety of digital circuits, including combinational and sequential ones, can be seen in several
examples in the lab. The models are very much made sense of and assist us with figuring out the
commonsense utilization of Verilog. Additionally, the laboratory could benefit from more difficult
Verilog code examples. While the provided examples are helpful for comprehending the
fundamentals of Verilog, more complex examples would assist us in further developing our skills.

COCLUSION (FA22-BEE-135) :-
In this lab we have observed the ISE enables the developer to synthesize
("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's
reaction to different stimuli, and configure the target device with the programmer. Xilinx's patented
algorithms for synthesis allow designs to run up to 30% faster than competing programs and allows
greater logic density which reduces project time and costs.

COCLUSION (FA22-BEE-139) :-
In this lab, we designed a simple digital circuit using Verilog and simulated
the circuit using Xilinx ISE. We verified that the output values were consistent with the behavior
described by the Verilog code. This exercise demonstrates the use of Verilog and Xilinx ISE for
designing and testing digital circuits. We have faced some problems like it showing 1 on every logic
and we tackled this problem by zooming out on the screen.