DIGITAL LOGIC DESIGN LAB MAY 20, 2023

SUBMITTED BY:
AMIN QURESHI (FA22-BEE-135)
ARIJ NIAZ (FA22-BEE-139)
ANAS YUSUF (FA22-BEE-136)

SUBMITTED TO:
MR. NUMAN AHMED

DATE OF SUBMISSION:
20TH MAY, 2023

DIGITAL LOGIC
DESIGN LAB
LAB REPORT 8
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

LAB # 08: Design and Implementation of n – bit Binary

Multiplier on FPGA
1. BINARY MULTIPLIER
A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply
two binary numbers. It is built using binary adders. A variety of computer arithmetic techniques can
be used to implement a digital multiplier. Most techniques involve computing a set of partial
products, and then summing the partial products together.

2. HALF/FULL ADDER
Full Adder is used to find the sum of 2 binary numbers. It contains 3 inputs (2 bits of each number
from right to left and 1 carry bit) and 2 outputs (1 being sum bit and other carry bit). The output

carry is used as input carry for the next pair of binary digits in order.
Half Adder is same like Full Adder. The only difference is that Half Adder takes 2 input bits of
binary numbers and does not use the carry bit to produce accurate required outputs.
3. BINARY MULTIPLIER (2x2)

 STEP-WISE PROCEDURE
1. Firstly, create a new project in ISE Design Suite. Set the following
project specifications (Figure 1):
 Family to Spartan3E
 Device to XC3S500E
 Package to FG320
 Speed to -4
2. Then create New Source of Type Verilog Module
and give port names. Press Finish and a module will
form.
3. Then, type in the code required for creating a 2x2
Binary multiplier.

Figure 1
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

1. HALF ADDER MODULE CODE

3.1.1. Explanation:
Half Adder module consists of 2 inputs x, y and 2 outputs s, cout. x and y are pair of bits of some
2 bit binary numbers. s and cout are output sum bit and carry bit respectively.
sum and cout’s equations extracted from truth table are written using gate instantiation. XOR and
AND gates are applied on x, y and results are stored in s and cout respectively.
3.1.2. Test Bench:
1. For adding test bench file, create New Source of Type Verilog test fixture and
enter file name in format “TB_Module_Name”.
2. Then, assign various values to the input variables for testing the module (Here there

Figure 2
will be 4 combinations as 2 inputs are involved.). (Figure 2)
3.2.MAIN MODULE CODE

3.2.1. Explanation:
2 2-bit registers and 1 4-bit wire are declared for input of 2 2-bit numbers and output of
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

multiplication respectively. Sequentially, we’ll pick pairs of bits of a and b from right to left like we
do for multiplication. (0-1 being their n index values).
B[0] and B[1] will multiply with A[0] and A[1]. A[0]*B[0] result will be directly stored in output M[0],
whereas the rest will be stored in wire in[0], in[1], in[2] to be used in HA modules.
After getting values in wires, HA module will be called and respective registers and wires will be
passed to add 2 bits to finally generate a 4-bit binary output of 2x2 binary multiplication.

3.3. RESULTS

Timing diagram

Schematic diagram

4. BINARY MULTIPLIER (4x3)

 STEP-WISE PROCEDURE
1. Firstly, create a new project in ISE Design Suite. Set the following project specifications
(Figure 1):
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

 Family to Spartan3E
 Device to XC3S500E
 Package to FG320
 Speed to -4
2. Then create New Source of Type Verilog Module
and give port names. Press Finish and a module will
form.
3. Then, type in the code required for creating a 4x3
Binary multiplier.
4.1. FULL ADDER MODULE CODE Figure 1

4.1.1. Explanation:
Full Adder module consists of 3 inputs x, y, cin and 2 outputs sum, cout. x, y and cin are pair of
bits of some 2 binary numbers. cin is input carry bit. sum and cout are output sum bit and
carry bit respectively. sum and cout’s equations extracted from truth table are used. ^ is XOR gate,
& is AND gate and | is OR gate.
cct module is Full Adder/Subtractor module used on Adder mode (m=0) to get 4 bit sum output
when 4 bit inputs are passed to it.
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

4.2. MAIN MODULE CODE

4.2.1. Explanation:
2 registers of 4 and 3-bit, and 1 7-bit wire are declared for input of 4 bit and 3 bit binary number
and output of multiplication respectively. Sequentially, we’ll pick pairs of bits of a and b from right to
left like we do for multiplication. (0-4 being their n index values).
B[0], B[1], B[2] will multiply with A[0], A[1], A[2], A[3]. A[0]*B[0] result will be directly stored in
output M[0]; A[1]*B[0]+A[0]*B[1] will be stored in M[1], whereas the rest will be stored in wires
a1,b1, a2, b2 to be used in FA modules.
After getting values in wires, FA module will be called and respective registers and wires will be
passed to add 2 4-bit numbers and 1 1-bit carry bit to finally generate an 8-bit binary output of 4x3
binary multiplication. 2 FA modules will be called as addition is being done in 2 stages.
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

4.2.2. Test Bench:

4.3. RESULTS Timing diagram

Schematic diagram

Schematic diagram
DIGITAL LOGIC DESIGN LAB MAY 20, 2023

5. CONCLUSION
AMIN QURESHI (FA22-BEE-135)

the design and implementation of an n-bit binary multiplier on an FPGA combine the power of
hardware description languages, digital logic design methodologies, and reconfigurable hardware
to deliver a versatile and high-performing solution for multiplication tasks in binary arithmetic. It
stands as a fundamental component in digital systems, contributing to enhanced computational
capabilities and paving the way for further advancements in various domains of technology and
engineering.
ANAS YUSUF (FA22-BEE-136)
In conclusion, hardware description languages and digital logic design methodologies are used in
the design and implementation of an n-bit binary multiplier on an FPGA (Field-Programmable Gate
Array). A binary multiplier may effectively perform multiplication tasks in binary arithmetic by using
the right algorithm and optimising the circuitry. The design can be modified and tailored for different
purposes thanks to the flexibility of reconfigurable hardware made possible by the use of an FPGA.
The n-bit binary multiplier can be used to perform multiplication operations more quickly and
effectively, which makes it an important part of digital systems and computational jobs.
ARIJ NIAZ (FA22-BEE-139)
In essence, the utilization of hardware description languages and digital logic design methodologies
is paramount in the creation and execution of an n-bit binary multiplier on an FPGA. By employing
the right algorithm and optimizing the circuitry, this multiplier performs multiplication operations
swiftly and effectively within binary arithmetic. The adaptability of reconfigurable hardware, made
possible by utilizing an FPGA, allows for tailoring and customization of the design to cater to
various needs. As a result, the n-bit binary multiplier assumes a vital role in digital systems and
computational endeavors, facilitating rapid and efficient execution of multiplication tasks.

6. PRECAUTIONS
1. Ensure voltage coming from main power supply is 220 V.
2. Give files appropriate names, so they can be distinguished easily.
3. Must save the results so they can be reused later on.
4. While creating new project, make sure the correct specifications are set for ISE Design
suite to work properly.
5. Make sure correct logic gates are used to replicate the canonical form in Verilog code.
6. When passing values to a module, make sure inputs and outputs are in the correct order.