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  • Not Dmux

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    deepak negi
    3 views12 pages
    The document discusses VHDL code, schematic designs, and simulations for common digital logic gates and circuits including NOT, AND, OR, NAND, NOR, XOR gates as well as half adder, full adder, half subtractor, full subtractor, 4x1 multiplexer, and 4x1 demultiplexer. For each logic element, it provides the VHDL code, schematic, and simulation results.

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    SR Flip flop

    Original Title

    not-dmux

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    The document discusses VHDL code, schematic designs, and simulations for common digital logic gates and circuits including NOT, AND, OR, NAND, NOR, XOR gates as well as half adder, full adder, half subtractor, full subtractor, 4x1 multiplexer, and 4x1 demultiplexer. For each logic element, it provides the VHDL code, schematic, and simulation results.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    3 views12 pages

    Not Dmux

    Uploaded by

    deepak negi
    The document discusses VHDL code, schematic designs, and simulations for common digital logic gates and circuits including NOT, AND, OR, NAND, NOR, XOR gates as well as half adder, full adder, half subtractor, full subtractor, 4x1 multiplexer, and 4x1 demultiplexer. For each logic element, it provides the VHDL code, schematic, and simulation results.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 12

    VHDL code for NOT Gate:

    Schematic Design and RTL Design:

    Simulation of NOT- Gate:


    VHDL code for AND Gate:

    Schematic Design and RTL Design:

    Simulation of AND- Gate:


    VHDL code for OR-Gate:

    Schematic Design and RTL Design:

    Simulation of OR- Gate:


    VHDL code for NAND Gate:

    Schematic Design and RTL Design:

    Simulation of NAND- Gate:


    VHDL code for N0R Gate:

    Schematic Design and RTL Design:

    Simulation of N0R- Gate:


    VHDL code for EX-0R Gate:

    Schematic Design and RTL Design:

    Simulation of EX-0R- Gate:


    VHDL code for Half Adder:

    Schematic Design and RTL Design:

    Simulation of Half Adder:


    VHDL code for Full Adder:

    Schematic Design and RTL Design:

    Simulation of Full Adder:


    VHDL code for Half-Subtractor:

    Schematic Design and RTL Design:

    Simulation of Half-Subtractor:
    VHDL code for Full-Subtractor:

    Schematic Design and RTL Design:

    Simulation of Full-Subtractor:
    VHDL code for 4x1 Multiplexer:

    Schematic Design :

    Simulation of 4x1 Multiplexer:


    VHDL code for 4x1 Demultiplexer:

    Schematic Design :

    Simulation of 4x1 Demultiplexer:

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