CS312

USN M

M S RAMAIAH INSTITUTE OF TECHNOLOGY

(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU) BANGALORE - 560 054

SEMESTER END EXAMINATIONS - JANUARY 2011

Course & Branch : Subject : Subject Code : BE. - Computer Science and Engineering Semester: III Digital Design with VHDL Max. Marks: 100 - CS312 Duration: 3 Hrs

Instructions to the Candidates:

Answer one complete question from each unit.

UNIT-I 1. a) Determine if the equation; is valid (02)

xl x3 + x2x3 + xlx2 = xlx2{+ xIx3 + x2x3.

b) Find the minimum-cost sop & pos forms for the function (04) f(x1, x2,x3,x4)=Em(1,2,3^'5)
c) Write VHDL code to describe the following (06) f = xlx3 +x2x3.+x3x4 +xlx2 +xlx4
g = (xl + x3)(xl + x2 + x4)(x2 + x3 + x4 )

d) Using tabular method obtain the prime implicants of the following function (08) f (xl, x2, x3, x4) - Em(0,2,5,6,7,8,9,13) + D(1,12,15) 2. a) Obtain the logic diagram 'using only NAND gates, (04)

f(x, y,Z) = xy+ y(Z+x)+xz

Write a VHDL code for the following circuit diagram. (04)
U

c) Use . tabular method and table reduction to derive a minimum cost sop (12) expression for the function.

f (w, x, y, z) = Em(1,6,7,9,11,14,15) + dc(8,10)

UNIT-II 3. a) Explain a 4-bit parallel adder with the carry look ahead scheme. Clearly (10)

indicate how this scheme improves the performance of the operation. b) With the aid of block diagrams clearly distinguish between a decoder and (05) encoder. c) Give a 4 to 1Mux implementation of the function f = w, w2 w3 (05)

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4. a) Show the implementation using 3 to 8 binary decoder and an or gate for the following function. (04)

f (w,,w2,w3) = Em(0,2,3,4,5,7)
b) c) Design a multiplex tree to form a 16 to 1 line multiplexer using 4 to 1 line multiplexers. Write VHDL code for a 4 to 2 priority encoder using conditional signal statement. UNIT-111 Explain the operation of Basic latch (with NOR gates) with a circuit, characteristic table and timing diagram. Write VHDL code for D-Flip Flop using process statement. Design a 4-bit ring counter using d Flip Flops. Design a two-digit BCD counter using D Flip Flops. What is a shift register? Design and explain a 4-bit shift register using D Flip flops. Write count table and timing diagram. UNIT-IV A Finite State Machine (FSM) is defined by the state assigned table in fig. 7(a). Derive a circuit that realizes this FSM using D Flip Flops. Next State W=0 W=1 Y2 Y1 Y2Y1 10 11 01 00 11 00 ` 10 01 O/p 0 0 0 1 (08) (08)

5.

a) b) c)

(08) (05) (07) (10)

6.

a)

b)

(10)

7.

a)

(10)

Present State 00 01 10 11

Fig. 7(a) b) What is serial adder? Explain Mealy-type FSM for serial adder. 8. a) Design a module - 6 counter which counts in the sequence 0,1,2,3,4 ,5,0,1,... The counter counts the clock pulses' if its enable input , w is equal to 1. Use D Flip Flops in the circuit. Show a state table for the state - assigned table in figure 8 ( b), using A,B,C,D for the four rows in the table ; for A use the code y4Y3Y2Y1= 0001 . For B,C,D use 0010,0100 and 1000 respectively. Synthesis a circuit using D Flip Flops. Give a new state-assigned table using one - hot encoding.

Next State
Present State 00 01 10 11 W=O W=1
Y2Y1 Y2Y1

O/p

z
0 0 0 1

10 01 11

11 00 00

10 01
Fig. 8(b)

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'I UNIT-V 9. a) A circuit has an input w and an output z. a sequence of pulses is applied on (10) input w. The output has to!replicate every second pulse as shown in

figure 9(a). Design a suitable circuit. I

Fig. 9(a) b) Derive a flow table that describes the behavior of the circuit in figure 9(b). (10)

Fig. 9(b) 10. a) Discuss the analysis of Gated D latch with circuit, excitation table, flow table (12) and state diagram. b) Consider the circuit in figure 10(b). sensitize each path in this circuit to (08) obtain a complete test set that comprises a minimum numbers of tests.

Fig. 10(b)

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