UNIVERSITY OF PONDICHERY

DEPARTMENT OF ENGINEERING
BENG(HONS) ELECTRICAL AND ELECTRONICS ENGINEERING
ELECTRONICS SYSTEM DESIGN
LAB REPORT

Contents
Contents...............................................................................................................................................2
DESIGN FILE.....................................................................................................................................3
Results.................................................................................................................................................3
LAB 2 : 3 Bit Down Counter..............................................................................................................4
DESIGN FILE.....................................................................................................................................4
Results.................................................................................................................................................5
LAB 3 : 3 Bit Ring Counter................................................................................................................5
Design File..........................................................................................................................................5
Results.................................................................................................................................................6
LAB 4 : Ramdom Pattern Generator...................................................................................................6
Design File..........................................................................................................................................6
Results.................................................................................................................................................7
LAB 5 : Even/Odd Parity Checker.....................................................................................................7
DESIGN FILE.....................................................................................................................................7
Results.................................................................................................................................................8
LAB 6 : Sequence Detector.................................................................................................................8
Design File..........................................................................................................................................8
Results.................................................................................................................................................9
LAB 7 : Vending Machine..................................................................................................................9
Design file...........................................................................................................................................9
LAB 8 : Traffic light controller.........................................................................................................12
Design file.........................................................................................................................................12
Results...............................................................................................................................................13
Simulation.........................................................................................................................................14

LAB

BIT

BINARY

TO

GRAY

CODE

MAPPING
DESIGN FILE
/* *************** INPUT PINS *********************/
PIN

I0

; /*

*/

PIN

I1

; /*

*/

PIN

I2

; /*

*/

PIN

I3

; /*

*/

/* *************** OUTPUT PINS *********************/

PIN

12

Z0

; /*

*/

PIN

13

Z1

; /*

*/

PIN

14

Z2

; /*

*/

PIN

15

Z3

; /*

*/

FIELD INPUT=[I3..I0];
FIELD OUTPUT= [Z3..0] ;

TABLE INPUT=>OUTPUT {
'b'0000=>'b'0000;
'b'0001=>'b'0001;
'b'0010=>'b'0011;
'b'0011=>'b'0010;
'b'0100=>'b'0110;
'b'0101=>'b'0111;
'b'0110=>'b'0101;
'b'0111=>'b'0100;
'b'1000=>'b'1100;
'b'1001=>'b'1101;
'b'1010=>'b'1111;
'b'1011=>'b'1110;
'b'1100=>'b'1010;
'b'1101=>'b'1011;
'b'1110=>'b'1001;
'b'1111=>'b'1000;
}

Results

LAB 2 : 3 Bit Down Counter

DESIGN FILE
PIN 1= CLK;
PIN [12..14]=[Q2..0];

FIELD STATES = [Q2..0];

$REPEAT I = [0..7]
$DEFINE S{I} 'b'{I}
$REPEND

SEQUENCE STATES {
PRESENT S0
NEXT S7;
PRESENT S7
NEXT S6;
PRESENT S6
NEXT S5;
PRESENT S5
NEXT S4;
PRESENT S4
NEXT S3;
PRESENT S3
NEXT S2;
PRESENT S2
NEXT S1;
PRESENT S1
NEXT S0;
}

Results

LAB 3 : 3 Bit Ring Counter

Design File
Name

lab2 ;

PartNo

00 ;

Date

17-Feb-13 ;

Revision 01 ;
Designer Engineer ;
Company

Home ;

Assembly None ;
Location
Device

;
g16v8 ;

PIN 1 = CLK;

PIN [12..14] = [Q2..0];

FIELD STATES = [Q2..0];

$repeat i=[0..7]

$define S{i} 'b'{i}

$repend

SEQUENCE STATES {
PRESENT S1
NEXT S2;
PRESENT S2
NEXT S4;
PRESENT S4
NEXT S1;
PRESENT S3
NEXT S1;
PRESENT S5
NEXT S1;
PRESENT S6
NEXT S1;
PRESENT S7
NEXT S1;
PRESENT S0
NEXT S1;
}

Results

LAB 4 : Ramdom Pattern Generator

Design File
pin 1 = clock;
pin [12..14]=[q2..0];

field states = [q2..0];

$repeat i=[1..7]
$define s{i} 'b'{i}
$repend
sequence states {
present s1 next s4;
present s4 next s2;
present s2 next s5;
present s5 next s6;
present s6 next s7;
present s7 next s3;
present s3 next s1;
}

Results

LAB 5 : Even/Odd Parity Checker

DESIGN FILE
pin 1 = clk;
pin 2 = x;
pin [12,13] = [q1..0];
pin 14 = z;
field state=[q1..0];
$define s0 'b'00
$define s1 'b'01
$define s2 'b'10
sequence state {
present s0
if !x next s1 out !z ;
if x next s2 out z;

present s1
if !x next s1 out !z ;
if x next s2 out z;
present s2
if !x next s2 out z;
if x next s1 out !z;

Results

X is the input and y the output. Output goes to 1 if an odd number of 1 in input is detected. At
vector 4 x=1, hence z=1 until another x=1 is input. At vector 9 x=1 hence even number of 1 thus
output goes to 0.

LAB 6 : Sequence Detector

Design File
pin 1= clk;
pin 2=x;
pin [12..14]=[q2..0];
pin 15 =z;

field states= [q2..0];

$repeat i= [0..5]
$define s{i} 'b'{i}
$repend

sequence states {
present s0
if !x next s1 out !z;
if x next s2 out !z;
present s1

if !x next s1 out !z;

if x next s3 out !z;
present s2
if !x next s1 out !z;
if x next s4 out z;
present s3
if !x next s5 out z;
if x next s4 out z;
present s4
if !x next s1 out !z;
if x next s4 out z;
present s5
if !x next s1 out !z;
if x next s3 out !z;
}

Results

X represents the input and z the output. At vector 4 a 010 sequence is detected hence z goes to 1.
At vector 9 and 10 sequence of 11 is detected (overlapping considered) and output goes high.

LAB 7 : Vending Machine

Design file
pin 1 = clock;
pin [2,3]=[x,y]; /*x=rs10 & y=rs20*/
pin [12..14]=[q1,q0,z];
field states=[q1,q0];

$repeat i=[0..3]
$define s{i} 'b'{i}
$repend

field input=[y,x];
no=input:0;
ten=input:1;
twen=input:2;
fake=input:3;
sequence states {
present s0
if ten next s1 out !z;
if twen next s2 out !z;
default next s0 out !z;
present s1
if ten next s2 out !z;
if twen next s3 out z;
default next s1 out !z;
present s2
if ten next s3 out z;
if twen next s1 out z;
default next s2 out !z;
present s3
if ten next s1 out !z;
if twen next s2 out !z;
default next s0 out !z;
}

Results

X=rs10 and y=rs 20

At vector 5, no input and total amount is rs 20 (state S2)
At vector 6, input rs 20, total is rs40 hence deliver product and goes to S1(remain rs10).
Vector 8, input rs 20, total is rs30 hence deliver product and goes to S0(reset).
Vector 10,14 and 15 input rs 10, total rs 30 hence deliver product.
10

11

LAB 8 : Traffic light controller

Design file
/* *************** INPUT PINS *********************/
PIN 1 = CLK ;
PIN 2

PIN

/* *************** OUTPUT PINS *********************/

PIN

12

Q0

PIN

13

Q1

PIN [14..19]=[Z0..5]; /*MR MY MG SR SY SG*/

FIELD state = [Q1..0];
$REPEAT i=[0..3]
$DEFINE S{i} 'b'{i}
$REPEND
FIELD MODE=[C,T];
GO = MODE : 0;
FOLLOW = MODE : 1;
CAR = MODE : 2;
FOLL = MODE : 3;
FIELD OUTPUT=[Z0..5];
MGSR = OUTPUT:'b'001100;
MYSR = OUTPUT:'b'010100;
MRSG = OUTPUT:'b'100001;
MRSY = OUTPUT:'b'100010;
SEQUENCE state {
PRESENT S0
IF CAR NEXT S1;
DEFAULT NEXT S0;
OUT Z2 OUT Z3;
PRESENT S1
IF GO NEXT S1;
IF CAR NEXT S1;
DEFAULT NEXT S2;
OUT Z1 OUT Z3;
PRESENT S2
IF FOLLOW NEXT S2;

12

IF FOLL NEXT S2;

DEFAULT NEXT S3;
OUT Z0 OUT Z5;
PRESENT S3
IF GO NEXT S3;
IF CAR NEXT S3;
DEFAULT NEXT S0;
OUT Z0 OUT Z4;
}

Results

Vector 2 shows state s0 and output is z2 and z3(MG and SR). As long as a car is present on the
side street, the TLC will go through all the states and providing the required output. When there is
no car in the side street (after vector 8) the TLC will remain in state s0.

13

Simulation
The design files were burned and tested accordingly. The appropriate pins were considered as
defined in the design files and they can also be obtained in the .doc file generated by the
WINCUPL.
For example consider the sequence detector:
The pins were defined as follows
pin 1= clk;
pin 2=x;
pin [12..14]=[q2..0];
pin 15 =z;

<=inputs
<= outputs
<= outputs

The same can be obtained from the .doc file

______________
|
detector
|
clk x---|1
20|---x
x x---|2
19|---x
x---|3
18|---x
x---|4
17|---x
x---|5
16|---x
x---|6
15|---x
x---|7
14|---x
x---|8
13|---x
x---|9
12|---x
GND x---|10
11|---x
|______________|

Vcc

z
q0
q1
q2

All the design files were tested and the results were as expected.

14