Cadence:VirtuosoAnalogDesign

Environment

Introduction
CadenceisanElectronicDesignAutomation(EDA)environmentwhichallows differentapplicationsandtoolstointegrateintoasingleframeworkthusallowingto supportallthestagesofICdesignandverificationfromasingleenvironment.These toolsarecompletelygeneral,supportingdifferentfabricationtechnologies.

ThevariousDesignsteps
FirstlyaschematicviewofthecircuitiscreatedusingtheCadenceComposer SchematicEditor.Alternatively,atextnetlistinputcanbeemployed. Then,thecircuitissimulatedusingtheCadenceAffirmaanalogsimulation environment.Differentsimulatorscanbeemployed,somesoldwiththe Cadencesoftware(e.g.,Spectre)somefromothervendors(e.g.,HSPICE)iftheyare installedandlicensed. Oncecircuitspecificationsarefulfilledinsimulation,thecircuitlayoutiscreated usingtheVirtuosoLayoutEditor.Theresultinglayoutmustverifysomegeometricrules

dependentonthetechnology(designrules).Forenforcingit,aDesignRuleCheck (DRC)isperformed. Then,thelayoutshouldbecomparedtothecircuitschematictoensurethatthe intendedfunctionalityisimplemented.ThiscanbedonewithaLayoutVersusSchematic (LVS)check. AlltheseverificationtoolsareincludedintheDivasoftwareinCadence(more powerfulCadencetoolscanalsobeavailable,likeDracula,orAssuraindeepsubmicron technologies). Finally,anetlistincludingalllayoutparasiticsshouldbeextracted,andafinal simulationofthisnetlistshouldbemade.ThisiscalledaPostLayoutsimulation,andis performedwiththes ameCadencesimulationtools.Onceverifiedthelayoutfunctionality,thefinallayout isconvertedtoacertainstandardfileformatdependingonthefoundry(GDSII,CIF,etc.) usingthe Cadenceconversiontools.TheSummaryofthedesignstepsisagainexplainedwith aninverterexampleasfollows.

1.InvokingCadencetool
ThecommandInterpreterWindowcanbeinvokedbytyping icfb& Thetoolisavailableonvlsi34,vlsi35,vlsi36,vlsi27.Thefollowingwindowwill appearonthescreenoninvokingthecommand.

2. CreateLibrary
InordertocreatethelibrarygotoTools>LibraryManagerontheToolsmenu oftheCIW.

NowtocreateanewlibrarygotoFile>New>LibraryfromtheFilemenuof theLibraryManager.

Thenfillinthenameofthenewlibrary.ClickOK.Thefollowingfigureappears.

NowclickonAttachtoanexistingtechfileasshown

NowthelibraryyoucreatedshouldappearintheLibraryManagerwindow.

3.CreateSchematic
Startbyclickingonthelibrary(createdbyyou)intheLibraryManagerwindow, thengotoFile>New>CellViewandfillinwithInverter(inthiscase) asthecellname,schematicastheviewname,andComposerSchematicasthe tool,thenpressOK.

AnemptyWindowappearsasnextfigure.

3.1PlacingtheIntances ClickontheInstanceIconandthenclicktheBrowsebuttonintheformtoopen Librariesbrowsewindow.

Selectthefollowing: UndertheLibrarycolumn,selecttsmc35mm. UnderCell,nch.(fornmos) UnderView,selectsymbol

Youcaneditthepropertiesoftheinstancewhentheabovefigureappears

NowClickontheSchematicwindowtoplaceaninstanceasshownbelow Similarlyyoucanplacepmos. YoucanpresstheESCkeyonthekeyboardtogetoutoftheplaceinstancemode oryoucankeepplacingotherparts. 3.2AddingtheI/OPins InthelowerleftsideoftheComposerwindowclickonthePinicon.Addtheinput andoutputpins,shownasfollowing. UnderPinNames,typeInorOutoranyothername.NotethatDirectioninthe formreadsinputoroutput. 3.3AddingWires OntheleftsideoftheComposerwindowclickontheWireicon.Nowclickonthe schematicfromwhereyouwantto

drawthewireandclickonthepointwhereyouwanttofinishthewire.Thefinal schematicshouldlooksomewhatlikethis:

NowyouneedtoCheckandSaveyourdesign(eitherthetopleftbuttonorDesign> CheckandSave).MakesureyoulookattheCIWwindow andtherearenoerrorsorwarnings,ifthereareanyyouhavetogobackandfix them!Assumingtherearenoerrorswearenowreadytostartsimulation!

4. Simulation
IntheVirtuosoSchematicwindowgotoTools>AnalogEnvironment.Thereis goingtotheanother"What'sNew"popupwindowthatyoucanreadandcloseor minimize.

ThedesignshouldbesettotherightLibrary,CellandView.Thewindowappearsas shownbelow.

4.1ChoosingaSimulationEngine IntheSimulationwindow,selectSetupSimulator/Directory/Host ChoosetheSimulatorcyclicfieldisreadingSpectreS

4.2ChoosingtheAnalyses IntheAffirmaAnalogCircuitDesignEnvironmentwindow,clickAnalysis Choosepulldownmenutoopentheanalyseswindow. Severalanalysesmodesaresetup. 4.2.1TransientAnalysis IntheAnalysisSection,selecttranandsettheStopTimeandBefore ClickingOKbutton,clickAPPLYbutton.

4.3SavingandPlottingSimulationData SelectOutputTobePlottedSelectonSchematictoselectnodestobe plotted. Byclickingonthewireontheschematicwindowtoselectvoltagenode,andby clickingontheterminalstoselectcurrents.

Selecttheinputandoutputwiresinthecircuit.Observethesimulationwindowas thewiresgetadded. 4.4RunningtheSimulation ClickontheRunSimulationicon. Whenitcomplete,theplotsareshownautomatically.

5.Layout
Wewillusealayoutthathasasimilartopologytotheschematic.Itwillhave horizontalvdd(top)andgnd(bottom)linesINontheleft andOUTontheright,allinmetal1. TostarttheVirtuosoXLenvironment,opentheschematicviewofcellinverter. Next,inthe Composerwindow,clickonTools>DesignSynthesis>LayoutXL. TheVirtuosoXLStartupOptionwindowwillappear,askingwhetheranewlayout cellviewshouldbecreatedoranexisting layoutcellshouldbeused.EnableCreateNewandclickonOK.ACreateNewFile windowwillthenappear.

FillintheLibraryNameforCellNameinverter,forViewNamelayout,andfor ToolVirtuoso,andclickonOK. TheVirtuosolayoutwindowthenappears.

Tostartthegenerationofthelayoutfromtheschematic,clickonCreate>Pickfrom schematic...in theVirtuosoXLwindow.

Next,SelectdeviceinschematictoplaceintheVirtuosoSchematicwindow. TheVirtuosoXLwindowwillshowarectanglecorrespondingtoeachpmosand nmosdeviceintheschematic.

Theflattenthelayoutinstance,selecttheinstanceandclickEdit>Hierarchy> Flatten. Toseewhichlayoutinstancecorrespondstowhichschematicinstance,clickonan instanceinone oftheviewsandthecorrespondinginstanceintheotherviewwillbehighlighted.

Untilnowwehavejustmadeplacementcorrespondingtopmosandnmosinthe schematicandwestillneedtorouteourschematic.Firstlet'sroutetheoutput, clickonmetal1andthenCreate>Pathanddrawapathfromthedrainofthepmos tothedrainofthenmos(rightside).Youhavetodoubleclicktoendthepath. Similarlyconnectinput.Drawapolypathbetweenthetwogates Theonlyitemsleftnowarethevddandgndconnections.Nowyoucanmanuallydraw vddandGndnetsinMetal1.TheVDDrailisgenerallyabovethethecelland

theGNDrailisgenerallybelowthecell.Ingeneral,thepowerandgroundrailshavea fixedspacingbetweenthemsothatdifferentcellscaneasilybeconnectinarow. AddPins Onceyouhavefinishedcreatingthelayout,thenextstepistoaddtheI/Opinsofyour circuit.Itisnecessarytoaddthevdd!andgnd!pinstoyourcircuitforthepurpose ofverification(ifyouhaveusedtheseterminalsintheschematic).Netlabelsendingin ! meanglobalnodes(i.e.,allwiresintheentiredesignhierarchylabeledwiththisname are consideredtobeconnected,eveniftheyphysicallyarenot.Theyareusuallypower nets). ThefollowingisaprocedureforaddingI/Opinstoyourcircuit: FromyourLayoutwindow: 1.ChooseCreate>Pin...fromthemenu.TheCreatePinformwillappear

3.EnteraTerminalName(thenameofyourpin). 4.Makesurethatthe"DisplayPinName"optionisselected. 5.Specifythe"I/OType"asinput,output,orinputoutput,accordingtothe schematic.

6.SpecifythePinTypeasMetal1,Metal2,...dependingonwhichisthetop layerattheplacethatthepinistobeinserted(theyshouldmatch). 7.SpecifythePinWidthtothedesiredpinwidth(thepinissquare). 8. Movethemousetospecifywherethepinandthelabelshouldbeplaced. Theffinallayoutmaylooklike

6.Verification

6.1DesignRuleCheck(DRC) FromyourLayoutwindow: 1. ChooseAssura>RunDRCfromthemenu.TheVerifyDRCformwillappear. 2. ClickOKtorunDRC.

RulesFile: /cad/cadence/DesignKits/Tsmc_035MM_PDK/Assura/drc/2p4m/UM35p5_4M.23b Ifyourdesignhasviolatedanydesignrules,DRCwillreporttheerrorsinthe CIW.

Errorsarealsoindicatedbythemarkers(whitecolor)onthecircuit. Youmaythenproceedtocorrecttheerrorsaccordingtothedesignrules. Forhugelayouts,themarkersmightnotbeeasilylocated.Tofindmarkers, chooseVerify>Markers>Findinlayoutwindow. Apopupmenuwillappear.ClickontheZoomtoMarkersbox. 6.2LayoutversusSchematic(LVS) Oncethelayoutfulfillsallthedesignrules,thenextverificationstepfollows.The netlistbehindthe layoutviewisextractedandcomparedtothatoftheschematicview.Thisisthe LayoutVersus Schematic(LVS)Check. IntheVirtuosolayoutwindow,selectAssura>RunLVS.