EIE 322 Interface and Embedded Systems

Microcontroller Architecture the 8051 example

The 8051 Microcontroller (Chapter 2)
I. MacKenzie, Prentice-Hall 1995, QA 76.8.127M23
Dr. Jimmy To, EIE, PolyU

Introduction to Microcontrollers
Microprocessors
CPU only Needs many ICs to implement a small system

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Introduction to Microcontrollers
Microcontrollers
CPU + I/O + Timer(s) [+ ROM] [+ RAM] Low to moderate performance only

Limited RAM space, ROM space and I/O pins

EPROM version available Low chip-count to implement a small system Low-cost at large quantities Development tools readily available at reasonable cost
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Return

Signal Pins

Figure 2-2 8051 pinouts

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I/O Port Circuitry

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Alternate Pin-functions

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Memory Space

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Bit Addressable RAM

Figure 2-6 Summary of the 8051 on-chip data memory

(RAM)

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Bit Addressable RAM

Figure 2-6 Summary of the 8051 on-chip data memory (Special Function Registers)

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Register Banks
Four banks of 8 byte-sized registers, R0 to R7 Addresses are :

18 - 1F
10 - 17 08 - 0F 00 - 07
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for bank 3
for bank 2 for bank 1 for bank 0 (default)
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Register Banks
Active bank selected by bits in PSW. [ RS1, RS0 ]

Permits fast context switching in interrupt service routines (ISR).

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Program Status Word (PSW)

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Address Multiplexing for External Memory

Figure 2-7 Multiplexing the address (low-byte) and data bus

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Accessing External Code Memory

Figure 2-8 Accessing external code memory

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Accessing External Data Memory

Figure 2-11 Interface to 1K RAM

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Figure 2-10 Timing for MOVX instruction

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Overlapping External Code and Data Spaces

Allows the RAM to be
written as data memory, and read as data memory as well as code memory.

This allows a program to be

"downloaded" from outside into the RAM as data, and executed from RAM as code.
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Overlapping External Code and Data Spaces

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