DESIGN AND OPTIMIZATION OF PROCESSORS FOR ENERGY EFFICIENCY: A JOINT ARCHITECTURE-CIRCUIT APPROACH

A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Omid Jalal Azizi August 2010

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Abstract
Power consumption limits have changed how processors are designed today: designers now need to be very careful to use their energy budgets eciently. While a design option may be used to increase performance, it usually comes at an energy cost. Thus, to create a truly ecient processor, the designer must consider the space of all available options and parameters and make those design choices that oer the best rate of return in terms of performance per unit energy. Performing this eciency optimization presents several challenges. First, the design space of a processor can be very large, and designers need a way of exploring this multi-dimensional space eectively. Second, the costs of the architectural units are directly dependent on the circuits that are used to implement them; these circuits, however, have a design space of their own and can internally trade o speed for energy. As a result, to properly evaluate the cost of an architectural feature, designers need to be aware of the circuit-level design spaces as well.

This work presents an integrated optimization framework that addresses these challenges by performing a co-exploration of the architectural and circuit-level design spaces. In this framework, we model large architectural design spaces by using sta-tistical sampling and fitting techniques, and we characterize circuit design trade-os for underlying units which we store in a library. We then link these two design spaces together to create a joint architecture-circuit model. By using posynomial functions for our models, we are then able to form a geometric program optimization problem v

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