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16COM/40SEG Controller/Driver
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CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product
SPLC780D
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4 2. FEATURES.................................................................................................................................................................................................. 4 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 5. COMPARISON OF SPLC780D AND SPLC780C ........................................................................................................................................ 5 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 6.1. OSCILLATOR .......................................................................................................................................................................................... 6 6.2. CONTROL AND DISPLAY INSTRUCTIONS ................................................................................................................................................... 6 6.3. INSTRUCTION TABLE............................................................................................................................................................................... 8 6.4. 8-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET)................................................................................................ 9
6.5. 4-BIT OPERATION AND 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10 6.6. 8-BIT OPERATION AND 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET).............................................................................................. 10 6.7. RESET FUNCTION .................................................................................................................................................................................11 6.8. DISPLAY DATA RAM (DD RAM)............................................................................................................................................................ 13 6.9. TIMING GENERATION CIRCUIT............................................................................................................................................................... 13 6.10. LCD DRIVER CIRCUIT ....................................................................................................................................................................... 13 6.11. CHARACTER GENERATOR ROM (CG ROM)....................................................................................................................................... 13 6.12. CHARACTER GENERATOR RAM (CG RAM)........................................................................................................................................ 13 6.13. CURSOR/BLINK CONTROL CIRCUIT .................................................................................................................................................... 17 6.14. INTERFACING TO MPU....................................................................................................................................................................... 18 6.15. SUPPLY VOLTAGE FOR LCD DRIVE..................................................................................................................................................... 19 6.16. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER) ............................................................................................. 22 6.17. BUSY FLAG (BF) ............................................................................................................................................................................... 22 6.18. ADDRESS COUNTER (AC).................................................................................................................................................................. 22 6.19. I/O PORT CONFIGURATION ................................................................................................................................................................ 22 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 23 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 23 7.2. DC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 23 7.3. AC CHARACTERISTICS (VDD = 2.7V TO 4.5V, TA = 25) ..................................................................................................................... 24 7.4. DC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25)..................................................................................................................... 25 7.5. AC CHARACTERISTICS (VDD = 4.5V TO 5.5V, TA = 25) ..................................................................................................................... 25 8. APPLICATION CIRCUITS ......................................................................................................................................................................... 27 8.1. R-OSCILLATOR .................................................................................................................................................................................... 27 8.2. INTERFACE TO MPU............................................................................................................................................................................. 27 8.3. SPLC780D APPLICATION CIRCUIT ....................................................................................................................................................... 27 8.4. APPLICATIONS FOR LCD ...................................................................................................................................................................... 27 9. CHARACTER GENERATOR ROM ........................................................................................................................................................... 27 9.1. SPLC780D - 01 .................................................................................................................................................................................. 27 9.2. SPLC780D - 02 .................................................................................................................................................................................. 27 9.3. SPLC780D - 03 .................................................................................................................................................................................. 27 9.4. SPLC780D - 08 .................................................................................................................................................................................. 27 9.5. SPLC780D - 11 .................................................................................................................................................................................. 27 Sunplus Technology Co., Ltd. Proprietary & Confidential 2 NOV. 04, 2004 Version: 1.2
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SPLC780D
9.6. SPLC780D - 12 .................................................................................................................................................................................. 27 9.7. SPLC780D - 13 .................................................................................................................................................................................. 27 9.8. SPLC780D - 14 .................................................................................................................................................................................. 27 9.9. SPLC780D - 15 .................................................................................................................................................................................. 27 9.10. SPLC780D - 17 ............................................................................................................................................................................... 27 9.11. SPLC780D - 18 ............................................................................................................................................................................... 27 9.12. SPLC780D - 19 ............................................................................................................................................................................... 27 9.13. SPLC780D - 54 ............................................................................................................................................................................... 27 10. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 27 10.1. PAD ASSIGNMENT AND LOCATIONS ................................................................................................................................................... 27 10.2. PACKAGE CONFIGURATION ................................................................................................................................................................ 27
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SPLC780D
16COM/40SEG CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPLC780D, a dot-matrix LCD controller and driver from SUNPLUS, is a unique design for displaying alpha-numeric, Japanese-Kana characters and symbols. The SPLC780D provides two types of interfaces to MPU: 4-bit and 8-bit interfaces. The transferring speed of 8-bit is twice faster than 4-bit. A single SPLC780D is able to display up to two 8-character lines. be extended. rank. By cascading with SPLC100 or SPLC063, the display capability can The CMOS technology ensures the power saves in the most efficient way and the performance keeps in the highest
2. FEATURES
Character generator ROM: 10880 bits Character font 5 x 8 dots: 192 characters Character font 5 x 10 dots: 64 characters Character generator RAM: 512 bits Character font 5 x 8 dots: 8 characters Character font 5 x 10 dots: 4 characters 4-bit or 8-bit MPU interfaces
Direct driver for LCD: 16 COMs x 40 SEGs Duty factor (selected by program): 1/8 duty: 1 line of 5 x 8 dots 1/11 duty: 1 line of 5 x 10 dots
3. BLOCK DIAGRAM
OSC1 OSC2 VDD VSS
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1/16 duty: 2 lines of 5 x 8 dots / line Built-in power on automatic reset circuit Support external clock operation Low Power Consumption
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CL1,CL2 M
Parallel to Serial Data Conversion Circuit 5 5 Character Generator ROM 8 Character Generator RAM 8
Busy Flag
I/O
Data Register
Latch Circuit
40
Buffer
Instruction Register
Instruction Decorder 7
COM1COM16
SEG1SEG40
Address Counter
SPLC780D
4. SIGNAL DESCRIPTIONS
Mnemonic VDD VSS OSC1 OSC2 V1 - V5 E R/W RS PIN No. 33 23 24 25 26 - 30 38 37 36 I I I I Type I I Power input Ground Both OSC1 and OSC2 are connected to resistor for internal oscillator circuit. For external clock operation, the clock is input to OSC1. Supply voltage for LCD driving. A start signal for reading or writing data. A signal for selecting read or write actions. 1: Read, 0: Write. A signal for selecting registers. 1: Data Register (for read and write) 0: Instruction Register (for write), DB0 - DB3 DB4 - DB7 CL1 CL2 M D SEG1 - SEG22 39 - 42 43 - 46 31 32 I/O I/O O O Low 4-bit data Description
Chip size
PAD Size
SPLC780D is very similar to SPLC780C. Because they are fabricated on the same foundry and user the same rule, they have the same DC/AC characteristic and they are fully function compatible.
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High 4-bit data Clock to latch serial data D. Clock to shift serial data D. 34 35 O O Switch signal to convert LCD waveform to AC. 1: Selection, 0: Non-selection. Segment signals for LCD. 22 - 1 O O 80 - 63 47 - 62 Common signals for LCD. SPLC780C 2860u*2450u 90u * 90u 110u 2.5V 3140u*2690u 94u * 94u 120u 2.2V
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Memo
SPLC780D
6. FUNCTIONAL DESCRIPTIONS
6.1. Oscillator
SPLC780D oscillator supports not only the internal oscillator operation, but also the external clock operation. S=1 S=1 I/D=1 I/D=0 It shifts the display to the left It shifts the display to the right
D = 1: Display on, D = 0: Display off C = 1: Cursor on, C = 0: Cursor off It clears the entire display and sets Display Data RAM Address 0 in Address Counter. B = 1: Blinks on, B= 0: Blinks off
X: Do not care (0 or 1)
display returns to its original position. The cursor or blink goes to the most-left side of the display (to the 1st line if 2 lines are displayed). change.
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S
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5 x 8 dot character font 8th line Cursor
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5 x 10 dot
character font
11th line
RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L X X
Code
S/C 0 0 1 1
R/L 0 1 0 1 Shift cursor to the left Shift cursor to the right Shift display to the left.
Description
Address Counter AC = AC - 1 AC = AC + 1
AC = AC AC = AC
SPLC780D
6.2.6. Function set
Display data RAM can be read or written after this setting.
RS Code 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N F X X
X: Do not care (0 or 1) DL: It sets interface data length. DL = 1: Data transferred with 8-bit length (DB7 - 0). DL = 0: Data transferred with 4-bit length (DB7 - 4). It requires two times to accomplish data transferring. N: It sets the number of the display line. N = 0: One-line display. N = 1: Two-line display. F: It sets the character font. F = 0: 5 x 8 dots character font. F = 1: 5 x 10 dots character font.
In two-line display (N = 1), (aaaaaaa)2: (00)16 - (27)16 for the first line, (aaaaaaa)2: (40)16 - (67)16 for the second line.
N 0 0 1
F 0 1 X
Character Generator RAM data can be read or written after this setting.
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Character Font Duty Factor 5 x 8 dots 1/8 5 x 10 dots 5 x 8 dots 1 / 11 1 / 16
When BF = 1, it indicates the system is busy now and it will not accept any instruction until not busy (BF = 0). At the same time, the content of Address Counter (aaaaaaa)2 is read.
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Code
6.2.11. Read data from character generator RAM or display data RAM
RS 1
Code
It reads data (dddddddd)2 from character generator RAM or display data RAM.
To read data correctly, do the following: 1). The address of the Character Generator RAM or Display Data RAM or shift the cursor instruction.
SPLC780D
6.3. Instruction Table
Instruction Code Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write "20H" to DDRAM Clear Display 0 0 0 0 0 0 0 0 0 1 and set DDRAM address to "00H" from AC Set DDRAM address to "00H" Return Home 0 0 0 0 0 0 0 0 1 return from cursor AC to and 2.16ms 1.52ms 1.18ms Description Execution time (Temp = 25) Fosc= 190KHz Fosc= 270KHz Fosc= 350KHz
original position if shifted. The contents of DDRAM are not changed. Assign cursor
I/D
Function Set
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0 0 0 0 0 0 1 D C B bit. 0 0 0 0 0 1 S/C R/L changing data. of 0 0 0 0 1 DL N F of display line font type dots/5x8 dots) 0 0 0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 address counter. address counter AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 counter read. can also 1 1 0 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
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53s 53s
2.16ms
1.52ms
moving
(D),
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38s 38s 38s
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1.18ms 29s 29s
cursor(B) on/off control Set cursor moving and display shift control bit, and the direction, without DDRAM
29s
Set interface data length (DL: 8-bit/4-bit), numbers (N: 2-line/1-line) and, display (F:5x10 53s 38s 29s
Set CGRAM address in Set DDRAM address in Whether during internal operation or not can be known by reading BF. The contents of address be
53s 53s
38s 38s
29s 29s
Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
53s 53s
38s 38s
29s 29s
Note1: --: dont care Note2: In the operation condition under -20 ~ 75, the maximum execution time for majority of instruction sets is 100us, except two instructions, Clear Display and Return Home, in which maximum execution time can take up to 4.1ms.
SPLC780D
6.4. 8-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 2 Instruction Power on. (SPLC780D starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 X X
Operation
Set to 8-bit operation and select 1-line display line and character font.
It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ".
W_
The cursor is incremented by one and shifted to the right. Write " E ".
7 8
1 0 0
10
11
12 13
1 0 0
14
15
16
17
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0 1
WE_
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WELCOME_
The cursor is incremented by one and shifted to the right. Set mode for display shift when writing
WELCOME_
ELCOME _
Write "
"(space).
The cursor is incremented by one and shifted to the right. Write " C ".
LCOME C_
COMPAMY_
The cursor is incremented by one and shifted to the right. Only shift the cursor's position to the left (Y).
COMPAMY_
COMPAMY_
OMPANY_
COMPAMY_
18
OMPANY_
19
COMPAMY_
Write " " (space). The cursor is incremented by one and shifted to the right.
20 21 Return home
0 0 0 0 0
:
0 0 0 1 0
:
WELCOME_
: Both the display and the cursor return to the original position (address 0).
SPLC780D
6.5. 4-Bit Operation and 8-Digit 1-Line Display (Using Internal Reset)
No. 1 2 Power on. (SPLC780D starts initializing) Function set
RS R/W DB7 DB6 DB5 DB4 0 0
0 0 0 0
Instruction
Operation
0
0 0 0 1
0
0 0 0 1
1
1 X 0 1
0
0 X 0
0 0
Set to 4-bit operation and select 1-line display line and character font.
0 0
_
0
0 0
0 0
0 0
0 1
0 1
0 0
It will shift the cursor to the right when writing to the DD RAM / CG RAM. Now the display has no shift. Write " W ".
1 1
0 0
0 0
6.6. 8-Bit Operation and 8-Digit 2-Line Display (Using Internal Reset)
No. 1 2 Power on. Function set
0 0 0
6 7
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1 1 0 1 1 1
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W_
Instruction
Display
Operation
Set to 8-bit operation and select 2-line display line and 5 x 8 dot character font.
Display on.
Cursor appear.
It will shift the cursor to the right when writing to the DD RAM / Now the display has no shift. Write " W ".
W_
WELCOME_
It sets DD RAM's address. The cursor is moved to the beginning position of the 2nd line. Write " T ". The cursor is incremented by one and shifted to the right. : Write " T ". The cursor is incremented by one and shifted to the right.
WELCOME T_
10 11
:
WELCOME TO PART_
10
SPLC780D
No. 12 Entry mode set
0 0 0 0 0 0 0 1 1 1
Instruction
Display
WELCOME TO PART_
13
ELCOME O PARTY_
Write " Y ". The cursor is incremented by one and shifted to the right. : Both the display and the cursor return to the original position (address 0).
14 15 Return home
0 0 0 0 0
:
WELCOME TO PARTY
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[ 8-Bit Interface ] Power On W ait time > 15 ms after VDD > 4.5V
W ait time > 40ms After VDD > 2.7V
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BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB1 DB0 0 0 0 0 1 1 N F X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 I/D 0 1 S
Function set ( Interface is 8 bits length . Specify the number of display lines and character font . ) The number of display lines and character font cannot be changed afterwards . Display off Display clear
Initialization Ends
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SPLC780D
[ 4-Bit Interface ] Power On
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
BF cannot be checked before this instruction . Function set ( Interface is 8 bits length . )
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W ait time > 100 us Function set ( Interface is 8 bits length . ) BF can be checked after the following instructions . 0 0 Function set ( Interface is 4 bits length . Specify the number of the display lines and character font . ) 0 0 0 0 0 1 0 0 0 Display off 0 0 1 I/D S Display clear Initialization Ends Entry mode set
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The number of display lines and character font cannot be changed afterwards .
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SPLC780D
6.8. Display Data RAM (DD RAM)
The 80-bit DD RAM is normally used for storing display data. Those DD RAM not used for display data can be used as general data RAM. Its address is configured in the Address Counter. The relationships between Display Data RAM Address and LCD s position are depicted as follows.
79 4E
80 4F
Display position
When the display shift operation is performed , the display data RAM's address moves as : ( i ) Left shift 01 ( ii ) Right shift 4F 00
02
interface, the MPU access timing and the RAM access timing are generated independently.
the LCD driver circuit. When a program specifies the character drive-waveforms and the others still output unselected waveforms.
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03 04 05 06 06 07 08 01 02 03
In order to prevent the internal timing dots character patterns.
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05
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SPLC780D
The following diagram shows the SPLC780D character patterns: Correspondence between Character Codes and Character Patterns.
CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8) CG RAM (1) CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8)
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SPLC780D
The relationships between Character Generator RAM Addresses, Character Generator RAM Data (character patterns), and Character Codes are depicted as follows:
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Note1: Note2:
It means that the bit0~2 of the character code correspond to the bit3~5 of the CG RAM address. These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 ": Selected, " 0 " : No selected , " X " : Do not care (0 or 1). display T character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7-b4 = 0) to display T . Note6: The bits 0-2 of the character code RAM is the character pattern line position.
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0 X 0 0 1 0 0 1 X X X
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Cursor Position
The 8th line is the cursor position and display is formed by logical OR
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SPLC780D
6.12.2. 5 X 10 dot character patterns
CG RAM Address b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
0 0 0 1 1 1 1 1 1 1 1
Note1: Note2:
It means that the bit1~2 of the character code correspond to the bit4~5 of the CG RAM address. These areas are not used for display, but can be used for the general data RAM.
Note3: When all of the bit4-7 of the character code are 0, CG RAM character patterns are selected. Note4: " 1 : Selected, " 0 : No selected, " X : Do not care (0 or 1). (08) 16,and (09) 16 can display U character. with the cursor.
Note5: For example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7-b4 = 0) to display U . Note6: The bits 0-3 of the character code RAM is the character pattern line position.
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X X X X X X X X
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Cursor Position
That means all of the character codes (00) 16, (01) 16,
The 11th line is the cursor position and display is formed by logical OR
16
SPLC780D
6.13. Cursor/Blink Control Circuit
This circuit generates the cursor or blink in the cursor / blink control circuit. The cursor or the blink appears in the digit at the Display Data RAM Address defined in the Address Counter. When the Address Counter is (07) 16, the cursor position is shown as belows:
b6 AC 0
b5 0
b4 0
b3 0
b2 1
b1 1
b0 1
Display position
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the cursor position 1 2 3 4 5 6 7 8 9 10 Display position 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 ( Hexadecimal ) the cursor position
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SPLC780D
6.14. Interfacing to MPU
There are two types of data operations: 4-bit and 8-bit operations. Using 4-bit MPU, the interfacing 4-bit data is transferred by 4-busline (DB4 to DB7). Thus, DB0 to DB3 bus lines are not used. Using 4-bit MPU to interface 8-bit data requires two times transferring. First, the higher 4-bit data is transferred by 4-busline (for 8-bit operation, DB7 to DB4). Secondly, the lower 4-bit data is transferred by 4-busline (for 8-bit operation, DB3 to DB0). For 8-bit MPU, the 8-bit data is transferred by 8-buslines (DB0 to DB7).
RS
R/W
Internal operation
DB7
DB6
DB5
DB4
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Functioning IR7 IR3 Busy AC3 Not busy AC3 D7 IR6 IR2 AC6 AC2 AC6 AC2 D6 IR5 IR1 AC5 AC1 AC5 AC1 D5 IR4 IR0 AC4 AC0 AC4 AC0 D4 Instruction Write Busy flag check Busy flag check
Example of 4-bit Data Transfer Timing Sequence
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D1
D0
Data Write
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SPLC780D
RS
R/W
Internal operation
Functioning
DB7
IR7
Busy
Busy
Not Busy
DB6
IR6
AC6
AC6
DB5
IR5
AC5
AC5
DB4
IR4
AC4
AC4
DB3
DB2
DB1
DB0
Different voltages can be supplied to SPLC780Ds pins (V5 - 1) for obtaining LCD drive-waveform. The relationships between bias, duty factor and supply voltages are shown as belows:
Supply Voltage
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IR3 AC3 AC3 AC3 IR2 AC2 AC2 AC2 IR1 AC1 AC1 AC1 IR0 AC0 AC0 AC0 Instruction Write Busy flag check Busy flag check Busy flag check
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AC6
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D6
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D5 D4 D3 D2 D1 D0
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Data Write
Duty Factor
1/16 1/5 VDD 1/5 VLCD VDD 2/5 VLCD VDD 3/5 VLCD VDD 4/5 VLCD VDD VLCD
V1 V2 V3 V4 V5
VDD 1/4 VLCD VDD 1/2 VLCD VDD 1/2 VLCD VDD 3/4 VLCD VDD VLCD
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SPLC780D
6.15.1. The power connections for LCD (1/4 Bias, 1/5 Bias) are shown belows:
VDD ( +5.0V ) VDD R V1 V2 V3 V4 R V5 V5 R V LCD R V3 V4 V1 V2 R VDD ( +5.0V )
VDD R
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VR VR 1 / 4 Bias 1 / 5 Bias (1/8,1/11 Duty) -V or Gnd (1/16 Duty) -V or Gnd
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VDD( +5.0V )
VDD( +5.0V )
VDD
VDD
V1
V1
V2 V3
V2
V3
V4
V4
V5
The bias voltage must have the following relations: VDD V1 V2 V3 V4 V5.
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SPLC780D
6.15.2. The relationship between LCD frames frequency and oscillators frequency.
(Assume the oscillation frequency is 250KHz, 1 clock cycle time = 4.0s)
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400 clocks 1 2 10 11 1 2 10 11 1 2 VPP V1 COM1 V2(V3) V4 VSS 1 Frame 1 Frame 1 frame = 4(s) x 400 x 11 = 17600(s) = 17.6ms Frame frequency 1 17.6(ms) 5 6 .8(Hz)
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200 clocks
1 2
15 16 1 2
15 16 1 2
1 Frame 1 frame = 4(s) x 200 x 16 = 12800(s) = 12.8ms 1 Frame frequency 78.1(Hz) 12.8(ms)
1 Frame
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SPLC780D
6.16. REGISTER --- IR (Instruction Register) and DR (Data Register)
SPLC780D contains two 8-bit registers: Instruction Register (IR) and Data Register (DR). Using combinations of the RS pin and the R/W pin selects the IR and DR, see below:
VDD
PMOS
RS 0 0 1 1
R/W 0 1 0 1
Operation IR write (Display clear, etc.) Read busy flag (DB7) and Address Counter (DB0 - DB6) DR write (DR to Display data RAM or Character generator RAM) DR read (Display data RAM or Character generator RAM to DR)
sch
NMOS
When RS = 0 and R/W = 1, the busy flag is output to DB7. As the busy flag =1, SPLC780D is in busy state and does not accept any instruction until the busy flag = 0.
and Character Generator RAM. When an instruction for address is written in IR, the address information is sent from IR to AC.
After writing to/reading from Display Data RAM or Character Generator RAM, AC is automatically incremented by one (or decremented by one). The contents of AC are output to DB0 DB6 when RS = 0 and R/W = 1.
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PMOS
NMOS
PMOS
NMOS
VDD
VDD
VDD
Enable
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PMOS
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NMOS Data
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SPLC780D
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Ratings -0.3V to +7.0V VDD - 12V to VDD + 0.3V -0.3V to VDD + 0.3V -30 to +80 -55 to +125
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Output High Output Low
Note: FOSC = 250KHz, VDD = 3.0V, pin E = L, RS, R/W, DB 0 - DB7 are open, all outputs are no loads.
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mA V VIH1 VIL1 0.7VDD -0.3 VDD 0.55 V VIH2 VIL2 IIH IIL 0.7VDD -0.2 VDD V 0.2VDD 1.0 V Pin OSC1 -1.0 A -10.0 -50 -120 A V VDD = 3.0V VOH1 VOL1 0.75VDD IOH = - 0.1mA IOL = 0.1mA 0.2VDD V VOH2 VOL2 0.8VDD V IOH = - 40A, 0.2VDD 20 V RCOM RSEG VLCD K 30 K V 3.0 9.0
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Pins: DB0 - DB7 Pins: DB0 - DB7 Pins: CL1, CL2, M, D CL1, CL2, M, D
IO = 50A, VLCD = 4.0V Pins: COM1 - COM16 Pins: SEG1 - SEG40 IO = 50A, VLCD = 4.0V
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SPLC780D
7.3. AC Characteristics (VDD = 2.7V to 4.5V, TA = 25) 7.3.1. Internal clock operation
Characteristics OSC Frequency Symbol FOSC1 Limit Min. 190 Typ. 270 Max. 350 Unit KHz Test Condition VDD = 3.0V, Rf = 75K2%
E Pulse Width
E Rise/Fall Time
Address Setup Time Address Hold Time Data Setup Time Data Hold Time
E Rise/Fall Time
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Limit Typ. Min. Max. Unit ns ns 1000 450 Pin E Pin E tPW tR , t F tSP1 25 ns Pin E 60 ns tHD1 tSP2 20 ns 195 10 ns tHD2 ns Limit Typ. Min. Max. Unit ns 1000 450 Pin E tW ns Pin E Pin E tR , t F tSP1 25 ns 60 ns tHD1 tD 20 ns 360 ns tHD2 5.0 ns
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SPLC780D
7.4. DC Characteristics (VDD = 4.5V to 5.5V, TA = 25)
Characteristics Operating Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage (TTL) Output Low Voltage (TTL) Output High Output Low Symbol IDD VIH1 VIL1 VIH2 VIL2 IIH IIL VOH1 VOL1 Limit Min. 2.5 -0.3 VDD-1 -0.2 -2.0 -20 2.4 Typ. 0.55 -125 Max. 0.8 VDD 0.6 VDD 1.0 2.0 -250 VDD 0.4 Unit mA V V V V A A V Test Condition External clock (Note) Pins:(E, RS, R/W, DB0 - DB7) VDD=5V Pin OSC1 Pin OSC1
Driver ON Resistance
Driver ON Resistance
Note: FOSC = 250KHz, VDD = 5.0V, pin E = L, RS, R/W, DB 0 - DB7 are open, all outputs are no loads.
7.5. AC Characteristics (VDD = 4.5V to 5.5V, TA = 25) 7.5.1. Internal clock operation
Characteristics OSC Frequency
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VOH2 VOL2 0.9VDD VDD V IOH = - 40A, 0.1VDD 20 V RCOM RSEG VLCD K 30 11 K V 3.0 Symbol FOSC1 Limit Typ. 270 Min. 190 Max. 350 Unit KHz Symbol FOSC2 Limit Typ. 250 50 Min. 125 45 t r, t f Max. 350 55 0.2 Unit KHz % s
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IO = 50A, VLCD = 4.0V Pins: COM1 - COM16 Pins: SEG1 - SEG40 IO = 50A, VLCD = 4.0V
Test Condition
Test Condition
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SPLC780D
7.5.3. Write mode (Writing Data from MPU to SPLC780D)
Characteristics E Cycle Time E Pulse Width E Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tC tPW tR , t F tSP1 tHD1 tSP2 tHD2 Limit Min. 500 230 40 10 80 10 Typ. Max. 20 Unit ns ns ns ns ns ns ns Pin E Pin E Pin E Pins: RS, R/W, E Pins: RS, R/W, E Pins: DB0 - DB7 Pins: DB0 - DB7 Test Condition
E Rise/Fall Time
Clock pulse width high Clock pulse width low Clock setup time Data setup time Data hold time M delay time
d e i f s n U o C ER s u IN l p M n T u S AR P r o F
Min. 500 230 Max. ns ns Pin E Pin E tW tR , t F tSP1 20 ns Pin E 40 ns tHD1 tD 10 ns ns ns 120 tHD2 5.0 Limit Typ. Min. 800 Max. Unit ns ns 800 500 ns tDSP tHD tD 300 ns Pins: D 300 ns ns Pins: D -1000 1000 Pins: M
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SPLC780D
7.5.6. Write mode timing diagram (Writing Data from MPU to SPLC780D)
RS
V IH1 V IL1 tSP1 V IL1 tPW V IH1 V IL1 tR V IH1 V IL1 V IH1 V IL1 tSP2
R/W
tHD2
DB7 - 0
Valid Data tC
V IH1 V IL1
7.5.7. Read mode timing diagram (Reading Data from SPLC780D to MPU)
R/W
DB0 - DB7
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V IH1 V IL1
tHD1
V IH1
V IH1
tPW
V IH1 V IL1
V IH1 V IL1
tF tHD1
V IL1
tR
tD V IH1 V IL1
tHD2
Valid Data tC
V IH1 V IL1
tPWH
0.9VDD
tPWH
CL2
tCSP
0.9VDD
0.1VDD
0.1VDD
tCSP
D
0.9VDD 0.1VDD
tPWL
0.9VDD 0.1VDD
tDSP
M
0.1VDD
tHD
tD
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SPLC780D
8. APPLICATION CIRCUITS
8.1. R-Oscillator
The oscillation resistor Rf is used only for the internal oscillator operation mode.
OSC1 Rf : 75.0K2% ( when VDD = 3.0V) Rf : 91K 2% ( when VDD = 5.0V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
OSC2
600
Fosc ( KHz )
270 200
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0 0 75 100 200 300 400 0 Rosc ( Kohms ) 0 91 100 200 300 Rosc ( Kohms )
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VDD = 3.0V
VDD = 5.0V
PA0 | PA7
DB0 | DB7
COM1 | COM16
16
LCD PANEL
6805
SPLC780D
16 COMMONS X
PB0
PB1 PB2
RS
R/W
SEG1 | SEG40
40
40 SEGMENTS
D0 | D7 A1 | A7
8 7
DB0 | DB7
Z80
COM1 | COM16
16
LCD PANEL
16 COMMONS X
E RS
SPLC780D
SEG1 | SEG40 40
A0 IORQ WR
40 SEGMENTS
R/W
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SPLC780D
8.3. SPLC780D Application Circuit
40
SEG40 | SEG1
SPLC100A1
DR2 DL2 DR1 CL1 CL2 M DL1 VDD FCS SHL1 SHL2 GND VEE
40
SPLC100A1
DR2 DL2 DR1 CL1 CL2 M
40
SPLC100A1
Y1-Y40
Y1-Y40 DL1 DR2 VDD DL2 FCS DR1 SHL1 CL1 SHL2 CL2 GND M VEE
V1V2V3V4V5V6
SPLC780D
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R R R R R VR VDD ( +5V ) C C C C C -V or Gnd
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8.4. Applications for LCD
SEG40
SPLC780D COM1
COM11 SEG1
SEG40
COM16 SEG1
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LCD Panel ( Example 2 ) : 5 x 10 dots , 8 characters x 1 line [ 1 / 4 Bias , 1 / 11 Duty ]
LCD Panel ( Example 3 ) : 5 x 8 dots , 8 characters x 2 lines [ 1 / 5 Bias , 1 / 16 Duty ]
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8 characters x 1 line
8 characters x 2 lines
SEG40
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SPLC780D
SPLC780D
SEG1
SEG20
COM1 COM8
SEG21 SEG40
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LCD Panel
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SPLC780D
9. CHARACTER GENERATOR ROM
9.1. SPLC780D - 01
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9.2. SPLC780D - 02
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SPLC780D
9.3. SPLC780D - 03
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SPLC780D
9.4. SPLC780D - 08
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SPLC780D
9.5. SPLC780D - 11
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SPLC780D
9.6. SPLC780D - 12
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SPLC780D
9.7. SPLC780D - 13
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SPLC780D
9.8. SPLC780D - 14
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SPLC780D
9.9. SPLC780D - 15
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SPLC780D
9.10. SPLC780D - 17
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SPLC780D
9.11. SPLC780D - 18
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SPLC780D
9.12. SPLC780D - 19
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SPLC780D
9.13. SPLC780D - 54
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SPLC780D
10. PACKAGE/PAD LOCATIONS
10.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 VSS OSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
d e i f s n U o C ER s u N l I SPLC780Dp M n XXX T u S AR P r o F
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 OSC2 VDD R/W DB0 DB1 CL1 CL2 RS V1 V2 V3 V4 V5 40
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SEG39 SEG40
62 COM16 61 COM15 60 COM14 59 COM13 58 COM12 57 COM11 56 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2
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SPLC780D
10.3. Package Information
QFP 80L Outline Dimensions Unit: Millimeter
D D1
E1
Symbol D D1 E E1 e b A A1 A2 c L1
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Min.
Nom.
Max.
Unit Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter Millimeter
23.20 REF
20.00 REF
0.30 -
0.45
3.40 -
2.90 0.23
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SPLC780D
11. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. prices at any time without notice. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. publication are current before placing orders.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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12. REVISION HISTORY
Date NOV. 04, 2004 Revision # 1.2 1. VIH=2.5V@5V 2. Add COMPARISON OF SPLC780D AND SPLC780C 3. Modify IIL Min/Max JUN. 16, 2004 APR. 23, 2004 1.1 1.0 Add ROM code 1. Remove Preliminary 2. Modify description: Execution time to Execution time (Temp = 25) 3. Add Note2 APR. 01, 2004 0.2 1. Add min. and max. value in Instruction Table 2. Add 8-bit/4-bit data transfer timing sequence example AUG. 06, 2003 0.1 Original 32 - 44 Description Page
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7 7 17 - 18 33
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