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Analysis and Experimental Evaluation of Single-Switch Fast-Response Switching Regulators with Unity Power Factor
K. W. Siu, Y. S. Lee, and C. K. Tse, Member, IEEE
Abstract Based on a single-stage isolated power-factor-corrected power supply (SSIPP or S2 IP2 ) employing a boost powerfactor-correction (PFC) cell, the relationship between the input line voltage and line current of such switching regulators is studied. The conditions for unity power factor are derived. A control scheme to reduce the switch voltage stress while maintaining unity power factor is proposed. Practical implementation of the proposed control scheme is discussed. It is found that, by adding a simple input voltage feedforward to a conventional PWM controller, the switch voltage stress can be much reduced, while keeping the power factor very close to unity. Analysis and experimental results indicate that such a scheme is effective and feasible. Index Terms Fast output-voltage regulation, power-factor correction, SSIPP.

In this paper, a brief review on the principle of singlestage power-factor-corrected switching regulators is rst given. Then, the factors affecting the shape of the input line current of such regulators will be studied. Based on these ndings, a new control scheme to achieve a power factor up to unity will be proposed. A practical version of the control scheme, using only four additional passive components, will be described. The circuit represents a truly simple and low-cost implementation of near-unity power factor S IP . Steady-state analysis based on the new control schemes will be given. Experimental results will also be presented. II. PRINCIPLE OF SINGLE-STAGE POWER-FACTOR-CORRECTED SWITCHING REGULATORS Based on an S IP using a boost PFC cell [2], the principle of operation of single-stage power-factor-corrected switching regulators will be discussed in this section. Fig. 1 shows the simplied schematic of an S IP . This S IP can be understood as a cascaded connection of a boost converter and a forward converter, as identied by the dashedline boxes. The two converters (called cells) share the same electronic switch . Nodes and serve as the output terminals of the boost cell and, at the same time, the input terminals of the forward cell. The presence of diode switch prevents the primary current of transformer from circulating through . During normal operation, the boost cell is operated in discontinuous mode and the forward cell in either continuous or discontinuous mode. In order to achieve a power factor of 1, the waveform of the averaged input current in Fig. 1, (averaged over a switching period of ), should resemble that of the rectied sinewave of the ac mains. With this assumption, the averaged output current of the boost cell should also have the same rectied sinusoidal waveform. This implies that, inherently, the output voltage of the boost cell must contain a ripple component, the amplitude of which would depend on the value of the capacitance and the loading current. Usually, this ripple can be maintained within a few percent by using a sufciently large . The output voltage is regulated via a feedback loop which dynamically adjusts the duty cycle of the electronic switch to keep xed. It should be obvious that, since the duty cycle of the electronic switch is used to regulate the output voltage , it cannot be used at the same time to shape the input

I. INTRODUCTION NTERNATIONAL regulatory standards such as IEC 10003-2 [1] impose restrictions on the magnitudes of the harmonic components of the line current of switch-mode power supplies. Although this problem can be solved by adding a power-factor-correction (PFC) preregulator to the power supply circuit, such a design approach is far from optimum in terms of the size and cost of the power supply. Various alternative schemes have been proposed to optimize the design [3][12]. However, these schemes suffer from one or more of disadvantages such as slow output-voltage regulation [3], [4], complex circuitry [5][12], and low conversion efciency [8]. In order to overcome these disadvantages Redl, Balogh, and Sokal proposed a new family of single-stage isolated powerfactor-corrected power supplies (SSIPP or S IP ) [2]. In this family of power supplies, six S IP topologies are based on the boost PFC cell. However, these boost-based S IP still suffer from the drawback that the line currents drawn are inherently distorted.
Paper IPCSD 9742, presented at the 1996 IEEE Applied Power Electronics Conference and Exposition, San Jose, CA, March 37, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. This work was supported in part by the Research Grants Council of the University Grants Committee of Hong Kong, the Research Committee of The Hong Kong Polytechnic University, and the Industry Department of the Hong Kong Government. Manuscript released for publication May 16, 1997. The authors are with the Department of Electronic Engineering, The Hong Kong Polytechnic University, Kowloon, Hong Kong. Publisher Item Identier S 0093-9994(97)06555-9.

00939994/97$10.00 1997 IEEE

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Fig. 1. An S2 IP2 using a boost PFC cell.

Fig. 2. Low-frequency behavior model of S2 IP2 assuming a continuous-mode-operated forward cell.

current of the boost cell (so as to make it look like the rectied sinewave). In the topologies proposed in [2], the design makes use of the natural shape of the boost-cell input current (under discontinuous mode operation) to achieve a nonideal power-factor correction. It should be noted that an S IP using a buck-boost input cell operating in discontinuous mode will theoretically have a unity power factor. However, it is not the preferred input cell, because a buck-boost converter has a poorer conversion efciency compared with a boost converter. III. CONTROL SCHEME TO ACHIEVE UNITY POWER FACTOR Based on well-established low-frequency behavior models of boost and forward converters [14][16], the relationship between the line voltage and the input current of an S IP with a boost PFC cell will be studied in this section. The conditions for unity power factor will then be derived. Fig. 2 shows the low-frequency behavior model of the S IP given in Fig. 1. For the sake of analytic simplicity, it is here assumed that the boost cell always operates in discontinuous

mode and the forward cell always in continuous mode. The meanings of the symbols used in Fig. 2 are as follows: switching period of ; duty cycle of ; angular frequency of ac line input; (1) (2) , in fact, is the duty cycle of the diode switch where From Fig. 2, the input current is found to be .

or (3) In the actual operation of the S IP , the following assumptions are valid.

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1) The ripple of is small, because is large. 2) The duty cycle of the electronic switch (of the continuous-mode-operated forward cell) is nearly constant within each half cycle of the ac mains. With these assumptions, it can be found that if the term in (3) is made small, the power factor of the S IP will be close to 1 (because is then proportional to ). This requirement is, however, difcult to meet, because it implies a very large , which will place a very large voltage stress on the electronic switch . The large voltage stress is often a limiting factor that prevents the SSIPP from being used in high-voltage circuits. As an alternative solution to the problem, we propose here that the parameter (the switching period of the electronic switch) be modulated according to (4) is the switching period when . If this where could be done, the input current in (3) would be directly proportional to and the power factor would become 1. This new control scheme makes the design of single-switch fastresponse switching regulators with unity power factor possible without the need for a very large . IV. PRACTICAL IMPLEMENTATION OF CONTROL SCHEME An exact implementation of (4) in a pulse width modulation (PWM) IC will require a complex control circuit in the oscillator. However, it will be shown that, in practice, a much simpler control circuit can be used to keep low, while still meeting the IEC 1000-3-2 requirements. Consider the typical sawtooth oscillator circuit (for a UC3844 PWM IC) shown in Fig. 3(a) as an example, where the oscillating period is given by (5) In order to implement the control law of (4), ideally, we need to have, from (4) and (5)

(a)

(b) Fig. 3. Sawtooth generator of UC3844 PWM IC. (a) Normal xed-frequency circuit. (b) Proposed frequency-modulation circuit.

We then have, from (8) and (9), (10) The implementation of even (10) is not straightforward, because it involves the division of by . However, if is replaced by a constant , so that (10) becomes

or (6) However, knowing that (6) as a series: is less than 1, we can express

(11) the implementation will be much easier. A simple circuit that can implement the function of (11) is shown in Fig. 3(b), where (12) (13) The corresponding switching period then given by of the converter is

(7) may then be approximated by (neglecting the The required second and higher order terms) (8) Assume that is chosen to have a dc bias of assuming , so that (9)

(14)

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For a given value of , the range of frequency variation implied is between and . Although in the derivation of (11) the parameter is supposed to replace , it does not mean that must have . a value equal to, or even close to, the averaged value of In order to evaluate the performance of the proposed control scheme, a steady-state analysis will be performed in Section V to nd out the relationships among voltage stress, power factor, and harmonic distortion for different values of . V. ANALYSIS The steady-state analysis will be carried out based on the circuit model of Fig. 2. One of the important parameters of the circuit is the voltage stress across the storage capacitor. This voltage can be determined by equating the average output current of the boost cell during a line half cycle to the average input current of the forward cell during the same half cycle. Referring to Fig. 2, the equality can be written as follows:

^i =Vc as a function of Fig. 4. Voltage ratio V

undesirable continuous-mode operation of the boost cell. To ensure the boost cell is operating in the discontinuous mode, we must have or (19) or

or

(15)

Substituting (14) and the circuit parameters, the following equation for the voltage is obtained: Equation (19) imposes an upper limit for the voltage ratio . To maintain a high voltage ratio, the value of should be chosen such that the voltage ratio is close to that limit at full-load condition. Now, we calculate the power factor of the regulator. The instantaneous input current is given by (20) (17) The rms value of the input current is Fig. 4 is a set of curves showing the relationship between and the voltage ratio , for different values of . (Note ratio indicates a lower voltage stress.) It that a higher can be seen that, for a given value of , the proposed control scheme gives a higher ratio (and, therefore, a lower ). It should be understood that the graphs shown in Fig. 4 are based on the assumption of a continuous-mode-operated forward cell. If the load resistance is sufciently large (or sufciently small), the forward cell will eventually enter into discontinuous mode operation, and the voltage ratio will then stop to decrease [2]. The condition for the forward cell to operate in continuous mode is given by (18) . where Also, it is obvious from Fig. 4 that a larger inductance value of will give a higher (and, therefore, better) voltage ratio. However, too large a value of may result in

or

(16)

where

(21) The power input is

(22) Hence, the power factor of the system is

(23)

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Fig. 7. Measured storage capacitor voltage Vc versus output power.

^i =Vc . Fig. 5. Power factor as a function of voltage ratio V

the peak of the rectangular current through the primary side of transformer (ignoring magnetizing current): (25) The voltage stress of the electronic switch is given by (26) VI. EXPERIMENTAL RESULTS An experimental 100-W (18-V/5.6-A) converter has been built and tested to verify the proposed control scheme. The output voltage of the forward cell is regulated using voltagemode control with a UC3844 IC. The control network is optimized for the forward section to operate in both continuous mode and discontinuous mode. The following is a list of circuit parameters used in the experiment:

^i =Vc . Fig. 6. THD as a function of voltage ratio V

Fig. 5 shows a plot of the power factor versus the ratio for different values of . It is interesting to see that, while the proposed control scheme improves the power factor for large values of (when the voltage stress is low), it also results in a slightly worse power factor (compared with the case of ) for small values of . This, in fact, is due to the approximated control scheme of (11). If the original ideal control scheme of (4) was used, the power factor would always be equal to 1. However, this worsening effect may not appear in the actual operation of the converter, because the ratio can be kept large by properly selecting the operating range of . The total harmonic distortion (THD) of the line current can be found as (24) ratio. It is Fig. 6 shows the THD as a function of the , the proposed control scheme keeps found that with the total harmonic distortion down to about 10% for a ratio up to 0.75 . The current stress of the electronic switch is equal to the sum of the peak of the sawtooth current through and

s H F H F With this set of circuit parameters, from (17) and (19), and achievable voltage the calculated maximum value of ratio are 1.3 and 0.81, respectively. From the set of curves shown in Fig. 4, the optimum value for the parameter is found to be 2. Fig. 7 shows the experimentally measured versus power-level characteristics for different values of . It is found that a reduction of maximum voltage stress from 330 V ( constant) to 250 V is obtained with the proposed control law. Fig. 8 shows the averaged input line voltage and current waveforms when the converter is operating at full-load condition. This is the worst case operating condition with respect to line-current distortion. When the proposed control law of (10) is applied (with ), the THD of the line current is improved from 25% to 15% and the power factor is improved from 0.97 to 0.99 . Fig. 9 shows

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(a)

Fig. 11. Transient response of the output voltage to step changes in the loading current from 100% to 50% and back.

(b)

= K=

Fig. 8. Line voltage and current waveforms. (a) When T is kept constant 0.97, THD 25%). (b) When proposed control law is applied with (p.f. 2 (p.f. = 0.99, THD = 15%).

100 W), the efciency is 80.8%. This efciency is rather low, because an SSIPP is effectively a cascaded connection of two converters. However, the measured harmonic components of the input current comply well with the IEC 1000-3-2 Class D requirement, as shown in Fig. 10. Fig. 11 shows the transient response of the output voltage (middle trace) of the circuit due to step changes in the load current from 100% to 50% and back over a half line cycle (bottom trace). The response is very fast because it is determined solely by the forward cell with its wide-band voltage-regulating loop. It should be noted that the output voltage ripple at peak ac line voltage is smaller than at zero ac line voltage because of the frequency-variation nature of the control scheme. VII. CONCLUSION The factors affecting the power factor of single-switch fastresponse switching regulators using a boost input cell have been studied. A control scheme to reduce switch voltage stress and to improve the power factor has been proposed. A simple and low-cost implementation of the proposed scheme, using only four passive components, has also been discussed. Experimental results have conrmed that single-switch regulators employing the new control scheme can be designed to have a relatively low voltage stress, while maintaining a high power factor. REFERENCES
[1] Electromagnetic Compatibility (EMC)Part 3: Limits, Section 2: Limits for Harmonic Current Emissions (Equipment Input Current 16A Per Phase), IEC 1000-3-2, 1st ed., 1995-03. [2] R. Redl, L. Balogh, and N. O. Sokal, A new family of singlestage isolated power-factor-correctors with fast regulation of the output voltage, in Conf. Rec. IEEE PESC94, Taipei, Taiwan, R.O.C., 1994, pp. 11371144. [3] E. X. Yang et al., Isolated boost circuit for power-factor correction, in Proc. APEC93, pp. 196203. [4] R. Erickson, M. Madigan, and S. Singer, Design of a simple highpower-factor rectier based on the yback converter, in Proc. APEC90, pp. 792801. [5] M. M. Jovanovic, D. M. C. Tsang, and F. C. Lee, Reduction of voltage stress in integrated high-quality rectier-regulators by variablefrequency control, in Proc. APEC94, pp. 569575.

Fig. 9. Converter efciency versus output power.

<

Fig. 10.

Harmonic contents of input current.

the converter efciency at different power levels with . Under the condition of 110-V ac input and 18-V dc output (at

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[6] H. Watanabe, Y. Kobayashi, Y. Sekine, M. Morikawa, and T. Ishii, The suppressing harmonic currents, MS (magnetic-switch) power supply, in Proc. INTELEC95, pp. 783790. [7] M. Brkovic and S. Cuk, Novel single stage AC-to-DC converters with magnetic ampliers and high power factor, in Proc. APEC95, pp. 447453. [8] S. Teramoto et al., A power supply of high power factor, in Proc. Chinese-Japanese Power Electronics Conf. 1992, pp. 365372. [9] M. Madigan, R. Ericson, and E. Ismail, Integrated high quality rectierregulators, in Conf. Rec. IEEE PESC92, pp. 10431051. [10] I. Takabasi and R. Y. Igarashi, A switching power supply of 99% power factor by the dither rectier, in Proc. INTELEC91, pp. 714719. [11] M. H. Kherulawa et al., A fast-response high power factor converter with a single power stage, in Conf. Rec. IEEE PESC91, pp. 769779. [12] Y. Jiang and F. C. Lee, Single-stage single-phase parallel power factor correction scheme, in Conf. Rec. IEEE PESC94, Taipei, Taiwan, R.O.C., 1994, pp. 11451151. [13] K. H. Liu and Y. L. Lin, Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters, in Conf. Rec. IEEE PESC89, pp. 825829. [14] S. Cuk and R. D. Middlebrook, Advances in Switched-Mode Power Conversion, vols. I and II. Millbrae, CA: Tesla, 1983. [15] Y. S. Lee, Computer-Aided Analysis and Design of Switch-Mode Power Supplies. New York: Marcel-Dekker, 1993, ch. 2. [16] Y. S. Lee, D. K. W. Cheng, and S. C. Wong, A new approach to the modeling of converters for SPICE simulation, IEEE Trans. Power Electron., vol. 7, pp. 741753, Oct. 1992. [17] Y. S. Lee and K. W. Siu, Single-switch fast-response switching regulators with unity power factor, in Proc. APEC96, San Jose, CA, 1996, pp. 791796.

Y. S. Lee received the M.Sc. degree from the University of Southampton, Southampton, U.K., and the Ph.D. degree from the University of Hong Kong, in 1974 and 1988, respectively. He was with Cable & Wireless, Rediffusion Television, and the General Post Ofce, all in Hong Kong, before joining The Hong Kong Polytechnic University, Kowloon, in December 1969 as a Member of the Academic Staff. He is currently a Professor in the Department of Electronic Engineering. He is the author of the book Computer-Aided Analysis and Design of Switch-Mode Power Supplies (New York: MarcelDekker, 1993) and 60 technical papers on the design of power electronics and analogue circuits. Dr. Lee is a fellow of the Institution of Electrical Engineers (U.K.) and the Hong Kong Institution of Engineers.

C. K. Tse (M90) received the B.Eng.(Hons) and Ph.D. degrees from the University of Melbourne, Melbourne, Australia, in 1987 and 1991, respectively. He is currently an Assistant Professor at The Hong Kong Polytechnic University, Kowloon, where his research interests include circuit theory and power electronics. Dr. Tse was awarded the L. R. East Prize by the Institution of Engineers, Australia, in 1988. He is a Chartered Professional Engineer in Australia.

K. W. Siu received the B.Eng.(Hons.) degree in electronic engineering in 1992 from The Hong Kong Polytechnic University, Kowloon, Hong Kong, where he is currently working toward the Ph.D. degree in power electronics. His research interests include power-factor correction circuits for acdc converters and computer-aided design of switching power supplies.