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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. X, NO. X, MONTH 20XX 1
A Memristor Spice Implementation and a New
Approach for Magnetic Flux Controlled Memristor
Modeling
Daniel Batas, Member, IEEE, Horst Fiedler, Member, IEEE
AbstractThis paper introduces a behavior model of a mem-
ristive soild-state device for simulation with a SPICE compat-
ible circuit simulator. After showing the underlying functional
mechanics and model equations of a memristor the SPICE
equivalent circuit based on a charge controlled memristor is
presented and discussed. Hereafter a magnetic ux controlled
memristor model is introduced including technical description
and SPICE implementation. It is shown that the presented SPICE
models meet the requirements for simulations of multi memristor
circuits.
Index Termssemiconductor device modeling, hysteresis, cir-
cuit simulation, SPICE
I. INTRODUCTION
T
HE three traditional fundamental circuit elements are
resistors (R), capacitors (C) and inductors (L). All of
them have two terminals only. These basic devices are based
on the conjunction of the four electrical base units charge
q, current i, voltage v and magnetic ux . With two of
these units combined a total of six combinations is possible
theoretically. Two of them are already dened via time variable
t: i = dq/dt and v = d/dt. The three basic circuit elements
R, C and L can be obtained via derivations of the base units:
R = du/di, C = dq/du and L = d/di. Because one
correlation between two variables was missing, a further basic
circuit element was postulated in [1] in the year 1971 called
memristor: M = d/dq. It took a long time to establish a
link from this theoretical denition to a physical realization
of such a device with its predicted memristive properties [2].
A memristor can be thought of as a resistive device that
varies its resistance in dependence of its current or magnetic
ux. It is a basic two terminal device and cannot be built up out
of the other 3 basic circuit elements. By a formal substitution
of d and dq in the denition of M with their time depending
expressions (see above) the unit of M is revealed as (ohm).
The authors in [2] describe a nano scale two layer struc-
ture which has the properties of a memristor: the bottom
layer consists of stoichiometric titanium dioxide which is an
D. Batas and H. Fiedler are with the Department of Electrical Engineering
and Information Technology, Integrated Systems Intitute, Technische Uni-
versit at Dortmund, Emil-Figge-Str. 68, 44227 Dortmund, Germany. e-mail:
daniel.batas@ieee.org, horst.edler@ieee.org
Manuscript received June 5, 2009; revised October 23, 2009. The review
of this paper was arranged by Associate Editor Lars-Erik Wernersson.
Copyright (c) 2009 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org .
Digital Object Identier XX.XXXX/TNANO.20XX.XXXXXXX
electrical insulator. The upper layer is also TiO
2
but with a
small number of intended oxygen vacancies. These vacancies
act as electrically charged 2
+
-dopants making this layer a
semiconductor with high conductance. If an external electrical
eld is strong enough the dopants can be shifted bidirectionally
in theory [3]. With dopants moved towards the insulator side
the width of the insulator is reduced as well as the width
of the semiconductor is increased. Thus the borderline of the
two layers has moved and the electrical properties of the
structure have changed. Due to geometries of the insulator
layer in the nanometer range a tunnel current is possible.
According to [2] it is very important that the geometries of
the structure especially the thickness of both layers are in the
nanometer scale because this effect is about one million times
stronger in the nanometer scale than in the micrometer scale.
The memristive effect is not limited to TiO
2
([4] - [7]) but
could also be observed on nickel oxide ([8],[9]) and other
materials ([10],[11]). All they have in common is an externally
steered non-volatile change of resistance which leads to the
characteristic hysteresis curve in the I/V diagram (Fig. 7).
II. MODEL EQUATIONS
Assigning w(t) as the actual width of the semiconductor
layer and D as the maximum drift distance for w, [2] dened
the voltage/current-relation of a charge controlled memristor
as:
v(t) =

R
ON
w(t)
D
+R
OFF

1
w(t)
D

i(t) . (1)
The voltage v(t) is depending on both the actual current and
resistance. Variable w(t) is limited to values between zero
and D. The charge steering property of the device is obtained
from:
w(t) =
V
R
ON
D
q(t) . (2)
This shows a linear dependence of w(t) from q(t) resulting
in a rst order model with simple linear drift of dopants. By
inserting (2) into (1) the resistance results in a time depending
value of the charge q(t) , with
V
representing the mobility
of the dopants. Therefore, the state of the device w(t) is
depending on the amount of charges that have moved through
the memristor. The corrigendum for [2] in [12] has no impact
on (1) nor (2).

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2 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. X, NO. X, MONTH 20XX
III. SPICE IMPLEMENTATION
In [1] an equivalent circuitry for a memristor was proposed
using discrete active circuit elements. Unfortunately the count
of active devices needed to emulate the memristive effect is so
high that it cannot be applied to simulate circuits with a high
memristor count. Because of this reason it is more appropriate
to describe the memristive behavior. Since a memristor is a
primitive device we created a behavior model of a memristor at
device level using the SPICE circuit description language. This
implementation is not bound to other physical spice models
or devices since it applies the use of ideal dependent sources
only.
In SPICE the memristor is represented by a two terminal
subcircuit block. Its current path contains two circuit elements:
a voltage source for modeling the voltage drop across the
device (left part of Fig. 1) and a tiny series resistance.
Since q(t) has to be determined the dependent voltage source
Ememristor is used to measure the actual branch current.
Some SPICE derivates like LTspice offer an additional series
resistance for voltage sources. Unfortunately this is not stan-
dard for all derivates of SPICE, therefore a further resistor
(Rser) is applied in the current path of the memristor. Its
value is set near to zero to affect the generated voltage of
the memristor at a minimum. The presence of this resistor is
important for practical reasons only because the user should
be able to apply any kind of external voltage or current source
to the memristor subcircuit without considering about any
additional series resistors in the main circuit hierarchical level.
The default value for this series resistance in the memristor
subcircuit block should be set less than 1/1000 of R
ON
.
However, if this value for Rser is chosen too small conver-
gence problems can occur. Since q(t) from (2) is the time
.model low_level_switch SW Ron=1G Roff=1n Vt={offset}
.model high_level_switch SW Ron=1n Roff=1G Vt={D+offset}
pos
Rser 1m
low_level_switch
Cw
1
neg
Vlow
{offset}
w
high_level_switch
Vhigh
{D+offset}
Ememristor
neg
.PARAM Ron=100
.PARAM Roff_Ron=160
.PARAM w0=0.1
.PARAM mu=1E14
.PARAM D=10n
.PARAM Roff=Roff_Ron*Ron
.PARAM offset=1n
.ic V(w)={w0*D+offset}
V=(Ron*(V(w,neg)offset)/D+Roff*
(1(V(w,neg)offset)/D))*I(Ememristor)
Gi2i
I=I(Ememristor)*Ron*mu/D
Fig. 1. Schematic of the memristor SPICE implementation
integral of the measured current it is fed into capacitor Cw
via Gi2i. Equation (2) requires a constant multiplication which
is also done by Gi2i (Fig. 1), thus the node potential w in the
schematic represents the correct value of w(t) from (2). The
problem of limiting the boundaries for the memristive effect
of w(t) is solved using elementary SPICE switches. These
switches are an integral part of the SPICE language since
Berkeley SPICE version 3. Many derivative products offer
these switches, others like ELDO need different commands
for their switch implementations (Fig. 5). As shown in the
.model cards the on- and off-resistance of these switches
are set to extreme values. When a switch is controlled into on-
state, node potential w is connected to a voltage source which
prevents a further increase/decrease of its potential. With this
construct w is limited to a dened upper and lower voltage
level. The inner loop is closed by dependent voltage source
Ememristor which implements model equation (1). It gives
a dynamic feedback to the branch current inside the memristor
depending on w(t). To avoid numerical difculties at w = 0
an offset is used for the lower limit of potential w (Fig. 3
applies a more adequate offset of 1V ).
Figure 1 also shows that this SPICE implementation is
highly parameterized. As depicted in the .PARAM cards from
Fig. 1, 4 and 5 the default values used to generate Fig. 2 and 3
were taken from [2] to indicate compliance of the theoretical
model with the SPICE implementation. In detail adjustable
model parameters are Ron, w0, mu, and D with direct relation
to model equations (1) and (2), and Roff_Ron as the ratio
of the maximum-to-minimum resistance of the device (Roff
is calculated automatically and offset is for internal use
only). If one or all of these parameters is left out by the
user at instantiation of the device these default values for each
memristor will be used for simulation. The non-linear behavior
of a memristor is depicted in Fig. 2 with an external voltage
of v(t) = 1V sin(
0
t) and
0
= 2 1/2 Hz.
0.5 1 1.5 2
c
u
r
r
e
n
t

[
u
A
]
30
60
90
120
0
30
60
90
120
voltage
current
w(t)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
v
o
l
t
a
g
e

[
V
]
0
0.2
0.4
0.6
0.8
0
w
(
t
)
/
D
time [s]
1
1
Fig. 2. SPICE simulation of the time domain behavior for a charge controlled
memristor applied with physical data and stimulus from [2]
Although the current is in phase with the voltage its shape
isnt linear referred to the sinusodial input signal. The bottom
graph of Fig. 2 shows the time dependence of w(t)/D. The
bias for w was set to 0.1 D = 1 nm and D = 10 nm.
All parameters for the simulation of Fig. 2 were set to values
of the original data from [2] to show exact compliance of
this SPICE implementation to the model introduced in [2].
In this case w(t) never reaches its boundaries. In Fig. 3 the
characteristic I/V curve of a memristor showing hysteresic
behavior is depicted. Increasing the frequency of the external
voltage leads to a smaller q(t) resp. w(t), thus the hysteresic
behavior of the memristor is decreased until asymptotically
passing over to the characteristic curve of a conventional
resistor.
In numerical simulations a rapid change of the control

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BATAS et al.: A MEMRISTOR SPICE IMPLEMENTATION AND A NEW APPROACH FOR MAGNETIC FLUX CONTROLLED MEMRISTOR MODELING 3
voltage for the switches could cause difculties for the internal
timestep variable of the simulator. Therefore a more simulation
friendly method of limiting w(t) has been developed. Figure
4 shows the schematic of the same memristor model using
diodes.
120
120
90
60
30
60
90
30
0
i(v)
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1
voltage [V]
c
u
r
r
e
n
t

[
u
A
]
Fig. 3. I/V characteristic of a charge controlled memristor
.PARAM Vforward_high=1.03 wmax=Dscale+offsetVforward_high
.PARAM Vforward_low=0.9 wmin=offset+Vforward_low
pos
Rser 1m
.PARAM Ron=100
.PARAM Roff_Ron=160
.PARAM w0=0.1
.PARAM mu=1E14
.PARAM D=10n
.PARAM Roff=Roff_Ron*Ron
.PARAM offset=1 scaling=1E9
.PARAM Dscale=D*scaling
.ic V(w)={w0*Dscale+offset}
Cw
1
neg
w
Dlower_level
Dupper_level
Vhigh
{wmax}
Vlow
{wmin}
Gi2i
I=scaling*I(Ememristor)*Ron*mu/D
neg
V=(Ron*(V(w,neg)offset)/Dscale+Roff*
(1(V(w,neg)offset)/Dscale))*I(Ememristor)
Ememristor
Fig. 4. Schematic of the memristor model using diodes
The switching behavior of diodes have a softer characteristic
compared to ideal switches. Using diodes instead of switches
results in a more robust memristor model, however, the dis-
advantage is that w(t) does not exactly follow (2) anymore
when w(t) is close to each of the boundaries. Nevertheless the
authors in [2] proposed to add a window function (Dw)w for
w(t) to enhance the linear drift model for results to be closer to
their measurements of manufactured memristors. Thus using
diodes for the boundaries should be no disadvantage at all.
Since the value for the forward voltages of the diodes are
depending on the operating point resp. the current that each
diode has to conduct the user either has to adjust these absolute
values for Vforward_low and Vforward_high or has to
accept a slightly shifted value for the modeled borderlines of
w(t). In Fig. 5 a netlist for ELDO is printed wich makes
use of SPICEs subcircuit feature to be able to simulate an
arbitrary count of memristors in one simulation run. Ghigh
and Glow show that some SPICE derivates like HSpice or
ELDO offer a voltage controlled resistor (V CR) directly. If
a certain derivate of SPICE shows convergence problems, set
GMIN either as a global option or add a very weak conductor
( 1mS) in parallel to Cw.
Compared to [13] we implemented the charge controlled
memristor model from [2] into a simple netlist and simple
schematics without applying operational ampliers nor logic
gates, thus making them easy to comprehend. The netlist
and schematics are for direct usage and suited for both, the
charge controlled and the magnetic ux controlled memristor
model ( section IV), with either a low device count. The
SPICE implementations from Fig. 1, 4 and 5 are highly
parameterizable. Even the terms of the behaviorable sources
can be adjusted easily. The use of diodes (Fig. 4) is preferable
when putting emphasis on robust simulations.
*
charge controlled memristor implementation for ELDO
.SUBCKT memristor pos neg PARAM: Ron=100 Roff_Ron=160
+ D=10n w0=0.1 mu=1E-14
.PARAM Roff=Roff_Ron
*
Ron
.PARAM offset=1 scaling=1E9
.PARAM Dscale=D
*
scaling
Rser pos ser 1m
Ememrist ser neg VALUE={(Ron
*
(V(w,neg)-offset)/Dscale
+ +Roff
*
(1-(V(w,neg)-offset)/Dscale))
*
I(Ememrist)}
Gi2i neg w VALUE={scaling
*
I(Ememrist)
*
Ron
*
mu/D}
Cw w neg 1
.ic V(w)={w0
*
Dscale+offset}
Vupper_level upper_level neg DC {Dscale+offset}
Vlower_level lower_level neg DC {offset}
Ghigh w upper_level VCR PWL(1) w neg -1 1G {Dscale+
+ offset-1n} 1G {Dscale+offset} 1n
Glow w lower_level VCR PWL(1) w neg -1 1n {offset-1n}
+ 1n {offset} 1G
.ENDS
Fig. 5. ELDO subcircuit netlist of the memristor macro model
IV. ALTERNATIVE MODEL
The shown SPICE implementation (macro model) for a
charge controlled memristor model exactly reproduces the
results from [2]. However, these simulation results do not
have a good compliance - not even qualitatively - with the
characteristic form of I/V curves of manufactured devices.
Therefore the following equations (3) to (9) try to approach
memristor modeling from a different point of view to get a
closer match to the measured curves from [2],[6],[7],[8],[10]
or [11] even with a simple linear drift of w. Besides the
charge steering mechanism of a memristor modelled in [2],
[1] also dened a functional relationship for a memristor
which explains the memristive behavior in dependence on its
magnetic ux:
i(t) = W

(t)

v(t) . (3)
Variable W() represents the memductance which is the
reciprocal of memristance M. Here a mechanism is demanded
that maps the magnetic ux as the input signal to the current
that is owing through the memristor. The magnetic ux
is the integral of voltage v(t) over time: =

v(t) dt.
We can assume that an external voltage which is applied to
the previously described two-layer structure has an inuence
on the movable 2
+
-dopants over time. The width w(t) of
the semiconductor layer is depending on the velocity of the
dopants v
D
(t) via the time integral:
w(t) = w
0
+

t
0
v
D
()d . (4)

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4 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. X, NO. X, MONTH 20XX
The drift velocity v
D
in an electric eld E is dened via its
mobility
D
:
v
D
(t) =
D
E(t) (5)
and the electric eld E is connected with the voltage via
E(t) =
v(t)
D
(6)
with D denoting the total thickness of the two-layer structure
(D = t
OX
+ t
SEMI
). Due the good conductance of the
semiconductor layer the electric eld is applied to the time
depending thickness of the insulator layer t
OX
for the most
part (due to v(l) =

E dl). However, this was neglected for

reasons of simplication. If we combine (4), (5) and (6), we
obtain:
w(t) = w
0
+

D
D

t
0
v()d = w
0
+

D
D
(t) . (7)
This equation shows a proportional dependence of the width w
from the magnetic ux . Since the thickness of the insulator
layer is in the low nanometer region a tunnel current or
equivalent mechanism is possible. The magnetic ux slightly
decreases the thickness of the insulator layer wich is the barrier
for the tunnel current. This current rises exponentially with a
reduction of the width t
OX
() (the exponential dependence
is deducible from the quantum mechanic wave function).
For modeling the memristor current it is arbitrary on which
absolute location of the exp()-function w
0
= 0 is assigned to
because the slope is e over the whole input range. We have
chosen the exponent to vary between 0 and ln(R
OFF
/R
ON
)
which leads to a memductance of:
W

=
1
R
OFF
exp

w(t)
D
ln

R
OFF
R
ON

. (8)
Since (7) shows that w(t) is a function of the magnetic ux ,
(3) is satised. From this it follows that the I/V characteristic
of a magnetic ux controlled memristor can be described
through:
i(t) =
1
R
OFF
exp

w(t)
D
ln

R
OFF
R
ON

v(t) . (9)
Figure 6 shows a SPICE implementation for the model of
a magnetic ux controlled memristor that is a modication of
Fig. 1 to meet (9) and (7).
.model high_level_switch SW Ron=1n Roff=1G Vt={Dscale+offset}
.model low_level_switch SW Ron=1G Roff=1n Vt={offset}
.PARAM Roff=Roff_Ron*Ron
.PARAM offset=1 scaling=1E9
.PARAM Roff_Ron=160
.PARAM mu=1E14
.PARAM Ron=100
.PARAM w0=0.1 D=10n
.PARAM Dscale=D*scaling
.ic V(w)={w0*Dscale+offset}
pos
neg
Gmemristor
offset)/(Dscaleoffset)*log(Roff/Ron))
I=V(pos,neg)/Roff*exp((V(w,neg)
{scaling*mu/D}
low_level_switch
1
neg
Vlow
{offset}
w
high_level_switch
pos
Vhigh
{Dscale+offset}
Gv2i
Cw
Fig. 6. Schematic of the magnetic ux controlled memristor model
In fact, the quality of this magnetic ux controlled model
can only be validated by measurements on physical devices.
Because of this, the spice implementation has several param-
eters that can be modied to actual need. It should serve
as a base for further adjustment to measurements. Equation
(3) to (7) explain the dependence of the boundary w from
the magnetic ux as a input variable based on theoretical
relationships of these variables. However the microscopic
explanation of the observed current is unresolved further on.
The primary purpose of this paper is to present a SPICE
implementation for research of integrated circuits applying
memristors. For such a complex non-linear device like the
memristor simulation with SPICE is essential and common
practice in circuit development. Therefore, for the missing
relationship between w(t) and i(t) we here assume a tunneling
mechanism which is only one possible explanation but other
microscopic mechanisms are possible as well. However, this
exponential behavior was also proposed in [6],[7],[11] and
[14]. By inserting the exp()-term of the tunnel current char-
acteristic into a SPICE implementation the resulting curves t
clearly better to measured curves (from [2],[6],[7],[8]) than the
charge controlled memristor model proposed in [2]. However,
when future experimental results suggest a different analytical
functional dependence, it is straight forward to adjust the
SPICE model equations.
magnetic flux controlled
3
2
1
0
1
2
3
c
u
r
r
e
n
t

[
m
A
]
1 0.5 0 0.5 1
voltage [V]
Fig. 7. I/V characteristic of a magnetic ux controlled memristor applied
with the same physical data and stimulus from [2]
We are aware that assuming a tunnel current for the missing
link between (7) and (8) leads to an additional exponentional
dependence on the applied voltage but we have neglected
this component so far because we only know of published
characteristic hysteresis plots rather than numerical results
from manufactured devices. In addtition the linear drift model
which is part of both memristor models has to be replaced
by a non-linear drift that is based on studies of manufactured
devices. To take care of additional - yet unexplored - effects
when the borderline reaches its limits a different window
function can be inserted into (8) resp. (9) for w(t) instead of
the actual linear one. However, even by now the magnetic ux

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BATAS et al.: A MEMRISTOR SPICE IMPLEMENTATION AND A NEW APPROACH FOR MAGNETIC FLUX CONTROLLED MEMRISTOR MODELING 5
controlled memristor model already shows a good conformity
with measured characteristic curves (Fig. 7). Simulations could
also verify that the time t
0
for a full stroke of w(t) with
t
0
=
D
2

D
v
0
(10)
is exactly predicted by this model: for a constant voltage of
1V ,
D
= 10
10
cm
2
/(V s) and D = 10 nm the time needed
to do a full stroke is 10 ms according to physical data from
[2].
V. SIMULATION OF MEMRISTOR CIRCUITS
So far, memristive devices have good looking properties to
be used in future high density random access memory chips.
They have a simple cell structure, device geometries in the
low nanometer scale and are suitable for three dimensional
integration. However, before [2] was published the effect
of non-volatile resistive switching was already studied for
use in ReRAMs resp. RRAMs due to mentioned reasons
([7],[9],[10]). In this context there are even further possibilities
for similar non-volatile memory devices that are based on
effects like phase change (PRAM, [15]) or magneto-resistance
(MRAM, [16]). All in common is the possibility for an exter-
nal change of the internal electrical resistance of the structure.
The effort in modelling memristance is simple compared
to PRAMs because phase change SPICE implementations
have to deal with the complex phase change mechanism
([17],[18],[19]).
The same properties led to other possible elds of applica-
tions such as alternative memristor logic ([20]), defect-tolerant
circuits ([21]) or logic threshold circuits which function similar
to human synapses ([3]). The hysteresis property of memristors
also seems to be useful for analog circuits, which led us
develop the SPICE implementation. Therefore it is shown that
this implementation is suited for simulation of multi memris-
tor circuits. Using SPICE is common practice in all device
level simulations and will help in the development of new
circuit architectures which apply new integrated devices. For
a exible application of the shown memristor equivalent circuit
the dened parameters can be setup at subcircuit instantiation
for each memristor. It is possible to connect the memristor
equivalent circuit to either a voltage or current source. Figure
8 depicts a demo circuit which does a logical AND operation
of input signals in1 and in2.
M1
Vin1
in2
in1
Vin2
M2
out
M3
M4
Fig. 8. Demonstration circuit using memristors
First M3 and M4 have to be initialized to get into high-
impedance state wich is done best by applying high level
on both inputs (Fig. 9: t < 10 ms). When this is done M3
and M4 remain high-ohmic and act as conventional resistors.
Both inputs can be switched into low state (t=10 ms). At time
t=40 ms one of the input signals is switched into high state
(here in1) and forces the other input memristor (M2) to drift
into low-ohmic state. Therefore node out remains just about
zero when the memristor (M2) has reached its most low-ohmic
state. Only when both of the input signals are switched to high
level (at t=100 ms) a small current is forced to ow through
M3 and M4 resulting in a voltage drop. This characteristic
curve is due to the non-linear behavior of memristors and is
not possible when using resistors only.
1
v(in2)
i
n
2

[
V
]
1
v(in1)
i
n
1

[
V
]
0
0.2
0.4
0.6
0.8
o
u
t

[
V
]
0 40 80 120 160 200
time t [ms]
1
0
0
v(out)
Fig. 9. Transient SPICE simulation of the demo circuit from Fig. 8 applying
the charge controlled macro model with a minimum drift time t
0
= 10 ms
(for a full stroke), R
ON
= 100 , R
OFF
/R
ON
= 160, D = 10 nm and
v
0
= 1 V according to physical data from [2]
Compared to a standard CMOS AND gate this demo circuit
has quite a few disadvantages, especially that a small current
is taken from the sources of the input signals. It is intended
as a demo only to prove that simulation of a memristor
circuit is possible using conventional simulation programs in
combination with the presented SPICE implementation. When
thinking of circuits with a very high count of memristors
such as memristor memory circuits with millions of devices
to simulate, a behavior model of a memristor written in
Verilog-A or VHDL-AMS would speed up simulation time
further but this also requires a (non-standard SPICE) simulator
with capabilities to simulate parameter driven devices and
behavioral scripts at the same time.
VI. CONCLUSION
In summary, a SPICE implementation for a charge con-
trolled memristor model is presented based on equations pub-
lished in [2]. The implementation is discussed and considers

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6 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. X, NO. X, MONTH 20XX
all relevant aspects for simulation, thus enabling analysis and
design of complex circuits. To get a closer match of simulation
results to measured curves an alternative new model describes
the behavior of a memristor from another viewpoint which
is applying a mechanism that is controlled by the magnetic
ux. Although microscopic details of the relationship between
memductance and the tunnel current is not nally solved
resp. proven simulation results already show good conformity
to published measurements. However, both models are still
based on simplied assumptions like linear drift of dopants. In
section V the SPICE implementation based on [2] is used for
a sample memristor circuit to verify that the implementation is
suited for simulations of multi memristor circuits in general. It
is highly parameterizable and allows the simulation of different
pysical memristor devices e.g. those based on TiO
2
or NiO.
Through this validation of new ideas in circuit development
should be enabled.
Memristor circuitry based on TiO
2
is not very fast due
to low dopant mobility. Furthermore the hysteresis behavior
increases towards low frequencies and high voltages. Similar
devices based on other materials like the CBRAM from [22]
show a quite faster switching bahavior. A big advantage of
memristors in generell is the simple physical structure suited
for integration in the low nanometer scale, particularly when
thinking of a 3D integration.
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Daniel Batas (M06) recieved the Dipl.-Ing. degree
and Dr.-Ing. degree in electronic enginieering from
the University of Dortmund, Dortmund, Germany,
in 1997 and 2004 respectively. Currently he is
working for his postdoctoral lecture qualication at
the Integrated Systems Institute, Technische Univer-
sit at Dortmund, Dortmund, Germany. His research
interests include design and development of inte-
grated analog CMOS circuits and development of
computer-aided design tools for circuit sizing of
integrated CMOS circuits.
Horst Fiedler (M81) received the Dipl.-Ing. degree
in electrical engineering from the University of the
Ruhr, Bochum, Germany, in 1978 and the Dr.-Ing.
degree from the University of Dortmund, Dortmund,
Germany, in 1981. He joined the Fraunhofer Institute
of Microelectronic Circuits and Systems, Duisburg,
Germany in 1985 where he managed a department
for analogue and digital integrated circuit design. In
1990 he was appointed Professor at the University of
Duisburg, Duisburg, Germany. Currently, he is a full
Professor at the TU Dortmund, Dortmund, Germany.
His current research interests include the design and fabrication of integrated
microsystems comprising mixed-signal circuits as well as microstructured
non-electrical components.