VLSI

Sl.No PSVLSI001 PSVLSI002 PSVLSI003 PSVLSI004 PSVLSI005 PSVLSI006 PSVLSI007 PSVLSI008 PSVLSI009 PSVLSI010 PSVLSI011 PSVLSI012 PSVLSI013 PSVLSI014 PSVLSI015 PSVLSI016 PSVLSI017 PSVLSI018 PSVLSI019 PSVLSI020 PSVLSI021 PSVLSI022 PSVLSI023 PSVLSI024 PSVLSI025 PSVLSI026 PSVLSI027 PSVLSI028 PSVLSI029 PSVLSI030 PSVLSI031 PSVLSI032 PSVLSI033 Topic Pipelined Radix-2k Feed forward FFT Architectures

email id:vlsi@pantechmail.com Field

An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic FFT Architectures for Real-Valued Signals Based on Radix-23& Radix-24 Algorithms Achieving Reduced Area By Multi-Bit Flip Flop Design
IEEE 2013

Communication Systems, Architectural Designs and Low Power Design (Memories, Flip-Flops, Counters, Aritmetic Cores and

Design of High Speed Low Power Viterbi Decoder for TCM System

High-Throughput Compact Delay-Insensitive Asynchronous NOC Router Design of Low Energy, High Performance Synchronous and Asynchronous 64-PointFFT An Efficient High Speed Wallace Tree Multiplier Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS Low-Power Digital Signal Processing Using Approximate Adders Performance Evaluation of FFT Processor Using Conventional and VedicAlgorithm A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier Low-Power Digital Signal Processing Using Approximate Adders Asynchronous Fine-Grain Power-Gated Logic Comparison of Static and Dynamic Printed Organic Shift Registers A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction Sub threshold Dual Mode Logic

A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor Performance Analysis of a New CMOS Output Buffer A Current-Starved Inverter-Based Differential Amplifier Design for Ultra-Low Power Applications A low power single phase clock distribution using VLSI technology Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop Asynchronous Design of Energy Efficient Full Adder

Reconfigurable Processor for Binary Image Processing

IEEE 2013

An Efficient Denoising Architecture for Removal of Impulse Noise in Images Optical Flow Estimation for Flame Detection in Videos Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes

www.pantechsolutions.net | www.pantechproed.com 2013 PantechProEd Private Limited.

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Digital Image Processing Applications (Steganography, Surveillance termarkingmentation, Enhancement)

Hardware Implementation of a Digital Watermarking System for Video Authentication

IEEE 2013

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Analog and Digital Circuits Design)

Protocol Designs

VLSI
PSVLSI034 PSVLSI035 PSVLSI036 PSVLSI037 PSVLSI038 PSVLSI039 PSVLSI040 PSVLSI041 PSVLSI042 PSVLSI043 PSVLSI044 PSVLSI045 PSVLSI046 PSVLSI047 PSVLSI048 PSVLSI049 PSVLSI050 PSVLSI051 PSVLSI052 PSVLSI053 PSVLSI054 PSVLSI055 PSVLSI056 PSVLSI057 PSVLSI058 PSVLSI059 PSVLSI060 PSVLSI061

email id:vlsi@pantechmail.com Background Subtraction Based on Threshold detection using Modified K-Means Algorithm Modified Gradient Search for Level Set Based Image Segmentation Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter An Efficient Modified Structure Of CDF9/7 Wavelet Based On Adaptive Lifting With SPHIT For Lossy To Lossless Image Compression. A Fast Low-Light Multi-Image Fusion with Online Image Restoration An Analysis of SOBEL and GABOR Image Filters for Identifying Fish Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation Shadow Removal for Background Subtraction Using Illumination InvariantMeasures Least Significant Bit Matching Steganalysis Based on Feature Analysis
Cryptography Real Time / Embedded Applications (ZIGBEE, Communication Systems, Architectural Designs and Algorithm Protocol Designs RF, Sensors, GSM, GPS) IEEE 2013

Teaching HW/SW Co-Design With a Public Key Cryptography Application FPGA Implementation of Pipelined Architecture For SPIHT Algorithm Parallel AES Encryption Engines for Many-Core Processor Arrays Reverse Circle Cipher for Personal and Network Security Prototype of a Fingerprint Based Licensing System For Driving A Topology-Based Model for Railway Train Control Systems Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing A Smarter Toll Gate Based on Web Of Things An Interactive RFID-based Bracelet for Airport Luggage Tracking System The Security Technology and Tendency of New Energy Vehicle in Future RFID-based Tracking System Preventing Trees Extinction and Deforestation RFID-based Location System for Forest Search and Rescue Missions Secure Transmission in Downlink Cellular Network with a Cooperative Jammer Pipelined Parallel FFT Architectures via Folding Transformation High Speed and Area Efficient Vedic Multiplier Multifunction RNS modulo (2n1) Multipliers Based on Modified Booth Encoding BPSK System on Spartan 3E FPGA

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation

PSVLSI062 PSVLSI063 PSVLSI064 PSVLSI065

Teaching And Research In FPGA Based Digital Signal Processing Using Xilinx System Generator Platform-Independent Customizable UART Soft-Core Input/ Output Peripheral Devices Control through Serial Communication using Microblaze Processor Real Time Smart Car Lock Security System Using Face Detection and Recognition

www.pantechsolutions.net | www.pantechproed.com 2013 PantechProEd Private Limited.

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IEEE 2012

Design of Modified Low Power Booth Multiplier

IEEE 2013

IEEE 2013 Softcore Processor Design (Microblaze, Xilinx Platform Studio)

VLSI
PSVLSI066 PSVLSI067 PSVLSI068 PSVLSI069 PSVLSI070 PSVLSI071 PSVLSI072 PSVLSI073 PSVLSI074 PSVLSI075 PSVLSI076 PSVLSI077 PSVLSI078 PSVLSI079 PSVLSI080 PSVLSI081 PSVLSI082 PSVLSI083 PSVLSI084 PSVLSI085 PSVLSI086 PSVLSI087 PSVLSI088 PSVLSI089 PSVLSI090 PSVLSI091 PSVLSI092 PSVLSI093 PSVLSI094 PSVLSI095 PSVLSI096 PSVLSI097

email id:vlsi@pantechmail.com Implementation of a Home Automation System through a Central FPGA Controller
(Xilinx ISE, Place and Core Processor Design (SoftcoreLow Power Applications (Microwind& Security Algorithms DSCH)

IEEE 2012

An improved three-factor authentication scheme using smart card with biometric privacy protection The Ship Monitoring and Control Network System Design Image Segmentation via Normalized Cuts and Clustering Algorithm VLSI Architecture of Arithmetic Coder Used in SPIHT Edge Detection of Angiogram Images Using the Classical Image Processing Techniques Median Filter on FPGAs Analysis of CT and MRI Image Fusion using Wavelet Transform Background Subtraction Algorithm for Moving Object Detection in FPGA An Auto-adaptive Edge-Detection Algorithm for Flame and Fire Image Processing Gesture Recognition Using Field Programmable Gate Arrays High Speed Implementation of RSA Algorithm with Modified Keys Exchange

An efficient FPGA implementation of the Advanced Encryption Standard Algorithm A Novel Architecture for VLSI Implementation of RSA Cryptosystem Models Simulation based on HDL-Simulink Platform Single Phase Clocked Quasi Static Adiabatic Tree Adder A Novel High-Performance CMOS 1 Bit Full-Adder Cell Design of Low Voltage Low Power Operational Amplifier

Low-Power and Area-Efficient Carry Select Adder Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design An Evaluation of CMOS Adders in Deep Submicron Processes Design Low Power 10T Full Adder Using Process and Circuit Techniques A Novel High Speed & Power Efficient Half Adder Design Using MTCMOS Technique in 45 Nanometre Regime Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

www.pantechsolutions.net | www.pantechproed.com 2013 PantechProEd Private Limited.

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IEEE 2012 Low Power Applications (Tanner EDA, W-Edit, S-Edit, L-Edit, T-Spice)

IEEE 2012

Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting

IEEE 2012

A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL

Microblaze)

IEEE 2012

Route)

A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow ElectronicToll- Collection Systems Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE