vhdl mem_type dual port

------------------------------------------------------------------------------------------------------------------------------------------------------------------ Titre : ram synthtisable -- Projet : -------------------------------------------------------------------------------- Fichier : ram_simple.vhd -------------------------------------------------------------------------------- Description : RAM avec une seule adresse mais deux horloges -- description conforme a la doc leo_tech.pdf page 292 -- surface occupee : 16 function generators ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY ram_simple IS PORT ( SIGNAL data : IN std_logic_vector(7 DOWNTO 0); SIGNAL address : IN std_logic_vector(4 DOWNTO 0); SIGNAL we, inclock, outclock : IN std_logic; SIGNAL q : OUT std_logic_vector(7 DOWNTO 0)); END ram_simple; ARCHITECTURE fe2 OF ram_simple IS TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0); SIGNAL mem : mem_type; SIGNAL address_int : unsigned(4 DOWNTO 0); BEGIN -- ex2 l0 : PROCESS (inclock,outclock, we, address) BEGIN -- PROCESS IF (inclock = '1' AND inclock'event) THEN address_int <= unsigned(address); IF we = '1' THEN mem(To_integer(unsigned(address))) <= data; END IF; END IF; IF (outclock = '1' AND outclock'event) THEN q <= mem(to_integer(address_int)); END IF; END PROCESS; END fe2;

-------------Pseudo Dual Port VHDL Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity daul_port_ram is generic (data_width : natural := 8; addr_width : natural := 16); port ( clk_in : in std_logic; clk_out : in std_logic; we : in std_logic; addr_in : in std_logic_vector( addr_width - 1 downto 0); addr_out : in std_logic_vector( addr_width - 1 downto 0); data_in : in std_logic_vector( data_width - 1 downto 0); data_out : out std_logic_vector( data_width - 1 downto 0) ); end daul_port_ram; architecture daul_port_ram_arch of daul_port_ram is type mem_type is array (2** addr_width downto 0) of std_logic_vector( data_width - 1 downto 0) ; signal mem : mem_type ; begin mem_write : process (clk_in) begin if clk_in'event and clk_in = '1' then if (we = '1') then mem( conv_integer( addr_in)) <= data_in ; end if ; end if ; end process write ; mem_read : process (clk_out) begin if clk_out'event and clk_out = '1' then data_out <= mem( conv_integer( addr_out)) ; end if ; end process read; end daul_port_ram_arch;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_example is port (Clk : in std_logic; address : in integer; we : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM --with each element being 8 bit wide. type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => '0')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(we='1') then ram(address) <= data_i; end if; data_o <= ram(address); end if; END PROCESS; end Behavioral;

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Simple generic RAM Model +-----------------------------+ | Copyright 2008 DOULOS | | designer : JK | +-----------------------------+

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; entity sync_ram is port ( clock : in std_logic; we : in std_logic; address : in std_logic_vector; datain : in std_logic_vector; dataout : out std_logic_vector ); end entity sync_ram; architecture RTL of sync_ram is type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range); signal ram : ram_type; signal read_address : std_logic_vector(address'range); begin RamProc: process(clock) is begin if rising_edge(clock) then if we = '1' then ram(to_integer(unsigned(address))) <= datain; end if; read_address <= address; end if; end process RamProc; dataout <= ram(to_integer(unsigned(read_address))); end architecture RTL;

TEST BENCH -- test bench solution to ex09 library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_std.all; entity Ram_TB is end entity Ram_TB; architecture Bench of Ram_TB is signal Address :Std_logic_vector(9 downto 0); signal DataIn, DataOut :Std_logic_vector(7 downto 0);

signal WE : Std_logic; signal clock : Std_logic; signal StopClock : boolean := FALSE; begin UUT: entity work.sync_ram(RTL) port map ( clock => clock, we => WE, address => Address, datain => DataIn, DataOut => DataOut ); ClockGen: process is begin while not StopClock loop clock <= '0'; wait for 5 ns; clock <= '1'; wait for 5 ns; end loop; wait; end process ClockGen; Stim: process is begin wait until rising_edge(clock); -- cycle 1 datain <= "00000000"; address <= "0000000001"; we <= '0'; wait until rising_edge(clock); -- cycle 2 we <= '1'; datain <= "00000100"; wait until rising_edge(clock); -- cycle 3 datain <= "00000111"; address <= "0000000010"; wait until rising_edge(clock); -- cycle 4 we <= '0'; wait until rising_edge(clock); -- cycle 5 address <= "0000000001"; wait until rising_edge(clock); -- cycle 6 address <= "0000000010"; wait until rising_edge(clock); -- cycle 7 wait until rising_edge(clock); -- cycle 8 StopClock <= true; wait; end process; end architecture Bench;

architecture Bench2 of Ram_TB is signal signal signal signal signal Address :Std_logic_vector(9 downto 0); DataIn, DataOut :Std_logic_vector(7 downto 0); WE : Std_logic; clock : Std_logic; StopClock : boolean := FALSE;

signal ok: boolean := true; begin UUT: entity work.sync_ram(RTL) port map ( clock => clock, we => WE, address => Address, datain => DataIn, DataOut => DataOut ); ClockGen: process is begin while not StopClock loop clock <= '0'; wait for 5 ns; clock <= '1'; wait for 5 ns; end loop; wait; end process ClockGen; Stim: process is begin -- Initialise input signals address <= "0000000000"; datain <= "00000000"; we <= '0'; wait until rising_edge(clock); -- write to all addresses while address /= "1111111111" loop we <= '1'; wait until rising_edge(clock); address <= std_logic_vector(unsigned(address) + 1); datain <= std_logic_vector(unsigned(datain) + 1); end loop; -- stop writing address <= "0000000000"; datain <= "00000000"; we <= '0'; wait until rising_edge(clock); -- read from all addresses while address /= "1111111111" loop address <= std_logic_vector(unsigned(address) + 1); wait until rising_edge(clock); -- ok should permanently go false on the first error

ok <= ok and dataout = std_logic_vector(unsigned(address(7 downto 0)) - 1); end loop; StopClock <= true; wait; end process; end architecture Bench2;