Advanced Asic Chip Synthesis

ADVANCED ASIC CHIP
SYNTHESIS
ASIC design flow

Synopsys Design Compiler
Synopsys technology library
Logic synthesis
Synthesis layoutLTL
Post_layout optimization
SDF
HDL
(GTECH) HDL
target cell librarycell
ASIC design flow

IP and Library
Models
Verified RTL
Design
Constraints
Logic Synthesis optimization&scan insertion

Static Timing Analysis
no
Time ok?
Post global route

no
Floorplan placement,
CT Insertion&Global routing
Time ok?
Transfer clock tree to DC
Detail routing
Formal verification
Post-layout Optimization
(in-place optimization(IPO))
Time ok?
Tape out
no
ASIC design flow
tap
Tap_controller.v
Tap_bypass.v
Tap_instruction.v
Tap_state.v
Pre_layout
Synthesis
STA using PrimeTime
SDF generation
Verification
Floorolanning and Routing

Post_layout
layout tool STA using PrimeTime
Post-layout Optimization
Fix Hold-Time Violation
ASIC design flow
Initial Setup :
DC .synopsys_dc.setup
company =zte corporation;
designer =name;
technology=0.25 micron
search_path=search_path+{. /usr/golden/library/std_cells\
/usr/golden /library/pads}
target_library ={std_cells_lib.db}
link_library ={*,std_cells_lib.db,pad_lib.db}
symbol_library ={std_cells.sdb,pad_lib.sdb}
ASIC design flow
Synthesis:
Constrain scripts
/* Create real clock if clock port is found */
if (find(port, clk) == {"clk"}) {
clk_name = clk
create_clock -period clk_period clk
}
/* Create virtual clock if clock port is not found */
if (find(port, clk) == {}) {
clk_name = vclk
create_clock -period clk_period -name vclk
ASIC design flow
Constrain scripts
/* Apply default drive strengths and typical loads for I/O ports */
set_load 1.5 all_outputs()
set_driving_cell -cell IV all_inputs()
/* If real clock, set infinite drive strength */
if (find(port, clk) == {"clk"}) {
set_drive 0 clk
}
/* Apply default timing constraints for modules */
set_input_delay 1.2 all_inputs() -clock clk_name
set_output_delay 1.5 all_outputs() -clock clk_name
set_clock_skew -minus_uncertainty 0.45 clk_name
/* Set operating conditions */
set_operating_conditions WCCOM
/* Turn on Auto Wireload selection Library must support this feature */
auto_wire_load_selection = true
ASIC design flow
Compile and scan insertscripts,bottom_up

set_fix_multiple_port_net buffer_constants all
compile scan
check_test
create_test_pattern sample 10
preview_scan
insert_scan
check_test
dont_touch
remove_attribute find(-hierarchy
design,*)dont_touch
Write netlist
remove_unconnected_ports find(-hierarchy cell,*)
change_names hierarchy rules BORG
set_dont_touch current_design
write herarchy output active_design+.db
write format verilog hierarchy output active_design+.sv
ASIC design flow
Pre_layout STA DCblockSTA,PrimeTime

full_chipSTA
Setup_time
Hold_time
DC
cell
ASIC design flow
SDF generation,pre_layoutSDFpre_layout timing,

SDFlayout toolscript
active_design=tap_controller
read active_design
current_design active_design
link
Create_clock period 33 waveform {0 16.5} tck
Set_dont_touch_network {tck trst}
set_clock_skew delay 2.0 minus_uncertainty 3.0 tck
set_driving_cell cell BUFF1X pin Z all_inputs()
set_drive 0 {tck trst}
set_input_delay 20.0 clock tck max all_inputs()
set_output_delay 10.0 clock tck max all_outputs()
write_timing format sdf-v2.1 \
-output active_design+.sdf
write_constraints format sdf cover_design\
-output constraints.sdf
ASIC design flow
Verification
SDF:verilog test_bench
:
RTLgate_level
Floorolanning and global Routing

Estimated RC delay
custom wire_load
incremental synthesispost_layout,reoptimize_design
in_placescript
Detail routing
realRC delay
hold_timepost_layout
post_layoutSDF,gate_level
ASIC design flow
ECO
Engineering change order,ASIC,ASIC

ECO,,tape-out(sign-off)
bugECOchip
10%
DCECO compiler,
layoutECO
DC
Synopsys Design Compiler,UNIX

FPGALTL(links-to-layout)
DC
scriptDCDC
DC
DC
DCHDL
Translate_off/translate_on:DCverilog
full_case:caselatch
Script
Script
Script
DC(.synopsys_dc.setup)

read,compile)

Conditional:
if (expr) {
[dc_shell commands]
} else {
[dc_shell commands]
}
Looping:
foreach(variable, list ){
[dc_shell commands]
}
while( expr) {
[ dc_shell commands]
Script :DCsyntax and context checkersScript
DC
DC8
Design:
Cellinstance
Reference:cellinstance
Port:design
Pin:designcell
Net:portspinspins
Clock:pinport
Library:celltarget_library,link_library
DC
DC
find <type> <name list> -hierarchy

type:DC
name list:
-hierarchy
List,list:mylist={el1 el2 el3}
DC
,DC
DC,dc_shell_status;
DC
dc_shell>vhdlout_use_package={library IEEE.std_logic_1164;\
library STD_LIB;}

flop
dc_shell>designer=myname;
UNIX dc_shell>designer=get_unix_variable(USER)
dc_shell>List target_library
target_library=cbacore.db
dc_shell>List variable all
dc_shell> remove_ variable designer,
DC
DCnets,cells,clocks
DC,
set_attribute <object list>
<attribute name>
< attribute value>
dc_shell>get_attribute STD_LIB
get_attribute <object list>

<attribute name>
default_max_transition
DC
DC
*.dbDC
Verilog
VHDL
EDIF:electronic design interchange format,
DC
Script files <filename>.scr

RTL verilog file <filename>.v
RTL VHDL file <filename>.vhd
Synthesized VHDL netlist <filename>.svhd
EDIF file <filename>.edf
Synthesized verilog netlist <filename>.sv
Synopsys database file <filename>.db
report <filename>. rpt
Log files <filename>.log

technology librarycell
target librariescell
link librariescellDClink libraries

cell

(.libLC.db
Library Group;
Library level attributes;
Environment description;
Cell description;
Library Group
library(ex25)/* Library Group
{/*start of library*/
<attributes description>
<environment description>
<cell description>
}/*end of library*/
Library Group Library
Library level attributes:

CMOS/TTL)
library (ex25){
technology(cmos);
delay_model
date
revision
current_unit
time_unit
voltage_unit
pulling_resistance_unit
capacitive_load_unit(1.0 pf);
default_inout_pin_cap
default_input_pin_cap
default_output_pin_cap
default_max_fanout
default_max_transition
default_operating_condition
in_place_swap_mode
}
:table_lookup;
:feb 29,2000;
:1.0;
:1A;
:1ns;
:1V;
:1kohm;
:1.5;
:1.0;
:0.0;
:10.0;
:10.0;
:NOMINAL;
:match_footprint;
Environment description:
scaling factors)
timing rang models)
operation condition)
wire-load models)
scaling factors K-factors

PVT
K_process_fall_transition
K_process_rise_transition
K_temp_fall_transition
K_temp_rise_transition
K_volt_fall_transition
K_volt_rise_transition
:1.0;
:1.2;
:0.03;
:0.04;
:0.02;
:0.5;
timing rang models)

Timing_range(BEST){
faster_factor :0.5;
slower_factor :1.3;
}
operation condition)PVTRC
DCcellnetdelay;
tree_type:worst_case_tree,
balance_tree, best_case_tree,Dcdriver
pindriven cellinput pinwire_load
wire-load models)pre_layoutnet
Synopsys wire-load models
net fanout net length
Cell descriptioncellpin
cell(BUFFD0){
area:5.0;
pin(Z){
max_capacitive:2.2;
max_fanout:4;
function:I;
direction:output;
timing(){
}
related_pin: I;
}
pin(I){
direction:input;
capacitive:0.04;
fanout_load:2.0;
max_transition:1.5;
}
}
CellpinDRC
Input pinfanout_load
Output pinmax_fanout
Input or output pin max_transition
Input or output pinmax_capacitance
DRCcell
Cell DRC
dc_shell> set_attribute find(pin,ex25/BUFFD0/Z) max_fanout 2.0
cellclock input pinclocktrueinput pin
Good library
cell
Bufferinverters
Cellrisefalldelay
cell:OR,NOR;
cells,:AND,NAND;
inverterscellsAIO,OAI
cells
flip_flop;
flip_flop
set,resetFlop
latch;
delay cell;

Synopsys
CMOS
CMOS
CMOS
non-linear delay model)cell
NLDM,,cellinput transition output loading
celldelayoutput transition ,cellcell delay,
output transition input transition output loading
cell,
Cellinput transitionoutput loadinginput transitiondriving
celloutput transitiondriving celltiming arc,driven cell
,
reset
2ns
Z
Z
U2
0.3ns
U1
Affected gate
U1output transitionU2input transition

set_disable_timing U1 from A to Z,DCA to Ztiming arc.
Partitioning for synthesis
scripts
RTL
HDL
DC
DCgroup,ungroup
Group:; Ungroup
groupungroup
dc_shell>current_design top
Group {U1 U2} design_name sub1

U0
U0
U1
top
U2
Ungroup -all
top
U1
sub1
U2

10K
I/Opads,DFT,clock,core logic;
block
Layout
cell
RTLHDLHDL
HDL
HDLDC
RTL
DC,
HDLhard_coded
Clock
Clockreset
Clock
muxset_disable_timing
top level
I/O pad
DC
verilog,Stateparameters ;
setup
setup
setup
setup
setup
setup
setup.synopsys_dc.setup,
setup
Project working directorysetup

DCsetupsetup
setup
startupProject working directory
Synopsys installation directorySynopsys
Users home directorsetup
Startup
Search_path:
Target_library:cells, DC
Target libraryLink library
DC
Link_ library:cells,DCRAM,ROMPad
RTLcells
Symbol_library:cellsDA
Target_libraryLink _library
Target libraryLink_library
Target_libraryTarget librarytranslate
startup
.synopsys_dc.setup
company =zte corporation;
designer =name;
technology=0.25 micron
search_path=search_path+{. /usr/golden/library/std_cells\
/usr/golden /library/pads}
target_library ={std_cells_lib.db}
link_library ={*,std_cells_lib.db,pad_lib.db}
symbol_library ={std_cells.sdb,pad_lib.sdb}
DC
DCScript
RTL design entry
Environment constraints
Design and clock constraints
Compile design into mapped gates
Optimizing design
analyze the synthesis results and debug potential problems.
Save design netlist
Report constraints
(Optional) Apply critical path constraints
(Optional) Second compile to improve critical paths
(Optional) Second path compile constraint report
RTL design Entry
DCHDL,
readanalyze&elaborateanalyze&elaborate
analyze&elaborateGTECH
HDL GTECHsoft macros such as adders, comparators
synopsys synthetic lib Analyze
.synworkelaborate
analyzedelaborateRead
analyze&elaborate
verilog VHDL
read
verilog VHDLEDIF
db
verilog VHDLRTL
-library
.syn
Generics(vhdl)
Architecture(vhdl)
I/Owire-load
DC set_max_capacitance
set_max_transition
&set_max_fanout on
input &output ports or
current_design;
set_operating_conditions
on the whole design
Top level
clk
set_drive
on Clock
set_driving_cell
on input signals
Clock
Divider
Logic
Block B
Block A
set_load on inputs
set_wire_load
for each block,
including top level
set_load on output
Set_operating_conditions <name of operating conditions>

process,voltage,temperature, cellwire delay
Set_operating_conditions WORSTTYPICALBEST)
set_operating_conditions min BEST max WORST DCWORST
BEST
Set_wire_load <wire-load model> -mode <top|enclosed|segmented>

DCwire_loadwire-load
netsdelay
wire_loadnet loadingwire-load mode
top,enclosed,segmented,net wire_load
Top:wire_loadtop-levelflattenlayout
Enclosednetwire_loadenclosed layout
logical and physical hierarchy
Segmentednetwire_loadenclosednet,
Segmented wire_load,
wire_load
pre-layout
dc_shell>set_wire_load MEDIUM mode top
Set_load<value><object list> netsports
Set_drive <value><object list>:input port,0

clock portset_drive 0 {CLK RST} set_driving_cell
-cell<cell name> -pin<pin name> <object list>:input portcell
transition time
Set_min_library <max library filename>

-min_version<min library filename>
worst-casebest-case libraries,
DChold-timesetup-time
hold-time
DRCset_max_transition <value> <object list>
set_max_capacitance <value> <object list>
set_max_fanout <value> <object list>
input portsoutput portscurrent_design,
.;
set_max_transition 0.3 current_design
set_max_capacitance 1.5 find(port,out1)
set_max_fanout 3.0 all_outputs()
design and clock constraints
DC
Top level
clk
Create_clock&
set_clock_skew
set_input_delay
on input signals
Clock
Divider
Logic
Block B
Block A
set_max_area
for each block,
set_output_delay
on output
set_max_area
timing path(Create_clock, Set_input_delay, Set_output_delay)
clock source buffer

clock_skewVDSM
layoutcell
DC
DC
Create_clock:duty
create_clock period 40 waveform{0 20} CLK40ns 0 ns,20
ns;
create_clock -name vTEMP_CLK -period 20

Set_clock_transition:pre_layouttransition(
fanout.DC
Set_clock_skewskewdelaypre_layout post_layout
-propagatedDCskew
Set_clock_skew uncertainty 0.5 CLK
Pre-layoutDC :
DC:
create_clock period 40 waveform {0 20} CLK
Set_clock_skew delay 2.5 uncertainty 0.5 CLK
Set_clock_transition 0.2 CLK
set_dont_touch_network CLK
set_drive 0 CLK
layoutskew
set_clock_skew delay 2.5 minus_uncertainty 2.0 plus_uncertainty 0.2 CLK
minus_uncertaintysetup-time plus_uncertainty hole-time.
celldelayinput signaloutput pin
clock networkfanout clock network clock
transition timeDC
post-layoutDC:
clock transition
timelayout DC
DC,scriptlayout
layout pre_layout.
DCclock
set_clock_skew propagated minus_uncertainty 2.0 plus_uncertainty 0.2 CLK
set_dont_touch_network CLK
set_drive 0 CLK
clock uncertaintyprocess
,SDFSDF
SDF
DC:
DC
DCCLKclkB CLKBlock B
CLKclkA,CLKclk_div clkAclkA
clk _divoutput port
Clk_div
clkA
CLK
clkB
Block
A
Block
dc_shell>create_clock period 40 waveform {0 20} CLK

dc_shell>create_clock period 80 waveform {0 40} find(port,clk_div/clkA)
DC:
Set_input_delay:
set_input_delay max 23.0 clock CLK { dataout }

set_input_delay min 0.0 clock CLK { dataout }
DC:
Set_output_delay:cell
set_output_delay max 19.0 clock CLK {dataout}

over-constrain, setup-time.
-0.5layout in-place optimizationhold_timetiming
margin.
DC:
Set_dont_touch_network,portnetDCnetnet
dont_touchCLKRST
Set_dont_touch_network{CLK,RST}
output portset_dont_touch_network.
set_dont_touch_network
DC DRCRESET
Set_dont_touchcurrent_design,cell,net,references.DC
Set_dont_touch find(cell,sub1)
Set_dont_use:.setupcellDC
Set_dont_use {mylib/SD*},SDflip-flops.
Advanced constraints
Path:startpoint endpoint
statrpoint:input ports cellclock pins;

endpoint: output portscelldata pins;
Path_delay
Set_false_path
DCfalse
pathfalse pathDC
false path
1,clock false path
set_false_path -from [get_clock CLKA] -to [get_clock CLKB]
2,logicfalse path
dc_shell>set_false_path through mux1/A through mux2/A

dc_shell> set_false_path through mux1/B through mux2/B
3,tristates path,DCtristates false path
3,tristates false path

set_false_path -through [get_pins U1/DATA_BUS_OUT[1]] \
-through [get_pins U1/DATA_BUS_IN[1]]
Set_multicycle_path:DC
DC
dc_shell> set_multicycle_path 2 -from FFA/CP \

-through Multiply/Out -to FFB/D
Group_path:
dc_shell>group_path to {out1 out2} name grp1
Set_max_delay
set_max_delay 5 from all_inputs() to all_outputs
set_max_delay 0 -from CK2 -to all_register(clock_pin)
gated clocks or resets

Set_min_delay
Set_min_delay 3 from all_inputs()
set_fix_holdDC
Compilation Strategies
GETCH gate cell
cpmpile
Multiple InstancesDC
unquify
dont_touch
Synopsys
Top-down hierarchical compile
Time-budget compile
Compile-characterize-write-script-recompile(CCWSR)
Resolving Multiple Instances

Multiple Instances:
moduleB
moduleA
U1
U2
time-budgeting,moduleA moduleB DC
moduleA dont_touch
unquify U1,U2moduleA_U1moduleA_U2 DC
dc_shell>unquify
unquify dont_touch DCU1
U2
Top-down hierarchical compile

top level100K
gate
top_level
analyze -format vhdl {alu.vhd... risc_core.vhd }

elaborate RISC_CORE
include scripts/top_level. scr
compile
Time-budget compile:Bottom-Up
Scripts
scripts;
Top
incrementallyDRCs;
Time-budget compile
analyze {source/PRGRM_CNT.vhd ... Source/PRGRM_CNT_TOP.vhd}

elaborate PRGRM_CNT_TOP
# Default Constraints
source Bottom_up_budget.scr;
compile
report_constraint -all > reports/PRGRM_CNT_TOP.rpt
# MAKE SURE timing has been met! (If not, recode or recompile)
write -format db -hier -output mapped/PRGRM_CNT_TOP.db
analyze {ALU.vhd}
elaborate ALU
# Default Constraints
. . .
# MAKE SURE timing has been met! (If not, recode or recompile)
write -format db -hier -output mapped/PRGRM_CNT_TOP.db
top level
read_vhdl source/RISC_CORE.vhd
# Bring in compiled .db files
link
# SYSTEM-LEVEL Constraints
source Top_level.scr;
# Check for timing violations:
report_constraint -all > reports/RISC_CORE.rpt
write -format db -hier -output mapped/RISC_CORE.db
Compile-characterize-write-script-recompile(CCWSR):
top leveltop levelcharacterize top

levelwrite_script
re-compile
DC
scripts
scripts
Optimizing design
Design space exploration

Design space exploration
HDL
DC
delay
design rule Fixing
design rule Fixing
Area
(delay prioritized)
(DRC prioritized)
DCDC
vertical logic,
horizontal logic,
vertical logic
horizontal logic
DC10%
Optimizing design
worst Negative slack
Optimizing design
Total Negative Slack

DCWNSgrouping path
TNSWNSTNS-8nsWNS-5ns
-2 ns
in1
-5 ns
out
in2
CLK
-3 ns
TNSlayout
TNS
DCpositive slack
Optimization design
Optimization Step
Logic optimizationflattenstructure Gate optimization
Unoptimized design
Flatten
Structure
Logic optimization
Gate optimization
Optimized design
flattenstructure
Attribute
value
flatten
false
structure
true
structure(timing)
true
structure(boolean)
false
Optimization Techniques
Flattening
FlatteningFlattening
vertical flattened effortflattened
structured-map_effort high,
DCstructured
flattened,structured(,structuredset_flatten
-phasetrue,structured flattenedDC
flattened
set_flatten <true|false>
-design <list of design>
-effort <low|medium|high>
-phase<true|false>
Structuring
before structuring
after structuring
P=ax+ay+c
P=aI+c
Q=x+y+z
Q=I+z
I=x+y
Structuring timing(Boolean Boolean
compile_new_boolean_structure= true,DCboolean
set_structure <true|false>
-design <list of design>
-boolean < true|false >
-timing<true|false>
set_max_area 0Boolean , structuretime
Optimizing clock Networks

buffer
0.5umVDSM
cell
buffers
,
pinset_dont_touch_network,DCbuffer up
set_dont_touch_network
dont_touch
DC size upDRCset_dont_touch_network
incremental compilation
report_netnet,balance_buffer
buffer balance_buffer
in-place-optimizationcompile-in_place
compile_ok_to_buffer_during_inplace _optfalse,DC
buffersize up
Removing hierarchy
DCDC
Optimizing for Area

DC
dont_use
Incrementally compile:
incrementally incrementallyDC
Design For Test
DCTC(Test Compiler)DFT
DCDFT
BIST
DFT
Design For Test
BIST
DC BIST BIST BIST
RAMBIST
pass/failBIST
BISTVerilog VHDL
RTL
DataIn
L
F
S
R
BIST
RAM
Address
L
F
S
R
BIST
Read/write control
M
I
S
T
DataOut
BIST
Design For Test
JTAGIEEE1149.1JTAGDC
TDITDO:TMS:TAPTCK:TAP
Design For Test
flopbuilt-inscan flop
scan_flopflopflop
scan_flop
Design For Test
DCflop
scan-flop,
scan-flopfloptest_ready
set_scan_configuration
set_scan_configuration -style
multiplexed_flip_flop
compile -scanDCscan_flop
preview -scanset_scan_configuration
check -test
DCRTL
Design For Test
ATPG
create_test_patterns -sample<n>
best case
input portsoutput
ports
insert_scan
report_test
Design For Test
DFT
tri-state
mux tri-state mux
tri-state
Latches
Latches,latch
Design For Test
Gated or Generated Clocks

DFTflopclk Gated or Generated Clocksmux
,
DCcell:
dc_shell>set_scan_element false<list of cells or design>
CLK
Test_mode
Secondary
clock
Design For Test
single Edge
single Edgerising falling
Edge
mux,
process(clk,test_mode)
begin
if(test_mode=1)then
muxed_clk_output<=clk;
else
muxed_clk_output<=not(clk);
endif
endprocess
Design For Test
(RAM
RAMunknown
Data Known
Logic
During
Scan-mode
testable
Scan_mode
D
Scan_mode
Combination logic
Combination logic
Design For Test
clock skewflop
hold-timehold-time
flop
flop
Gated Reset Preset

FlopresetPresetflopresetPresetgated,mux
LINKS TO LAYOUT AND

POST LAYOUT OPTIMIZATION
Links to layout LTLDClayoutDC

layoutpost-layout
layout
post-layout
Layout
Layout
Post-Layout Optimization
Layout
Layout
layoutVerilogEDIF, EDIFECO
EDIFEDIF
Veriloglayoutlayout
Uniquify
net
ports
cellpin
assign tran
gating clock reset
Layout
Uniquify
layoutDCuniquified.uniquified
layoutflat
flop
clock_netNon_ uniquified layout
DC
netport Uniquify
dc_shell>remove_attribute find(-hierarchy design,*)dont_touch
dc_shell>Uniquify
moduleB
U1
moduleA_U1
U2
moduleA_U2
Layout
layoutnet*cell*,*-return
layoutnet,portDClayout
.synopsys_dc.setup,
define_name_rules BORG allowed A-Za-z0-9 \
-first_restricted _ last_restricted_
\
-max_length 30
-map {{\*cell\*,mycell},{-*return,myreturn}}
DC
change_names hierarchy rules BORGS
setup DCbus
bus_naming_style=%s[%d]
ports
DCportsportsDC
ports
remove_unconnected_ports find(-hierarchy cell,*)
check_design
Layout
assign tran
tri wires ,tran assigninout

port,DCtri wire tran setup
verilogout_no_tri=true,DC tri_state netwire
input portoutput portfeedthrough) output
portground1b0,0b0)DCassign
,input portoutput portbuffer:
set_fix_mulitple_port_nets feedthroughs
set_fix_multiple_port_nets all buffer_constants
dont_touchnet
netdont_touch
remove__attribute fin(net,<net name>) dont_touch
Layout
cellpin
DCports,
DFF dff_reg (.D(data),.CLK(m_clock),.Q(data_out));
QN portDCQN port,cell4
port,layoutcellportsetup
verilogout_show_unconnected_pins=truelayout
gating clock reset

clock reset set_dont_touch_networkclockreset
buffer,clockreset
report_transitive_fanout clock_tree
report_transitive_fanout from reset
clock_treeclock-from -fromclock_tree
DC
Layout
Layout
Floorplanning
clock tree insertion
routing the database
Layout
Floorplanning
floorplanning cellmacros(RAMs,ROMs,sub-blocks)
netRC
sub-blocks
sub-blocksmacros,cell
macrosfloorplanning
timing_driven layout(TDL))
floorplan
Layout
timing_driven layout(TDL))
layout DCcellmacros
,DCSDF
write_constraints format <sdf|sdf-v2.1> //1.0 2.1

-cover_design//DCthe worst pathdrive-load pin
-from <from list
-to <to list>
-through <through list>
-output <output file name
SDF(V2.1)
(DELAYFILE)
(SDFVERSIONOVI2.1)
(CELL
(CELLTYPEHello)
(INSTANCE)
(TMINGCHECK
(PATHCONSTRAINT INPUT1 U751/A3 U751/ZN U754/I1
U754/ZN REG0/D(1.523:1.523:1.523))/*path_delay (min,typ,max)
.
Layout
Floorplan
DCFloorplan
PDEFphysical design exchange format)set_loadnet
SDFnetcell delaywire_load
DC
PDEFcell
DCLayoutPDEF
read_cluster design <design name> <pdef filename>
DCLayout
write_cluster design <design name> <pdef filename>
SDFnetpin_to_pintiming arcscell delay

Set_loadnetDCnetcell delayDRC.
set auto_link_disable true
set_load 0.034 [get_nets N3243]
set_load 0.038 [get_nets N3244]
.
set auto_link_disable false
Layout
TDL
netlayout

DCPDEFpost-layout
Layout
Clock tree insertion

clock latency and skew.
latency
buffer
clock skew,buffer
rise fall bufferbuffer
bufferrise timefall time positive flop
latencyinverters,bufferinverters
invertersbuffer.
pad source bufferwire
gate inverters;
Layout
Transfer of clock tree to DC

layout tool DC
DC.
layout tool Verilog EDIF

layout tool
formal
SDFendpointflopclock pin
DCSDF
synopsys liblayout tool liby
clock treecellnet, layout database
layout tooldisconnect_net,create_cellDC scripts

DC
layout toolscriptPerl Awk

verilog
Layout
globalnet
detailednet
EXTRACTION
:
wire-loadwire-load
wire-load
layout
layout tool
DSPFSPEFDSPFRC
net
RSPFSPEFpinetRC
net
SDFnetcelllayout toolDC
cellPTcase
SDFnet RC+lumpedDCRCnet
post-layout lumped synopsys set_load
lumpednet driving cell , netdriven cellnet
wire capacitance
EXTRACTION
Floorplanning,placement and
Clock tree insertion
Global routing
Extract estimated delays
no
Time ok?
no
detailed routing
Extract real delays
Time ok?
no
Minor timing violations
Major timing violations
Synthesis and optimization

layout toolDC
custom wire_loadin_place
Optimization
layout tool
SDFNet RC
Set_load net
PDEF

layoutDC,DCpost-layout optimization, Layout tool

the worst case the best case
Synopsys lib
layout DC
current_design
<design name>
include quiet
<set_load file name>
read_timing f sdf <RC file name in SDF format>
read_cluster
<cluster file name in PDEF>
SDF
load
custom wire-load
Layout tool custom wire-load
NetSDFcustom wire-load
PDEFcustom wire-load
DC
create_wire_load -design <design name>
-cluster <cluster name>//layout
-trim <trim value> //
-percentile <percentile value> //wire-load
-output <output file name>
CWLM(custom wire-load model)layoutwire-load model
update_lib <library name> <CWLM file name>
DCCWLMDC.
In-place optimization
IPOlayoutIPO
/SETUP_TIMEHOLD_TIME
IPO
cell
cellbuffers)
synopsys IPO
in_place_swap_mode:match_footprintcell_footprintcell
layout
setupIPOcell
compile_ignore_footprint_during_inplace_opt =true|false;
compile_ok_to_buffer_during_inplace_opt =true|false;
compile_ignore_area_during_inplace_opt =true|false;
compile_disable_area_opt_during_inplace_opt =true|false;
IPO
compile in_place//libwire_load
reoptimize _design in_place//,custom wire_load
Location based Optimization
cell
cellPDEFlayout tool
Location based Optimization
LBOIPOPDEF reoptimize _design

in_placeIPOLBO
reoptimize _design in_placeLBO,IPO
lbo_buffer_removal_enable =true
lbo_buffer_insertion_enable =true
IPOLBO
reoptimize_design_change_list_file_name=<file name>
Fix Hold-time Violation

hold-time violation
Synopsys
delays
DC
Synopsys
two-pass
Single pass DC
Set_fix_hold
DCCLKbuffercell
hold-timelayoutreoptimize _designholdtime,layoutcompile incrementalhold-time
reoptimize _design
min_max
layout toolminmax
set_fix_hold <clock name>hold-time
two-pass
worst-case lidsetup-time,layoutbest-case lib
hold-time
Single pass
set_min_library <worst case library name>
-min_version <best case library name>
set_operating_conditions min BEST max WORST
include net_delay.set_load
reading_timing interconnect.sdf
reading_cluster floorplan.pdef
set_input_delay max 20.0 clock CLK {IN1 IN2}
set_input_delay min -1.0 clock CLK {IN1 IN2}
set_output_delay max 10 clock CLK {IN1 IN2}
set_fix_hold CLK
reoptimize_design in_place
delay
10-20hold-time delay
buffer,bufferbuffercell
hold-timefanin
fanin buffer
DC
hold-time IPOscript
perl Awk)setup-time slackholdtime
disconnect_net,create_cell,connectDCDC
buffer.
SDF
SDF
SDF
pre_layout
post_layout
post_layoutSDFDCRClumpedPT SDF
DC:
write_timing format sdf-v2.1 output<file name>
SDFgate-level
SDF
IOPATH delaycell delay,wire loading transition

INTERCONNECT delaydriving celloutput pindriven cellinput pin RC
delay
SETUP timing checkcellsetup-time
HOLD timing checkcellhold-time
SDF
pre_layoutSDF
pre_layoutwire-load,
DC
set_clock_skew delay 2.0 CLK
set_clock_transition 0.2 CLK
DCSDF DC
clock delayDCinput pad (CLKPAD)
set_annotated_delay 2.0 cell \
-from CLKPAD/A to CLKPAD/Z
clock_transitiondriven cell
delay,SDF
SDF
post_layoutSDF
,layout
read_timing format sdf<interconnect RCs in SDF format>
include quiet <parasitic capacitances in set_load format>
set_clock_skew propagated CLK
SDF
setup_timehold_timeXs
SDF
setup_timehold_time DC
setup_timehold_time zero
set_annotated_check 0 setup hold \
-from REG1/CLK \
-to REG 1/D
SDF
SDF
reset
2ns
U1
signal_a
Z
U2
0.3ns
Affected Gate
Cell delayinput transition input transition

driving celltransition delaydriving celltime arc
driven cell delay
SDFSDFDC
set_disable_timing U1 from A to Z

Advanced Asic Chip Synthesis

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Advanced Asic Chip Synthesis

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ADVANCED ASIC CHIP

ASIC design flow

target cell librarycell

ASIC design flow

Logic Synthesis optimization&scan insertion

Post global route

Transfer clock tree to DC

ASIC design flow

STA using PrimeTime

Floorolanning and Routing

layout tool STA using PrimeTime

Fix Hold-Time Violation

ASIC design flow

ASIC design flow

ASIC design flow

ASIC design flow

Compile and scan insertscripts,bottom_up

ASIC design flow

Pre_layout STA DCblockSTA,PrimeTime

ASIC design flow

SDF generation,pre_layoutSDFpre_layout timing,

ASIC design flow

Floorolanning and global Routing

ASIC design flow

Engineering change order,ASIC,ASIC

Synopsys Design Compiler,UNIX

Script :DCsyntax and context checkersScript

find <type> <name list> -hierarchy

get_attribute <object list>

Script files <filename>.scr

Synopsys technology library

Synopsys technology library

link librariescellDClink libraries

Synopsys technology library

Library level attributes;

Synopsys technology library

Library Group Library

Synopsys technology library

Library level attributes:

Synopsys technology library

scaling factors K-factors

timing rang models)

Synopsys technology library

Synopsys technology library

Synopsys technology library

Synopsys technology library

Synopsys technology library

cellclock input pinclocktrueinput pin

Synopsys technology library

Synopsys technology library

U1output transitionU2input transition

Partitioning for synthesis

Partitioning for synthesis

Group {U1 U2} design_name sub1

Partitioning for synthesis

Partitioning for synthesis

Partitioning for synthesis

Project working directorysetup

Synopsys installation directorySynopsys

Users home directorsetup

RTL design entry

Design and clock constraints

Compile design into mapped gates

analyze the synthesis results and debug potential problems.