Cmos Logic Data

Master Index
Product Selection Guide
The Better Program
B and UB Series Family Data
CMOS Handling and Design Guidelines
Data Sheets
CMOS Reliability
Equivalent Gate Count
Packaging Information
Including Surface Mounts
DATA CLASSIFICATION
Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of the
first page reads: This document contains information on a product under
development. Motorola reserves the right to change or discontinue this
product without notice.
Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of the
first page reads: This document contains information on a new product.
Specifications and information herein are subject to change without notice.
Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information
on a product in full production. Guaranteed limits will not be changed without
written notice to your local Motorola Semiconductor Sales Office.
ii
MOTOROLA CMOS LOGIC DATA
CMOS LOGIC
DATA
Prepared by
Technical Information Center
This book presents technical data for the broad line of CMOS logic integrated
circuits and demonstrates Motorolas continued commitment to MetalGate
CMOS. Complete specifications are provided in the form of data sheets. In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have
been included to familiarize the user with these circuits.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and
are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment
Opportunity/Affirmative Action Employer.
Printed in U.S.A.
Series C
MOTOROLA INC., 1991
Previous Edition 1990
All Rights Reserved
iii
iv
Master Index
MASTER INDEX
This index includes Motorolas entire MC14000 series CMOS products, although this book contains
data sheets for Logic Devices only. Data sheets for devices in the CMOS/NMOS Special Functions Data
book (DL130) are designated in the page number column as SF.
Products which have been cancelled are designated in the page number column as .
Device
MC14000UB
MC14001B
MC14001UB
MC14002B
MC14002UB
MC14006B
MC14007UB
MC14008B
MC14011B
MC14011UB
MC14012B
MC14012UB
MC14013B
MC14014B
MC14015B
MC14016B
MC14017B
MC14018B
MC14020B
MC14021B
MC14022B
MC14023B
MC14023UB
MC14024B
MC14025B
MC14025UB
MC14027B
MC14028B
MC14029B
MC14032B
MC14034B
MC14035B
MC14038B
MC14040B
MC14042B
MC14043B
MC14044B
MC14046B
CHAPTER 1
12
Function
Page
Dual 3Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual 4Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
18Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual 4Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 681
Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
8Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
4Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6104
Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6108
Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6112
Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6116
Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6116
PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6120
Device
MC14049B
MC14049UB
MC14050B
MC14051B
MC14052B
MC14053B
MC14060B
MC14066B
MC14067B
MC14068B
MC14069UB
MC14070B
MC14071B
MC14072B
MC14073B
MC14075B
MC14076B
MC14077B
MC14078B
MC14081B
MC14082B
MC14093B
MC14094B
MC14097B
MC14099B
MC14106B
MC14160B
MC14161B
MC14162B
MC14163B
MC14174B
MC14175B
MC14194B
MC14415
MC14433
MC14442
MC14443
Function
Page
Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6125
Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6125
8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6133
Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6133
Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6133
14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6140
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6144
16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6150
8Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6158
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6160
Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . 6162
Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6160
8Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6166
8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . 6170
8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6174
Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6180
Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6184
Synchronous Presettable 4Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6184
Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6193
Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6197
4Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6201
Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6205
31/2 Digit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MicroprocessorCompatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
6Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
CHAPTER 1
13
Device
MC14444
MC14447
MC14457
MC14458
MC14460
MC14466
MC144671
MC14468
MC14469
MC14490
MC144951
MC14497
MC14499
MC14500B
MC14501UB
MC14502B
MC14503B
MC14504B
MC14506UB
MC14508B
MC14510B
MC14511B
MC14512B
MC14513B
MC14514B
MC14515B
MC14516B
MC14517B
MC14518B
MC14519B
MC14520B
MC14521B
MC14522B
CHAPTER 1
14
Function
Page
MicroprocessorCompatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
6Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Remote Control Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Automotive Speed Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Interconnectable Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Addressable Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . SF
Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6210
Hexadecimalto7 Segment Latch/Decoder ROM/Driver . . . . . . . . . . . . . . . SF
PCM Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
7Segment LED Display Decoder/Driver with Serial Interface . . . . . . . . . . . SF
Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6217
Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6223
Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6227
Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6231
TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6235
Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6238
Dual 4Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6243
Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6248
BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6256
8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6262
BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6266
4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . 6274
4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . 6274
Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6280
Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6288
Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6292
4Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6297
Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6292
24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6301
Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6307
Device
MC14526B
MC14527B
MC14528B
MC14529B
MC14530B
MC14531B
MC14532B
MC14534B
MC14536B
MC14538B
MC14539B
MC14541B
MC14543B
MC14544B
MC14547B
MC14549B
MC14551B
MC14553B
MC14554B
MC14555B
MC14556B
MC14557B
MC14558B
MC14559B
MC14560B
MC14561B
MC14562B
MC14566B
MC14568B
MC14569B
MC14572UB
MC14573
MC14574
MC14575
MC14580B
MC14581B
MC14582B
Function
Page
Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6307
BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6315
Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6321
Dual 4Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6327
Dual 5Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6333
12Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6338
8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6341
5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6347
Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6354
Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6365
Dual 4Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6373
Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6377
BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6382
HighCurrent BCDto7Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6393
Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6398
Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6405
3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6412
2 X 2Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418
Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6422
Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6422
1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6425
BCDto7 Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6429
NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6434
9s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6445
128Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6451
Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6455
Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . . 6461
Programmable Dual 4Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . 6471
Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6481
Quad Programmable Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Quad Programmable Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Programmable Dual Op Amp/Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . SF
4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6484
4Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6489
LookAhead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6494
CHAPTER 1
15
Device
MC14583B
MC14584B
MC14585B
MC14597B
MC14598B
MC14599B
MC144110
MC144111
MC145000
MC145001
MC145026
MC145027
MC145028
MC145029
MC145040
MC145041
MC145104
MC145106
MC145107
MC145109
MC145112
MC145143
MC145144
MC1451451
MC1451461
MC1451511
MC1451521
MC1451551
MC1451561
MC1451571
MC1451581
MC1451591
MC145453
CHAPTER 1
16
Function
Page
Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6498
4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6507
8Bit BusCompatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6511
8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6511
Hex D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Quad D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
48Segment Multiplexed LCD Driver (Master) . . . . . . . . . . . . . . . . . . . . . . . . . SF
44Segment Multiplexed LCD Driver (Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Remote Control Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
AnalogtoDigital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
AnalogtoDigital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
4Bit Data Bus Input PLL Frequency Synthesizer
(Not Recommended for New Designs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
4Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
4Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
Serial Input PLL Frequency Synthesizer with Analog Phase Detector . . . . . SF
33Segment LCD Driver with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . SF
CMOS Selection Guide by Function

Device
Function
Page
NAND Gates
MC14011B
MC14011UB
MC14093B
MC14023B
MC14023UB
MC14012B
MC14012UB
MC14068B
Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6166
Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual 4Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
8Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
NOR Gates
MC14001B
MC14001UB
MC14025B
MC14025UB
MC14000UB
MC14002B
MC14002UB
MC14078B
Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Dual 3Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Dual 4Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
8Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AND Gates
MC14081B
MC14073B
MC14082B
Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
OR Gates
MC14071B
MC14075B
MC14072B
Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Triple 3Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual 4Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Complex Gates
MC14070B
MC14077B
MC14501UB
MC14506UB
MC14530B
MC14519B
MC14572UB
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual 5Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6160
6160
6223
6238
6333
6297
6481
Inverters/Buffers/Level Translator
MC14007UB
Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
MC14049B
MC14049UB
MC14050B
Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6125
MC14069UB
Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6158
MC14502B
Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6227
MC14503B
Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6231
MC14504B
TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6235
MC14584B
CHAPTER 2
22
Device
Decoders/Encoders
MC14028B
MC14511B
MC14513B
MC14543B
MC14544B
MC14547B
MC14558B
MC14514B
MC14515B
MC14532B
MC14555B
MC14556B
Function
Page
BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 681

BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6256
BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6382
HighCurrent BCDto7Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6393
BCDto7Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6429
4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . . . . 6274
4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . . . . 6274
8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6341
Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6422
Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6422
Multiplexers/Demultiplexers/Bilateral Switches
MC14016B
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
MC14066B
Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6144
MC14551B
Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6405
MC14053B
Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6133
MC14052B
MC14097B
MC14529B
Dual 4Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6327
MC14539B
Dual 4Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6373
MC14067B
16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6150
MC14051B
8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6133
MC14512B
8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6262
MC14519B
4Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6297
Schmitt Triggers
MC14093B
MC14583B
MC14106B
MC14584B
Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FlipFlops/Latches
MC14042B
MC14043B
MC14044B
MC14076B
MC14175B
MC14013B
MC14027B
MC14508B
MC14174B
MC14099B
MC14597B
MC14598B
MC14599B
Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6112

Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6116
Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6116
Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . . . . 6162
Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6197
Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Dual 4Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6243
Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6193
8Bit BusCompatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6511
8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6511
6166
6498
6180
6504
CHAPTER 2
23
Device
Function
Page
Shift Registers
MC14015B
MC14517B
MC14562B
MC14557B
MC14006B
MC14014B
MC14021B
MC14034B
MC14094B
MC14035B
MC14194B
MC14549B
MC14559B
Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6288
128Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6451
1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6425
18Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
8Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . . . . 6170
4Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6104
4Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6201
Counters
MC14017B
MC14018B
MC14020B
MC14022B
MC14024B
MC14029B
MC14040B
MC14060B
MC14160B
MC14161B
MC14162B
MC14163B
MC14510B
MC14516B
MC14518B
MC14520B
MC14522B
MC14526B
MC14534B
MC14553B
MC14566B
MC14569B
Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 686
12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6108
14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6140
Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6248
Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6280
Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6292
Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6292
Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6307
Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6307
5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6347
3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6412
Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6455
Programmable Dual 4Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . 6471
Oscillators/Timers
MC14521B
MC14536B
MC14541B
24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6301

Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6354
Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6377
Multivibrators
MC14528B
MC14538B
Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6321

Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6365
CHAPTER 2
24
Device
Function
Page
Adders/Comparators
MC14008B
MC14032B
MC14038B
MC14560B
MC14561B
MC14582B
MC14585B
4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6434
9s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6445
LookAhead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6494
4Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6507
ALU/Rate Multipliers
MC14527B
MC14554B
MC14581B
BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6315

2 X 2 Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418
4Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6489
Parity Checker
MC14531B
12Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6338
Memory
MC14580B
4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6484
Microprocessor/Industrial Control
MC14500B
Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6217
Other Complex Functions
MC14046B
PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC14415
Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC14490
Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC14568B
Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . .
6120
6205
6210
6461
CHAPTER 2
25
The Better Program

The BETTER program is offered on logic only, in dualinline plastic packages.
Better Processing
Standard Product Plus:
Level II (Suffix D)
100% burnin to MILSTD883 test conditions 160
hours at + 125C or 1.0 eV Arrhenus time/temperature
equivalent.
100% post burnin functional and dc parametric tests at
25C (or max rated TA at Motorolas option). Maximum
PDA of 2% (functional) and 5% (DC and functional).
HOW TO ORDER
MC14000B
Part
Identification
CP
Standard
Package
Suffix
D
BETTER
PROCESSING
LEVEL II = SUFFIX D
Part Marking
The Standard Motorola part number with the corresponding BETTER suffix can be order from your local authorized
Motorola distributor or Motorola sales offices. BETTER
pricing will be quoted as an adder to standard commercial
product price.
RAP
Reliability Audit Program
For Logic Integrated Circuits
1.0 INTRODUCTION
The Reliability Audit Program developed in March 1977 is
the Motorola internal reliability audit which is designed to assess outgoing product performance under accelerated stress
conditions. Logic Reliability Engineering has overall responsibility for RAP, including updating its requirements, interpreting its results, administration at offshore locations, and
monthly reporting of results. These reports are available at
CHAPTER 3
32
all sales offices. Also available is the Reliability and Quality

Handbook which contains data for all Motorola Semiconductors (#BR518S).
RAP is a system of environmental and electrical tests performed periodically on randomly selected samples of standard products. Each sample receives the tests specified in
section 2.0. Frequency of testing is specified per internal
document 12MRM15301A.
2.0 RAP TEST FLOW

Pull 500* piece sample from lot following Group A
acceptance.
45*
340
100
INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB
48 HRS
PTH***
48 HRS
TEMP CYCLES
40 CYCLES
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
ADD 460 CYCLES
INTERIM
ELECTRICAL
FINAL
INTERIM #
ELECTRICAL
INTERIM
TEST
ADD 500 CYCLES
FINAL
INTERIM*
TEST
PTH
48 HRS
(ADDITIONAL)
OP LIFE #
750 HRS
(ADDITIONAL)
TEMP CYCLES #
1000 CYCLES
(ADDITIONAL)
FINAL
ELECTRICAL
(48 HRS)
FINAL
ELECTRICAL
(96 HRS)
FINAL #
ELECTRICAL
(1000 HRS)
FINAL
ELECTRICAL
& SEAL**
(2000 CYCLES)
SCRAP
SCRAP
SCRAP
#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.
3.0 TEST CONDITIONS AND COMMENTS

PTHB 15 psig/121C/100% RH at rated VCC or VEE to
be performed on plastic encapsulated devices
only.
TEMP CYCLING MILSTD883, Method 1010, Condition C, 65C/+ 150C.
OP LIFE MILSTD883, Method 1005, Condition C
(Power plus Reverse Bias), TA = 145C.
NOTES:
1. All standard 25C dc and functional parameters will be
measured Go/No/Go at each readout.
2. Any indicated failure is first verified and then submitted to

the Product Analysis Lab for detailed analysis.
3. Sampling to include all package types routinely.
4. Device types sampled will be by generic type within each
logic I/C product family (CMOS, TTL, etc.) and will include
all assembly locations (Korea, Philippines, Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to approximately 800 hours of
85C/85% RH THB for VCC
15 V.
6. Only moisture related failures (like corrosion) are criteria
for failure on PTHB test.
7. Special device specifications (48As) for logic products will
reference 12MRM15301A as source of generic data for
any customer required monthly audit reports.
CHAPTER 3
33

The CMOS Devices in this volume which have a B or UB
suffix meet the minimum values for the industrystandardized# family specification. These standardized values are
shown in the Maximum Ratings and Electrical Characteristics Tables. In addition to a standard minimum specification
for characteristics the B/UB devices feature:
318 volt operational limits
Capable of driving two lowpower TTL loads or one low
power Schottky TTL load over the rated temperature
range
Direct Interface to HighSpeed CMOS
Maximum input current of 1 A at 15 volt power supply
over the temperature range
Parameters specified at 5.0, 10, and 15 volt supply
Noise margins: B Series
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply
UB Series
0.5 V min @ 5.0 V supply
The industrystandardized maximum ratings are shown at
the bottom of this page. Limits for the static characteristics
are shown in two formats: Table 1 is in the industry format
and Table 2 is in the equivalent Motorola format. The
Motorola format is used throughout this data book. Additional
specification values are shown on the individual data sheets.
Switching characteristics for the B and UB series devices
are specified under the following conditions:
Load Capacitance, CL, of 50 pF
Input Voltage equal to VSS VDD (RailtoRail swing)
Input pulse rise and fall times of 20 ns
Propagation Delay times measured from 50% point of
input voltage to 50% point of output voltage
Three different supply voltages: 5, 10, and 15 V
Exceptions to the B and UB Series Family

Specification
There are a number of devices which have a B or UB suffix
whose inputs and/or outputs vary somewhat from the family
specification because of functional requirements. Some
categories of notable exceptions are:
Devices with specialized outputs on the chip, such as
NPN emitterfollower drivers or transmission gates, do
not meet output specifications.
#Specifications coordinated by EIA/JEDEC SolidState Products
Council.
CHAPTER 4
42
Devices with specialized inputs, such as oscillator inputs, have unique input specifications.
Input Voltage
The input voltage specification is interpreted as the worstcase input voltage to produce an output level of 1 or 0.
This 1 or 0 output level is defined as a deviation from the
supply (VDD) and ground (VSS) levels. For a 5.0 V supply,
this deviation is 0.5 V; for a 10 V supply, 1.0 V; and for 15 V,
1.5 V. As an example, in a device operating at a 5.0 V supply,
the device with the input starting at ground is guaranteed to
switch on or before 3.5 V and not to switch up to 1.5 V.
Switching and not switching are defined as within 0.5 V of the
ideal output level for the example with a 5.0 V supply. The
actual switching level referred to the input is between 1.5 V
and 3.5 V.
Noise Margin
The values for input voltages and the defined output deviations lead to the calculated noise margins. Noise margin is
defined as the difference between V IL or V IH and Vout
(output deviation). As an example, for a noninverting buffer at
V DD = 5.0 volts: V IL = 1.5 volts and Vout = 0.5 volts. Therefore, Noise Margin equals V IL Vout = 1.0 volt. This figure is
useful while cascading stages (See Figure 1). With the input
to the first stage at a worstcase voltage level (V IL = 1.5 V),
the output is guaranteed to be no greater than 0.5 volts with
a 5.0 volt supply. Since the maximum allowable logic 0 for
the second stage is 1.5 volts, this 0.5 volt output provides a
1.0 volt margin for noise to the next stage.
Output Drive Current

Devices in the B Series are capable of sinking a minimum
of 0.36 mA over the temperature range with a 5.0 V supply.
This value guarantees that these CMOS devices will drive
one lowpower Schottky TTL input.
B Series vs UB CMOS
The primary difference between B series and UB series
devices is that UB series gates and inverters are constructed
with a single inverting stage between input and output. The
decreased gain caused by using a single stage results in less
noise immunity and a transfer characteristic that is less ideal.
The decreased gain is quite useful when CMOS Gates and
inverters are used in a Linear mode to form oscillators,
monostables, or amplifiers. The decreased gain results in increased stability and a cleaner output waveform. In addition
to linear operation, the UB gates and inverters offer an increase in speed, since only a single stage is involved.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as HighSpeed CMOS Logic.
MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol
Parameters
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
Input or Output Voltage (DC or Transient)
0.5 to VDD + 0.5
Iin, lout
Input or Output Current (DC or Transient),

per Pin
10
mA
500
mW
65 to + 150
_C
PD
Power Dissipation, per Package
Tstg
Storage Temperature
TL
Lead Temperature (8Second Soldering)
260
_C
* Maximum Ratings are those values values beyond which damage to the device may occur.
Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C To 125_C
5.0 V
Vout = 0.5 V
VIL = 1.5 V
FIRST STAGE
(NONINVERTING BUFFER)
Vout
VIL = 1.5 V SECOND STAGE

(NONINVERTING BUFFER)
Figure 1.
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications
ELECTRICAL CHARACTERISTICS
Limits
Parameter
P
IDD
Quiescent
Device Current
GATES
BUFFERS,
FLIPFLOPS
MSI
VOL
VOH
VIL
T
Temp
Range
VDD
(Vdc)
Mil
5
10
15
Comm
5
10
15
Mil
5
10
15
Comm
5
10
15
Mil
5
10
15
TLOW*
Conditions
C
di i
Vin = VSS or VDD

All valid input
combinations
VIN = VSS or VDD

All valid input
combinations
VIN = VSS or VDD
Comm
5
10
15
LowLevel
Output Voltage
All
5
10
15
VIN = VSS or VDD

|IO| < 1 A
HighLevel
Output Voltage
All
5
10
15
VIN = VSS or VDD

|IO| < 1 A
Input
Low Voltage#
B Types
All
5
10
15
Min
All valid input

combinations
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
Max
+ 25_C
Max
Units
U
i
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
Adc
1.0
2.0
4.0
1.0
2.0
4.0
7.5
15
30
Adc
1.0
2.0
4.0
1.0
2.0
4.0
30
60
120
Adc
4
8
16
4.0
8.0
16.0
30
60
120
Adc
5
10
20
5
10
20
150
300
600
Adc
20
40
80
20
40
80
150
300
600
Adc
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
4.95
9.95
14.95
Min
Max
THIGH*
4.95
9.95
14.95
1.5
3.0
4.0
Min
4.95
9.95
14.95
1.5
3.0
4.0
Vdc
1.5
3.0
4.0
Vdc
CHAPTER 4
43
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)
Limits
Parameter
Temp
Range
VDD
(Vdc)
TLOW*
Conditions
Min
Max
+ 25_C
Min
Max
Min
Units
Input
Low Voltage#
UB Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
VIH
Input
High Voltage#
B Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
Vdc
VIH
Input
High Voltage#
UB Types
All
5
10
15
VO = 0.5V or 4.5V
VO = 1.0V or 9.0V
VO = 1.5V or 13.5V
|IO| < 1 A
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
Vdc
IOL
Output Low
(Sink) Current
Mil
VO = 0.4V,
VIN = 0 or 5V
VO = 0.5V,
VIN = 0 or 10V
VO = 1.5V,
VIN = 0 or 15V
0.64
0.51
0.36
1.6
1.3
0.9
4.2
3.4
2.4
0.52
0.44
0.36
1.3
1.1
0.9
3.6
3.0
2.4
0.25
0.2
0.14
0.62
0.5
0.35
1.8
1.5
1.1
0.2
0.16
0.12
0.5
0.4
0.3
1.4
1.2
1.0
15
Com
10
15
IOH
Output High
(Source) Current
Mil
10
15
Com
VO = 0.4V,
VIN = 0 or 5V
VO = 0.5V,
VIN = 0 or 10V
VO = 1.5V,
VIN = 0 or 15V
VO = 4.6V,
VIN = 0 or 5V
VO = 9.5V,
VIN = 0 or 10V
VO = 13.5V,
VIN = 0 or 15V
15
VO = 4.6V,
VIN = 0 or 5V
VO = 9.5V,
VIN = 0 or 10V
VO = 13.5V
VIN = 0 or 15V
10
1.0
2.0
2.5
Max
VIL
10
1.0
2.0
2.5
THIGH*
1.0
2.0
2.5
mAdc
mAdc
mAdc
mAdc
IIN
Input Current
Mil
Comm
15
15
VIN = 0 or 15V
VIN = 0 or 15V
0.1
0.3
0.1
0.3
1.0
1.0
Adc
Adc
Ioz
3State Output
Leakage Current
Mil
Comm
15
15
VIN = 0 or 15V
VIN = 0 or 15V
0.4
1.6
0.4
1.6
12
12
Adc
Adc
CIN
Input Capacitance
per unit load
All
Any Input
7.5
pF
* TLOW = 55_C for Military temperature range device, 40C for Commercial temperature range device.
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.
CHAPTER 4
44
Table 2. Motorola Format for CMOS Industry B and UB Series Specifications
Characteristic
Ch
i i
55_C
25_C
+ 125_C
VDD
Vdc
Min
Max
Min
Max
Min
Max
Unit
U i
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
3.5
7.0
11
5.0
10
15
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
0.7
0.14
0.35
1.1
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
Iin
Cin
15
0.1
0.1
1.0
Adc
7.5
pF
IDD
5.0
10
15
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
Adc
FlipFlop and Buffer Quiescent Current

(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
1.0
2.0
4.0
30
60
120
Adc
MSI Quiescent Current

(Per Package)
IDD
5.0
10
15
5.0
10
20
5.0
10
20
150
300
600
Adc
LSI Quiescent Current
IDD
Output Voltage
Vin = VDD or 0
Symbol
S b l
Vin = 0 or VDD
Input Voltage B Types

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Input Voltage UB Types

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
0 Level
1 Level
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current B Gates
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Output Drive Current UB Gates
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
VIL
Vdc
VIH
Vdc
mAdc
IOH
Source
Sink
IOL
mAdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Output Drive Current Other Devices

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Vdc
Sink
IOL
mAdc
IOH
Source
Input Capacitance
(Vin = 0)
Gate Quiescent Current
(Per Package)
Sink
See Individual Data Sheets.
CHAPTER 4
45

HANDLING PRECAUTIONS
All MOS devices have insulated gates that are subject to
voltage breakdown. The gate oxide for Motorola CMOS devices is about 900 thick and breaks down at a gatesource
potential of about 100 volts. To guard against such a breakdown from static discharge or other voltage transients, the
protection networks shown in Figures 1A and 1B are used on
each input to the CMOS device.
Static damaged devices behave in various ways, depending on the severity of the damage. The most severely damaged inputs are the easiest to detect because the input has
been completely destroyed and is either shorted to VDD,
shorted to VSS, or opencircuited. The effect is that the device no longer responds to signals present at the damaged
input. Less severe cases are more difficult to detect because
they show up as intermittent failures or as degraded performance. Another effect of static damage is that the inputs
generally have increased leakage currents.
Although the input protection network does provide a great
deal of protection, CMOS devices are not immune to large
static voltage discharges that can be generated during handling. For example, static voltages generated by a person
walking across a waxed floor have been measured in the
4 15 kV range (depending on humidity, surface conditions,
etc.). Therefore, the following precautions should be
observed:
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD or
VSS.
3. All lowimpedance equipment (pulse generators, etc.)
should be connected to CMOS inputs only after the device is powered up. Similarly, this type of equipment
should be disconnected before power is turned off.
4. Circuit boards containing CMOS devices are merely
extensions of the devices, and the same handling
precautions apply. Contacting edge connectors wired
directly to device inputs can cause damage. Plastic
wrapping should be avoided. When external connec-
5.
6.
7.
8.
9.
10.
tions to a PC board are connected to an input of a CMOS

device, a resistor should be used in series with the input.
This resistor helps limit accidental damage if the PC
board is removed and brought into contact with static
generating materials. The limiting factor for the series
resistor is the added delay. This is caused by the time
constant formed by the series resistor and input
capacitance. Note that the maximum input rise and fall
times should not be exceeded. In Figure 2, two possible
networks are shown using a series resistor to reduce
ESD (Electrostatic Discharge) damage. For convenience, an equation for added propagation delay and
rise time effects due to series resistance size is given.
All CMOS devices should be stored or transported in
materials that are antistatic. CMOS devices must not be
inserted into conventional plastic snow, styrofoam, or
plastic trays, but should be left in their original container
until ready for use.
All CMOS devices should be placed on a grounded
bench surface and operators should ground themselves prior to handling devices, since a worker can be
statically charged with respect to the bench surface.
Wrist straps in contact with skin are strongly recommended. See Figure 3 for an example of a typical work
station.
Nylon or other static generating materials should not
come in contact with CMOS devices.
If automatic handlers are being used, high levels of
static electricity may be generated by the movement of
the device, the belts, or the boards. Reduce static build
up by using ionized air blowers or room humidifiers. All
parts of machines which come into contact with the top,
bottom, or sides of IC packages must be grounded to
metal or other conductive material.
Cold chambers using CO2 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
When leadstraightening or handsoldering is necessary, provide ground straps for the apparatus used and
be sure that soldering ties are grounded.
INPUT PROTECTION NETWORK

VDD
CMOS
INPUT
VDD
TO CIRCUIT
< 1500
VSS
Figure 1a. Input Protection Network

Double Diode
CHAPTER 5
52
CMOS
INPUT
300
VSS
Figure 1b. Input Protection Network

Triple Diode
11. The following steps should be observed during wave

solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to an
earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an earth
ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic
containers prior to being moved to subsequent
stations.
12. The following steps should be observed during board
cleaning operations:
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the
antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the cleaning basket.
e. High velocity air movement or application of solvents
and coatings should be employed only when
assembled printed circuit boards are grounded and
a static eliminator is directed at the board.
13. The use of static detection meters for production line

surveillance is highly recommended.
14. Equipment specifications should alert users to the presence of CMOS devices and require familiarization with
this specification prior to performing any kind of maintenance or replacement of devices or modules.
15. Do not insert or remove CMOS devices from test
sockets with power applied. Check all power supplies to
be used for testing devices to be certain there are no
voltage transients present.
16. Double check test equipment setup for proper polarity
of VDD and VSS before conducting parametric or functional testing.
17. Do not recycle shipping rails or trays. Repeated use
causes deterioration of their antistatic coating.
RECOMMENDED FOR READING:

Total Control of the Static in Your Business
Available by writing to:
3M Company
Static Control Systems
P.O. Box 2963
Austin, Texas 787692963
Or by Calling:
18003281368
VDD
TO OFFBOARD
CONNECTION
R1
CMOS
INPUT
OR
OUTPUT
D1
TO OFFBOARD
CONNECTION
CMOS
INPUT
OR
OUTPUT
R2
D2
Advantage:
Disadvantage:
Requires minimal board area

R1 > R2 for the same level of
protection, therefore rise and fall
times, propagation delays, and output
drives are severely affected.
Advantage:
Disadvantage:
VSS
R2 < R1 for the same
level of protection.
Impact on ac and dc
characteristics is minimized
More board area, higher initial cost
Note: These networks are useful for protecting the following

A digital inputs and outputs
C 3state outputs
B analog inputs and outputs
D bidirectional (I/O) ports
PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
C@k
where:
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven devices
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations
Figure 1. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility
CHAPTER 5
53
2
5
NOTES: 1. 1/16 inch conductive sheet stock covering bench

top work area.
2. Ground strap.
3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
5. Room humidifier. Primarily for use in areas where
the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
buildings to be less than outside humidity.
RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station
POWER SUPPLIES
CMOS devices have low power requirements and the ability to operate over a wide range of supply voltages. These
two characteristics allow CMOS designs to be implemented
using inexpensive, conventional power supplies, instead of
switching power supplies and power supplies with cooling
fans. In addition, batteries may be used as either a primary
power source or for emergency backup.
The absolute maximum power supply voltage for 14000
Series Metalgate CMOS is 18.0 Vdc. Figure 4 offers some
insight as to how this specification was derived. In the figure,
VS is the maximum power supply voltage and IS is the sustaining current of the latchup mode. The value of VS was
chosen so that the secondary breakdown effect may be
avoided.
In an ideal system design, a power supply should be
designed to deliver only enough current to insure proper
operation of all devices. The obvious benefit of this type
design is cost savings; an added benefit is protection against
the possibility of latchup related failures. This system

protection can be provided by the power supply filter and/or
voltage regulator.
CMOS devices can be used with battery or battery backup
systems. A few precautions should be taken when designing
batteryoperated systems:
1. The recommended power supply voltage should be observed. For battery backup systems such as the one in
Figure 5, the battery voltage must be at least 3.7 Volts
(3 Volts from the minimum power supply voltage and
0.7 Volts to account for the voltage drop across the series diode).
2. Inputs that might go above the battery backup voltage
should either use a series resistor to limit the input current to less than 10 mA or use the MC14049UB or
MC14050B hightolow voltage translators.
3. Outputs that are subject to voltage levels above VDD or
below VSS should be protected with a series resistor to
limit the current to less than 10 mA or with clamping
diodes.
IDD
LATCH
UP MODE
IS
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
AVALANCHE
VS
VS = DATA SHEET MAXIMUM SUPPLY RATING
VDD
Figure 3. Secondary Breakdown Characteristics
CHAPTER 5
54
POWER SUPPLY
LINE POWER ONLY

SYSTEM
BATTERY BACKUP
RECHARGE
BATTERY BACKUP
SYSTEM
MC14049UB
MC14050B
CMOS
SYSTEM
CMOS
SYSTEM
MC14049UB
MC14050B
Figure 4. Battery Backup Interface
VDD = 5.0 Vdc
All inputs, while in the recommended operating range (VSS

< Vin < VDD) can be modeled as shown in Figure 6. For input
voltages in this range, diodes D1 and D2 are modeled as
resistors, representing the reverse bias impedance of the
diodes. The maximum input current is worst case, 1 A,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This
model does not apply to inputs with pullup or pulldown
resistors.
Vout , OUTPUT VOLTAGE (V)
INPUTS
SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR
5.0
4.0
SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND
3.0
2.0
1.0
0
0
VDD
1.0
R1 = R2 = HIGH Z
Figure 5. Input Model for VSS
7.5 pF
v Vin v VDD
When left opencircuited, the inputs may selfbias at or

near the typical switchpoint, where both the Pchannel and
Nchannel transistors are conducting, causing excessive
current drain. Due to the high gain of the inverters (see
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching.
3.0
4.0
5.0
Vin, INPUT VOLTAGE (V)
Figure 6. Typical Transfer Characteristics

for Buffered Devices
R1
R2
2.0
For these reasons, all unused inputs should be connected

either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
FROM
EDGE
CONNECTOR
RS
CMOS
DEVICE
100 k
Figure 7. External Protection
CHAPTER 5
55
For input voltages outside of the recommended operating

range, the CMOS input is modeled as in Figure 9. The
resistordiode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from VSS 0.5 V
to VDD + 0.5 V and a maximum current of 10 mA. With the
above input ratings, most designs will require no special
terminations or design considerations.
D1
1.5 k
D2
7.5 pF
Figure 8. Input Model for Vin > VDD or Vin < VSS
Other specifications that should be noted are the maximum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 s
maximum rise and fall time at VDD = 5.0 V, 5 s at 10 V, or
4 s at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on the
input is amplified, and passed through to the output, causing
oscillations. The oscillation may have a low enough frequency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 s at 5.0 V, 5 s at 10 V, or 4 s at 15 V,
Schmitttrigger devices such as the MC14093B, MC14583B,
MC14584B, MC14106B, HC14, or HC132 are recommended
for squaringup these slow transitions.
VDD
Vin
VSS
VOH
Vout
VOL
Figure 9. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS BSeries outputs are buffered to insure consistent output voltage and current performance. All buffered outputs have guaranteed output voltages of VOL = 0.05 V and
VOH = VDD 0.05 V for Vin = VDD or VSS and lout = 0 A. The
output drives for all buffered CMOS devices are such that
1 LSTTL load can be driven across the full temperature
range.
CHAPTER 5
56
CMOS outputs are limited to externally forced output

voltages of VSS 0.5 V
Vout
VDD + 0.5 V. When
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more information on this, see the explanation of CMOS Latch Up in this
section.
The maximum rated output current for most outputs is
10 mA. The output shortcircuit currents of these devices
typically exceed these limits. Care must be taken not to exceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the crosssection of a typical CMOS inverter and Figure 12 shows the parasitic bipolar devices. The
circuit formed by the parasitic transistors and resistors is the
basic configuration of a silicon controlled rectifier, or SCR. In
the latch up condition, transistors Q1 and Q2 are turned ON,
each providing the base current necessary for the other to
remain in saturation, thereby latching the devices in the ON
state. Unlike a conventional SCR, where the device is turned
ON by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned ON by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be greater than VDD + 0.5 V or less than VSS 0.5 V and have sufficient current to trigger the SCR. The latchup mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the maximum rated values, as follows:
0.5 V Vin or Vout VDD + 0.5 V (referenced to VSS)
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
or series resistors may be used in plugin board applications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that powersupply lines are
free of excessive noise.
5. Limit the available power supply current to the devices
that are subject to latchup conditions. This can be accomplished with the power supply filtering network or
with a currentlimiting regulator.
PCHANNEL
NCHANNEL
INPUT
VDD
N+
PCHANNEL
OUTPUT
VDD
FIELD OXIDE
P+
P+
N SUBSTRATE
OUTPUT
FIELD OXIDE
VSS
NCHANNEL
OUTPUT
N+
N+
P+
FIELD OXIDE
P WELL
Figure 10. CMOS Wafer Cross Section
Q1
NCHANNEL OUTPUT
N+
VSS
N+
N
P
NSUBSTRATE RESISTANCE
N
P+
VSS
PWELL RESISTANCE
VDD
P
Q2
P+
VDD
PCHANNEL OUTPUT
Figure 11. Latch Up Circuit Schematic
CHAPTER 5
57

HANDLING PRECAUTIONS
All MOS devices have insulated gates that are subject to
voltage breakdown. The gate oxide for Motorola CMOS devices is about 900 thick and breaks down at a gatesource
potential of about 100 volts. To guard against such a breakdown from static discharge or other voltage transients, the
protection networks shown in Figures 1A and 1B are used on
each input to the CMOS device.
Static damaged devices behave in various ways, depending on the severity of the damage. The most severely damaged inputs are the easiest to detect because the input has
been completely destroyed and is either shorted to VDD,
shorted to VSS, or opencircuited. The effect is that the device no longer responds to signals present at the damaged
input. Less severe cases are more difficult to detect because
they show up as intermittent failures or as degraded performance. Another effect of static damage is that the inputs
generally have increased leakage currents.
Although the input protection network does provide a great
deal of protection, CMOS devices are not immune to large
static voltage discharges that can be generated during handling. For example, static voltages generated by a person
walking across a waxed floor have been measured in the
4 15 kV range (depending on humidity, surface conditions,
etc.). Therefore, the following precautions should be
observed:
1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VDD or
VSS.
3. All lowimpedance equipment (pulse generators, etc.)
should be connected to CMOS inputs only after the device is powered up. Similarly, this type of equipment
should be disconnected before power is turned off.
4. Circuit boards containing CMOS devices are merely
extensions of the devices, and the same handling
precautions apply. Contacting edge connectors wired
directly to device inputs can cause damage. Plastic
wrapping should be avoided. When external connec-
5.
6.
7.
8.
9.
10.
tions to a PC board are connected to an input of a CMOS

device, a resistor should be used in series with the input.
This resistor helps limit accidental damage if the PC
board is removed and brought into contact with static
generating materials. The limiting factor for the series
resistor is the added delay. This is caused by the time
constant formed by the series resistor and input
capacitance. Note that the maximum input rise and fall
times should not be exceeded. In Figure 2, two possible
networks are shown using a series resistor to reduce
ESD (Electrostatic Discharge) damage. For convenience, an equation for added propagation delay and
rise time effects due to series resistance size is given.
All CMOS devices should be stored or transported in
materials that are antistatic. CMOS devices must not be
inserted into conventional plastic snow, styrofoam, or
plastic trays, but should be left in their original container
until ready for use.
All CMOS devices should be placed on a grounded
bench surface and operators should ground themselves prior to handling devices, since a worker can be
statically charged with respect to the bench surface.
Wrist straps in contact with skin are strongly recommended. See Figure 3 for an example of a typical work
station.
Nylon or other static generating materials should not
come in contact with CMOS devices.
If automatic handlers are being used, high levels of
static electricity may be generated by the movement of
the device, the belts, or the boards. Reduce static build
up by using ionized air blowers or room humidifiers. All
parts of machines which come into contact with the top,
bottom, or sides of IC packages must be grounded to
metal or other conductive material.
Cold chambers using CO2 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
When leadstraightening or handsoldering is necessary, provide ground straps for the apparatus used and
be sure that soldering ties are grounded.
INPUT PROTECTION NETWORK

VDD
CMOS
INPUT
VDD
TO CIRCUIT
< 1500
VSS
Figure 1a. Input Protection Network

Double Diode
CHAPTER 5
52
CMOS
INPUT
300
VSS
Figure 1b. Input Protection Network

Triple Diode
11. The following steps should be observed during wave

solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to an
earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an earth
ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic
containers prior to being moved to subsequent
stations.
12. The following steps should be observed during board
cleaning operations:
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the
antistatic container.
d. Cleaned assemblies should be placed in antistatic
containers immediately after removal from the cleaning basket.
e. High velocity air movement or application of solvents
and coatings should be employed only when
assembled printed circuit boards are grounded and
a static eliminator is directed at the board.
13. The use of static detection meters for production line

surveillance is highly recommended.
14. Equipment specifications should alert users to the presence of CMOS devices and require familiarization with
this specification prior to performing any kind of maintenance or replacement of devices or modules.
15. Do not insert or remove CMOS devices from test
sockets with power applied. Check all power supplies to
be used for testing devices to be certain there are no
voltage transients present.
16. Double check test equipment setup for proper polarity
of VDD and VSS before conducting parametric or functional testing.
17. Do not recycle shipping rails or trays. Repeated use
causes deterioration of their antistatic coating.
RECOMMENDED FOR READING:

Total Control of the Static in Your Business
Available by writing to:
3M Company
Static Control Systems
P.O. Box 2963
Austin, Texas 787692963
Or by Calling:
18003281368
VDD
TO OFFBOARD
CONNECTION
R1
CMOS
INPUT
OR
OUTPUT
D1
TO OFFBOARD
CONNECTION
CMOS
INPUT
OR
OUTPUT
R2
D2
Advantage:
Disadvantage:
Requires minimal board area

R1 > R2 for the same level of
protection, therefore rise and fall
times, propagation delays, and output
drives are severely affected.
Advantage:
Disadvantage:
VSS
R2 < R1 for the same
level of protection.
Impact on ac and dc
characteristics is minimized
More board area, higher initial cost
Note: These networks are useful for protecting the following

A digital inputs and outputs
C 3state outputs
B analog inputs and outputs
D bidirectional (I/O) ports
PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE
R [ t
C@k
where:
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven devices
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations
Figure 1. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility
CHAPTER 5
53
2
5
NOTES: 1. 1/16 inch conductive sheet stock covering bench

top work area.
2. Ground strap.
3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
5. Room humidifier. Primarily for use in areas where
the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
buildings to be less than outside humidity.
RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station
POWER SUPPLIES
CMOS devices have low power requirements and the ability to operate over a wide range of supply voltages. These
two characteristics allow CMOS designs to be implemented
using inexpensive, conventional power supplies, instead of
switching power supplies and power supplies with cooling
fans. In addition, batteries may be used as either a primary
power source or for emergency backup.
The absolute maximum power supply voltage for 14000
Series Metalgate CMOS is 18.0 Vdc. Figure 4 offers some
insight as to how this specification was derived. In the figure,
VS is the maximum power supply voltage and IS is the sustaining current of the latchup mode. The value of VS was
chosen so that the secondary breakdown effect may be
avoided.
In an ideal system design, a power supply should be
designed to deliver only enough current to insure proper
operation of all devices. The obvious benefit of this type
design is cost savings; an added benefit is protection against
the possibility of latchup related failures. This system

protection can be provided by the power supply filter and/or
voltage regulator.
CMOS devices can be used with battery or battery backup
systems. A few precautions should be taken when designing
batteryoperated systems:
1. The recommended power supply voltage should be observed. For battery backup systems such as the one in
Figure 5, the battery voltage must be at least 3.7 Volts
(3 Volts from the minimum power supply voltage and
0.7 Volts to account for the voltage drop across the series diode).
2. Inputs that might go above the battery backup voltage
should either use a series resistor to limit the input current to less than 10 mA or use the MC14049UB or
MC14050B hightolow voltage translators.
3. Outputs that are subject to voltage levels above VDD or
below VSS should be protected with a series resistor to
limit the current to less than 10 mA or with clamping
diodes.
IDD
LATCH
UP MODE
IS
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
AVALANCHE
VS
VS = DATA SHEET MAXIMUM SUPPLY RATING
VDD
Figure 3. Secondary Breakdown Characteristics
CHAPTER 5
54
POWER SUPPLY
LINE POWER ONLY

SYSTEM
BATTERY BACKUP
RECHARGE
BATTERY BACKUP
SYSTEM
MC14049UB
MC14050B
CMOS
SYSTEM
CMOS
SYSTEM
MC14049UB
MC14050B
Figure 4. Battery Backup Interface
VDD = 5.0 Vdc
All inputs, while in the recommended operating range (VSS

< Vin < VDD) can be modeled as shown in Figure 6. For input
voltages in this range, diodes D1 and D2 are modeled as
resistors, representing the reverse bias impedance of the
diodes. The maximum input current is worst case, 1 A,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This
model does not apply to inputs with pullup or pulldown
resistors.
Vout , OUTPUT VOLTAGE (V)
INPUTS

5.0
4.0

3.0
2.0
1.0
0
0
VDD
1.0
R1 = R2 = HIGH Z
Figure 5. Input Model for VSS
7.5 pF
v Vin v VDD
When left opencircuited, the inputs may selfbias at or

near the typical switchpoint, where both the Pchannel and
Nchannel transistors are conducting, causing excessive
current drain. Due to the high gain of the inverters (see
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching.
3.0
4.0
5.0
Vin, INPUT VOLTAGE (V)

for Buffered Devices
R1
R2
2.0
For these reasons, all unused inputs should be connected

either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
FROM
EDGE
CONNECTOR
RS
CMOS
DEVICE
100 k
Figure 7. External Protection
CHAPTER 5
55
For input voltages outside of the recommended operating

range, the CMOS input is modeled as in Figure 9. The
resistordiode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from VSS 0.5 V
to VDD + 0.5 V and a maximum current of 10 mA. With the
above input ratings, most designs will require no special
terminations or design considerations.
D1
1.5 k
D2
7.5 pF
Figure 8. Input Model for Vin > VDD or Vin < VSS
Other specifications that should be noted are the maximum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 s
maximum rise and fall time at VDD = 5.0 V, 5 s at 10 V, or
4 s at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on the
input is amplified, and passed through to the output, causing
oscillations. The oscillation may have a low enough frequency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 s at 5.0 V, 5 s at 10 V, or 4 s at 15 V,
Schmitttrigger devices such as the MC14093B, MC14583B,
MC14584B, MC14106B, HC14, or HC132 are recommended
for squaringup these slow transitions.
VDD
Vin
VSS
VOH
Vout
VOL
Figure 9. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS BSeries outputs are buffered to insure consistent output voltage and current performance. All buffered outputs have guaranteed output voltages of VOL = 0.05 V and
VOH = VDD 0.05 V for Vin = VDD or VSS and lout = 0 A. The
output drives for all buffered CMOS devices are such that
1 LSTTL load can be driven across the full temperature
range.
CHAPTER 5
56
CMOS outputs are limited to externally forced output

voltages of VSS 0.5 V
Vout
VDD + 0.5 V. When
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more information on this, see the explanation of CMOS Latch Up in this
section.
The maximum rated output current for most outputs is
10 mA. The output shortcircuit currents of these devices
typically exceed these limits. Care must be taken not to exceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the crosssection of a typical CMOS inverter and Figure 12 shows the parasitic bipolar devices. The
circuit formed by the parasitic transistors and resistors is the
basic configuration of a silicon controlled rectifier, or SCR. In
the latch up condition, transistors Q1 and Q2 are turned ON,
each providing the base current necessary for the other to
remain in saturation, thereby latching the devices in the ON
state. Unlike a conventional SCR, where the device is turned
ON by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned ON by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be greater than VDD + 0.5 V or less than VSS 0.5 V and have sufficient current to trigger the SCR. The latchup mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the maximum rated values, as follows:
0.5 V Vin or Vout VDD + 0.5 V (referenced to VSS)
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
or series resistors may be used in plugin board applications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that powersupply lines are
free of excessive noise.
5. Limit the available power supply current to the devices
that are subject to latchup conditions. This can be accomplished with the power supply filtering network or
with a currentlimiting regulator.
PCHANNEL
NCHANNEL
INPUT
VDD
N+
PCHANNEL
OUTPUT
VDD
FIELD OXIDE
P+
P+
N SUBSTRATE
OUTPUT
FIELD OXIDE
VSS
NCHANNEL
OUTPUT
N+
N+
P+
FIELD OXIDE
P WELL
Figure 10. CMOS Wafer Cross Section
Q1
NCHANNEL OUTPUT
N+
VSS
N+
N
P
NSUBSTRATE RESISTANCE
N
P+
VSS
PWELL RESISTANCE
VDD
P
Q2
P+
VDD
PCHANNEL OUTPUT
Figure 11. Latch Up Circuit Schematic
CHAPTER 5
57
Data Sheets
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14000UB
Dual 3-Input NOR" Gate
Plus Inverter
L SUFFIX
CERAMIC
CASE 632
The MC14000UB dual 3input NOR gate plus inverter is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find primary
use where low power dissipation and/or high noise immunity is desired.
P SUFFIX
PLASTIC
CASE 646
Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
PinforPin Replacement for CD4000UB
D SUFFIX
SOIC
CASE 751A

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = 55 to 125C for all packages.
LOGIC DIAGRAM
3
4
5
11
12
13
CIRCUIT SCHEMATIC
VDD
10
14 11 12 13
8
8
9
VDD = PIN 14
VSS = PIN 7
4
9
5
VSS
7 6
10
PIN ASSIGNMENT
NC
14
VDD
NC
13
IN 3B
IN 1A
12
IN 2B
IN 2A
11
IN 1B
IN 3A
10
OUTB
OUTA
OUTC
VSS
IN 1C
NC = NO CONNECTION
MC14000UB
62
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
+ 125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current**

(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
mAdc
IT = (0.3 A/kHz) f + IDD/N

Adc
#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
** The formulas given are for the typical characteristics only at 25_C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14000UB
63
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
Output Rise Time

tTLH = (3.0 ns/pF) CL + 30 ns
tTLH
Output Fall Time

tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time

tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
tPLH,
tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
115
55
40
230
110
80
Unit
ns
ns
ns
* The formulas given are for the typical characteristics only at 25_C.
VDD
20 ns
14
OUTPUT
7
VSS
VDD
90%
50%
10%
INPUT
INPUT
PULSE
GENERATOR
20 ns
VSS
tPHL
CL
tPLH
VOH
90%
50%
10%
OUTPUT
VOL
tTHL
tTLH
Figure 1. Switching Time Test Circuit and Waveforms
16
16
VDD = 15 Vdc
10 Vdc
10
a ONE INPUT ONLY

AND INVERTER
b TWO INPUTS
c THREE INPUTS
a
c
8.0
6.0
5.0 Vdc
4.0
8.0
ID = 15 Vdc
6.0
4.0
ID = 10 Vdc
2.0
2.0
0
0
2.0
4.0
6.0
8.0
10
12
14
Vin, INPUT VOLTAGE (Vdc)
Figure 2. Typical Voltage and Current

Transfer Characteristics
MC14000UB
64
UNUSED INPUTS
CONNECTED TO VSS
14
16
Vout , OUTPUT VOLTAGE (Vdc)
12
VDD = 15 Vdc
TA = 25C
ID , DRAIN CURRENT (mAdc)
14
12
10 Vdc
10
b
a
8.0
6.0
a TA = + 125C
b TA = 55C
5.0 Vdc
4.0
a
2.0
0
0
2.0
4.0
6.0
8.0
10
12
14
16
Figure 3. Typical Voltage Transfer

Characteristics versus Temperature
MOTOROLA
MC14001B
Quad 2-Input NOR Gate
B-Suffix Series CMOS Gates
MC14002B
The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
All Outputs Buffered
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
PinforPin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
Dual 4-Input NOR Gate
MC14011B
Quad 2-Input NAND Gate
MC14012B
Dual 4-Input NAND Gate
MC14023B
Triple 3-Input NAND Gate
MC14025B
Triple 3-Input NOR Gate
MC14068B
P SUFFIX
PLASTIC
CASE 646
L SUFFIX
CERAMIC
CASE 632
8-Input NAND Gate
D SUFFIX
SOIC
CASE 751A
MC14071B
Quad 2-Input OR Gate
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
MC14072B
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
260
_C
Dual 4-Input OR Gate
MC14073B
Triple 3-Input AND Gate
MC14075B
Triple 3-Input OR Gate
MC14078B
8-Input NOR Gate
MC14081B
Quad 2-Input AND Gate
MC14082B
Dual 4-Input AND Gate
This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14001B
65
LOGIC DIAGRAMS
NAND
OR
AND
MC14001B
Quad 2Input NOR Gate
MC14011B
Quad 2Input NAND Gate
MC14071B
Quad 2Input OR Gate
MC14081B
Quad 2Input AND Gate
2 INPUT
NOR
1
2
1
2
1
2
1
2
5
6
5
6
5
6
5
6
8
9
10
8
9
10
8
9
10
8
9
10
12
13
11
12
13
11
12
13
11
12
13
11
3 INPUT
MC14025B
Triple 3Input NOR Gate
1
2
8
3
4
5
11
12
13
10
4 INPUT
MC14002B
Dual 4Input NOR Gate
2
3
4
5
9
10
11
12
13
NC = 6, 8
MC14023B
Triple 3Input NAND Gate
1
2
8
3
4
5
11
12
13
8 INPUT
MC14001B
66
10
2
3
4
5
9
10
11
12
13
NC = 6, 8
1
2
8
3
4
5
11
12
13
10
MC14072B
Dual 4Input OR Gate
2
3
4
5
9
10
11
12
13
NC = 6, 8
MC14073B
Triple 3Input AND Gate
1
2
8
3
4
5
11
12
13
10
MC14082B
Dual 4Input AND Gate
2
3
4
5
9
10
11
12
13
NC = 6, 8
MC14068B
8Input NAND Gate
13
NC = 6, 8
MC14012B
Dual 4Input NAND Gate
MC14078B
8Input NOR Gate
2
3
4
5
9
10
11
12
MC14075B
Triple 3Input OR Gate
2
3
4
5
9
10
11
12
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
13
NC = 6, 8
PIN ASSIGNMENTS
MC14001B
MC14002B
IN 1A
14
VDD
OUTA
14
VDD
MC14011B
MC14012B
IN 1A
14
VDD
OUTA
14
VDD
IN 2A
13
IN 2D
IN 1A
13
OUTB
IN 2A
13
IN 2D
IN 1A
13
OUTB
OUTA
12
IN 1D
IN 2A
12
IN 4B
OUTA
12
IN 1D
IN 2A
12
IN 4B
OUTB
11
OUTD
IN 3A
11
IN 3B
OUTB
11
OUTD
IN 3A
11
IN 3B
IN 1B
10
OUTC
IN 4A
10
IN 2B
IN 1B
10
OUTC
IN 4A
10
IN 2B
IN 2B
IN 2C
NC
IN 1B
IN 2B
IN 2C
NC
IN 1B
VSS
IN 1C
VSS
NC
VSS
IN 1C
VSS
NC
MC14023B
MC14025B
MC14068B
8Input NAND Gate
MC14071B
Quad 2Input OR Gate
IN 1A
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
NC
14
VDD
IN 2A
13
IN 3C
IN 2A
13
IN 3C
IN 1
13
OUT
IN 2A
13
IN 2D
IN 1B
12
IN 2C
IN 1B
12
IN 2C
IN 2
12
IN 8
OUTA
12
IN 1D
IN 2B
11
IN 1C
IN 2B
11
IN 1C
IN 3
11
IN 7
OUTB
11
OUTD
IN 3B
10
OUTC
IN 3B
10
OUTC
IN 4
10
IN 6
IN 1B
10
OUTC
OUTB
OUTA
OUTB
OUTA
NC
IN 5
IN 2B
IN 2C
VSS
IN 3A
VSS
IN 3A
VSS
NC
VSS
IN 1C
MC14072B
Dual 4Input OR Gate
MC14073B
Triple 3Input AND Gate
MC14075B
Triple 3Input OR Gate
MC14078B
8Input NOR Gate
OUTA
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
NC
14
VDD
IN 1A
13
OUTB
IN 2A
13
IN 3C
IN 2A
13
IN 3C
IN 1
13
OUT
IN 2A
12
IN 4B
IN 1B
12
IN 2C
IN 1B
12
IN 2C
IN 2
12
IN 8
IN 3A
11
IN 3B
IN 2B
11
IN 1C
IN 2B
11
IN 1C
IN 3
11
IN 7
IN 4A
10
IN 2B
IN 3B
10
OUTC
IN 3B
10
OUTC
IN 4
10
IN 6
NC
IN 1B
OUTB
OUTA
OUTB
OUTA
NC
IN 5
VSS
NC
VSS
IN 3A
VSS
IN 3A
VSS
NC
MC14081B
Quad 2Input AND Gate
MC14082B
Dual 4Input AND Gate
IN 1A
14
VDD
OUTA
14
VDD
IN 2A
13
IN 2D
IN 1A
13
OUTB
OUTA
12
IN 1D
IN 2A
12
IN 4B
OUTB
11
OUTD
IN 3A
11
IN 3B
IN 1B
10
OUTC
IN 4A
10
IN 2B
IN 2B
IN 2C
NC
IN 1B
VSS
IN 1C
VSS
NC
NC = NO CONNECTION
MC14001B
67

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Per Gate, CL = 50 pF)
Sink
mAdc

Adc

where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MC14001B
68
BSERIES GATE SWITCHING TIMES

Characteristic
Symbol
Output Rise Time, All BSeries Gates

tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
Output Fall Time, All BSeries Gates

tTHL

MC14001B, MC14011B only
All Other 2, 3, and 4 Input Gates
8Input Gates (MC14068B, MC14078B)
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
tPLH, tPHL
ns
5.0
10
15
125
50
40
250
100
80
5.0
10
15
160
65
50
300
130
100
5.0
10
15
200
80
60
350
150
110
14
PULSE
GENERATOR
20 ns
VDD
20 ns
INPUT
INPUT
OUTPUT
CL
VSS
* All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.
VDD
90%
50%
10%
0V
tPHL
OUTPUT
INVERTING
tPLH
VOH
90%
50%
10%
tTHL
tPLH
OUTPUT
NONINVERTING
tTLH
tTLH
tPHL
90%
50%
10%
tTHL
VOL
VOH
VOL
MC14001B
69
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
VDD
14
VDD
1, 6, 8, 13
*
2, 5, 9, 12
3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown
VSS
VDD
VSS
1, 3, 11
* Inverter omitted in MC14001B
2, 4, 12
14
VDD
MC14002B, MC14072B
One of Two Gates Shown
VSS
9, 6, 10
VDD
VDD
3, 9
8, 5, 13
2, 10
14
VDD
VSS
1, 13
VSS
5, 11
4, 12
VSS
SAME AS
ABOVE
7
VSS

VDD
2
MC14078B
Eight Input Gate
14
4
5
MC14001B
610
VDD
VSS
SAME AS
ABOVE
9
10
SAME AS
ABOVE
11
12
SAME AS
ABOVE
13
VSS
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14011B, MC14081B
One of Four Gates Shown
14
VDD
MC14023B, MC14073B
One of Three Gates Shown
3, 4, 10, 11
VDD
2, 5, 9, 12
1, 6, 8, 13
7 VSS
2, 4, 12
1, 3, 11
14
VSS
VDD
VDD
9, 6, 10
MC14012B, MC14082B
One of Two Gates Shown
8, 5, 13
7
VSS
VDD
VSS
14
VDD
MC14068B
Eight Input Gate
VDD
2, 10
*
3, 9
VSS
VDD
4, 12
5, 11
1, 13
SAME AS
ABOVE
2
VSS
3
VSS
5
4
SAME AS
ABOVE
14
VDD
VSS
9
10
SAME AS
ABOVE
11
12
SAME AS
ABOVE
VDD
13
7 VSS
VSS
MC14001B
611
TYPICAL BSERIES GATE CHARACTERISTICS

NCHANNEL DRAIN CURRENT
(SINK)
PCHANNEL DRAIN CURRENT

(SOURCE)
10
5.0
ID , DRAIN CURRENT (mA)
9.0
4.0
TA = 55C
3.0
40C
+ 85C + 25C
2.0
+ 125C
1.0
8.0
TA = 55C
7.0
40C
6.0
5.0
+ 25C
+ 85C
4.0
+ 125C
3.0
2.0
1.0
1.0
2.0
3.0
4.0
VDS, DRAINTOSOURCE VOLTAGE (Vdc)
5.0
Figure 2. VGS = 5.0 Vdc

50
45
TA = 55C
16
14
40C
12
+ 25C
+ 85C
10
18
+ 125C
8.0
6.0
40
35
30
+ 85C
15
2.0
5.0
1.0
2.0 3.0 4.0 5.0

6.0
7.0 8.0
9.0
10
40C
+ 25C
20
10
TA = 55C
25
4.0
+ 125C
Figure 4. VGS = 10 Vdc

100
45
90
40
80
35
TA = 55C
30
40C
25
+ 25C
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10

50
+ 85C
20
+ 125C
15
10
5.0
0
5.0
Figure 3. VGS = 5.0 Vdc
20
1.0
2.0
3.0
4.0
70
60
TA = 55C
50
40C
+ 25C
40
+ 85C
30
+ 125C
20
10
2.0
4.0 6.0 8.0 10

12
14
16
18
20
2.0 4.0 6.0 8.0 10 12 14 16

18 20
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
MC14001B
612
TYPICAL BSERIES GATE CHARACTERISTICS (contd)
V out , OUTPUT VOLTAGE (Vdc)
VOLTAGE TRANSFER CHARACTERISTICS

5.0
4.0

3.0
2.0
1.0
0
1.0
2.0

10
8.0

6.0
4.0
2.0
0
3.0
4.0
5.0
2.0
Figure 8. VDD = 5.0 Vdc
6.0
8.0
10
Figure 9. VDD = 10 Vdc
DC NOISE MARGIN
16
14
12

10
8.0
6.0
4.0
2.0
0
4.0
2.0
4.0
The DC noise margin is defined as the input voltage range

from an ideal 1 or 0 input level which does not produce
output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the 1 and
0 levels =
1.0 V with a 5.0 V supply
6.0
8.0
10
Figure 10. VDD = 15 Vdc
VDD
Vout
VDD
Vout
VO
VO
VO
VO
VDD
VDD
Vin
0
VIL
Vin
0
VIL
VIH
VIH
VSS = 0 VOLTS DC
(a) Inverting Function
(b) NonInverting Function
Figure 11. DC Noise Immunity
MC14001B
613
MOTOROLA
MC14001UB
UB-Suffix Series CMOS Gates

The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
nonbuffered functions.
Linear and Oscillator Applications
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
PinforPin Replacements for Corresponding CD4000 Series UB Suffix
Devices
Quad 2-Input NOR Gate
MC14002UB
Dual 4-Input NOR Gate
MC14011UB
Quad 2-Input NAND Gate
MC14012UB
Dual 4-Input NAND Gate
MC14023UB
Triple 3-Input NAND Gate
MC14025UB
Triple 3-Input NOR Gate
LOGIC DIAGRAMS
MC14001UB
Quad 2Input
NOR Gate
1
2
5
6
8
9
12
13
MC14002UB
Dual 4Input
NOR Gate
3
4
10
11
MC14011UB
Quad 2Input
NAND Gate
1
2
3
4
13
NC = 6, 8
MC14012UB
Dual 4Input
NAND Gate
13
NC = 6, 8
5
11
12
10
13
10
P SUFFIX
PLASTIC
CASE 646
11
13
D SUFFIX
SOIC
CASE 751A
MC14025UB
Triple 3Input
NOR Gate
2
8
3
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
MC14001UB
614
9
12
MC14023UB
Triple 3Input
NAND Gate
1
2
3
4
5
9
10
11
12
2
5
6
8
5
9
10
11
12
L SUFFIX
CERAMIC
CASE 632
1
2
8
3
4
5
11
12
13
9
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
10
This device contains protection circuitry to

guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
PIN ASSIGNMENTS
MC14001UB
MC14002UB
IN 1A
14
VDD
OUTA
14
VDD
MC14011UB
IN 1A
14
VDD
IN 2A
13
IN 2D
IN 1A
13
OUTB
IN 2A
13
IN 2D
OUTA
12
IN 1D
IN 2A
12
IN 4B
OUTA
12
IN 1D
OUTB
11
OUTD
IN 3A
11
IN 3B
OUTB
11
OUTD
IN 1B
10
OUTC
IN 4A
10
IN 2B
IN 1B
10
OUTC
IN 2B
IN 2C
NC
IN 1B
IN 2B
IN 2C
VSS
IN 1C
VSS
NC
VSS
IN 1C
MC14012UB
MC14023UB
MC14025UB
OUTA
14
VDD
IN 1A
14
VDD
IN 1A
14
VDD
IN 1A
13
OUTB
IN 2A
13
IN 3C
IN 2A
13
IN 3C
IN 2A
12
IN 4B
IN 1B
12
IN 2C
IN 1B
12
IN 2C
IN 3A
11
IN 3B
IN 2B
11
IN 1C
IN 2B
11
IN 1C
IN 4A
10
IN 2B
IN 3B
10
OUTC
IN 3B
10
OUTC
NC
IN 1B
OUTB
OUTA
OUTB
OUTA
VSS
NC
VSS
IN 3A
VSS
IN 3A
NC = NO CONNECTION

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
MC14001UB
615

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
1 Level
IIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Per Gate CL = 50 pF)
Sink
Vdc
mAdc

Adc

where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MC14001UB
616

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

VDD
Vdc
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
90
50
40
180
100
80
Unit
ns
ns
tPLH, tPHL
ns
20 ns
VDD
INPUT
14
PULSE
GENERATOR
INPUT
20 ns
VDD
90%
50%
10%
OUTPUT
0V
tPHL
*
CL
7
tPLH
VSS
* All unused inputs of AND, NAND gates must be

connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.
VOH
90%
50%
10%
OUTPUT
INVERTING
tTHL
VOL
tTLH
MC14001UB CIRCUIT SCHEMATIC
VDD
14

(1/2 of Device Shown)
VDD
10
14
2, 9
3, 10
4, 11
5, 12
1, 13
13
12
7
VSS
VSS
11
MC14001UB
617



14 VDD
14 VDD
14 VDD
1, 13
3, 4, 10, 11
1, 6, 8, 13
2, 9
2, 5, 9, 12
3, 10
6, 9, 10
5, 1, 11
4, 11
7 VSS
4, 2, 12
5, 12
3, 8, 13
7 VSS
1, 3, 11
2, 4, 12
8, 5, 13
9, 6, 10
12
10
8.0
8.0
b
6.0
5.0 Vdc
4.0
b
a
6.0
15 Vdc
b a
a
4.0
10 Vdc
2.0
7 VSS
2.0
0
0
2.0 4.0 6.0 8.0 10 12 14 16
2.0
4.0
a TA = 55C
b TA = + 25C
c TA = + 125C
c
10 Vdc
8.0
a TA = + 125C
b TA = 55C
8.0
a
6.0
5.0 Vdc
4.0
a b
2.0 4.0 6.0 8.0 10 12 14 16

Figure 3. Typical Voltage Transfer

Characteristics versus
Temperature
6.0
10 Vdc
10
10
c
b
I D, DRAIN CURRENT (mAdc)
VGS = 5.0 Vdc
12
2.0
Figure 2. Typical Voltage and

Current Transfer Characteristics
VDD = 15 Vdc Unused input

connected to
b
VSS.
a
14
14
14 VDD
16
VDD = 15 Vdc TA = + 25C

Unused input
connected to
VSS.
a One input only
10 Vdc
b Both inputs
16

7 VSS
b
c
15 Vdc
8.0
15 Vdc
b
a
VGS = 10 Vdc
b
c
6.0
a TA = 55C
b TA = + 25C
c TA = + 125C
4.0
a
2.0
5.0 Vdc
c
10
10
a
8.0
6.0
4.0
VDS, DRAIN VOLTAGE (Vdc)
a
2.0
Figure 4. Typical Output Source

Characteristics
MC14001UB
618
0
0
2.0
4.0
6.0
8.0
10
Figure 5. Typical Output Sink

Characteristics
MOTOROLA
MC14006B
18-Bit Static Shift Register
L SUFFIX
CERAMIC
CASE 632
The MC14006B shift register is comprised of four separate shift register

sections sharing a common clock: two sections have four stages, and two
sections have five stages with an output tap on both the fourth and fifth
stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12,
13, 14, 16, 17, or 18 bits by appropriate selection of inputs and outputs. This
part is particularly useful in serial shift registers and time delay circuits.
P SUFFIX
PLASTIC
CASE 646
Output Transitions Occur on the Falling Edge of the Clock Pulse

Fully Static Operation
Can be Cascaded to Provide Longer Shift Register Lengths
PinforPin Replacement for CD4006B
D SUFFIX
SOIC
CASE 751A

Symbol
VDD
Vin, Vout
lin, lout
PD
Tstg
TL
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA

Storage Temperature
500
mW
65 to + 150
_C
260
_C
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TRUTH TABLE
(Single Stage)
Dn
Qn+1
0
1
x
X = Dont Care
0
1
Qn
BLOCK DIAGRAM
1
13
DP1
Q4
VDD = PIN 14
VSS = PIN 7
NC = PIN 2
11
DP5
4
STAGES
C
4
STAGES
C
12
Q8
Q9
10
DP10 Q13
1
STAGE
C
4
STAGES
C
8
DP14
Q17
4
STAGES
C
Q18
D
1
STAGE
C
CLOCK 3
LOGIC DIAGRAM
(ONE REGISTER STAGE)
C
#
*
DATA
* Transmission Gate
(C)
1
IN
OUT
D+1
C
#Inverter used only on the first stage of

each fourstage element.
Input to output is
(A) A bidirectional low impedance when control input 1 is low and control input 2 is high.
(B) An open circuit when control input 1 is high and control input 2 is low.
2
(C)
MC14006B
619

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
(VO = 0.5 or 4.5 Vdc) 1 Level

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (1.3 A/kHz) f + IDD

Adc
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
DP1
14
VDD
NC
13
Q4
12
Q9
DP5
11
Q8
DP10
10
Q13
DP14
Q18
VSS
Q17
NC = NO CONNECTION
MC14006B
620

Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
300
110
80
600
220
160
5.0
10
15
200
120
80
100
60
40
fcl
5.0
10
15
5.0
8.3
12
2.5
4.2
6.0
MHz
tTLH
tTHL
5.0
10
15
15
5
4
Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH,
tTHL

tPLH
tPHL
Clock Pulse Width
tWH
Clock Pulse Frequency
Clock Pulse Rise and Fall Time**
Unit
ns
ns
ns
Setup Time
tsu
5.0
10
15
0
0
0
50
15
8.0
ns
Hold Time
th
5.0
10
15
180
90
75
75
25
20
ns
** When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
** of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.
be left open.
VDD = VGS
Vout
VDD = VGS
14
14
CLOCK Q4
Q8
DP1
Q9
DP5 Q13
DP10 Q17
DP14 Q18
7
VSS
Vout
IOH
EXTERNAL
POWER
SUPPLY
Figure 1. Typical Output Source Current

Characteristics Test Circuit
CLOCK Q4
Q8
DP1
Q9
DP5 Q13
DP10 Q17
DP14 Q18
VSS
IOL
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Output Sink Current

MC14006B
621
VDD
14
PULSE
GENERATOR
CLOCK Q4
Q8
DP1
Q9
DP5 Q13
DP10 Q17
DP14 Q18
CL
14
TEST
VSS CL
7
50
F
CL
CL
CL
CL
PRESET
1/3 MC14000
OR EQUIV
ID
1
f
CLOCK
50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveforms
VDD
14
PULSE
GENERATOR 1
CLOCK Q4
Q8
DP1
Q9
DP5
Q13
DP10 Q17
DP14 Q18
PULSE
GENERATOR 2
20 ns
20 ns
tWL
VSS
CL
CL
th 1
tsu 1
DATA
tWH
VDD
90%
50%
10%
VSS
th 0
tsu 0
VDD
5STAGE
OUTPUT
Q9, Q18
CL
CL
90%
50%
10%
CLOCK
4STAGE
OUTPUT
Q4, Q8
Q13, Q17
CL
CL
20 ns
20 ns
tPLH
tTLH
VSS
tPHL
VOH
90%
50%
10%
tTLH
VOL
tTHL
tPHL
90%
50%
10%
VOH
tTHL
VOL
Output state can change since data previously clocked in might be in either state.
MC14006B
622
MOTOROLA
MC14007UB
Dual Complementary Pair
Plus Inverter
L SUFFIX
CERAMIC
CASE 632
The MC14007UB multipurpose device consists of three Nchannel and

three Pchannel enhancement mode devices packaged to provide access to
each device. These versatile parts are useful in inverter circuits, pulse
shapers, linear amplifiers, high input impedance amplifiers, threshold
detectors, transmission gating, and functional gating.
P SUFFIX
PLASTIC
CASE 646

PinforPin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
D SUFFIX
SOIC
CASE 751A
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Plastic
Ceramic
SOIC
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
DPB
14
VDD
Tstg
Storage Temperature
65 to + 150
_C
SPB
13
DPA
260
_C
GATEB
12
OUTC
SNB
11
SPC
DNB
10
GATEC
GATEA
SNC
VSS
DNA
TL
PIN ASSIGNMENT
A
A
12
1
C
INPUT
1
0
Substrates of Pchannel devices internally

connected to VDD; substrates of Nchannel
devices internally connected to VSS.
11
12
13
INPUT
A = C, B = OPEN
A = B, C = OPEN
13
C
11
INPUT OUTPUT CONDITION
SCHEMATIC
14
VDD
14
D = DRAIN
S = SOURCE
10
VSS
3
4
5
VDD = PIN 14
VSS = PIN 7
10
Figure 1. Typical Application: 2Input Analog Multiplexer
MC14007UB
623

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
5.0
1.0
2.5
10
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
1.0
2.5
10
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
1 Level
VIH
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Per Gate) (CL = 50 pF)
Sink
Vdc
mAdc
IT = (0.7 A/kHz) f + IDD/6

IT = (1.4 A/kHz) f + IDD/6
IT = (2.2 A/kHz) f + IDD/6
Adc
be left open.
MC14007UB
624

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL
TurnOff Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns
tPLH = (0.15 ns/pF) CL + 17.5 ns
tPLH
TurnOn Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns
tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
90
45
35
180
90
70
5.0
10
15
75
40
30
150
80
60
5.0
10
15
60
30
25
125
75
55
5.0
10
15
60
30
25
125
75
55
Unit
ns
ns
ns
ns
* The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
VDD = VGS
VDD = VGS
14
IOH
7
14
VDS = VOH VDD
IOL
VSS
All unused inputs connected to ground.
VGS = 5.0 Vdc

8.0
b
a
c
12
b
10 Vdc
16
15 Vdc
a
a
20
10
VGS = 15 Vdc
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)
20
a TA = 55C
b TA = + 25C
c TA = + 125C
VSS
All unused inputs connected to ground.
4.0
VDS = VOL
16
a
10 Vdc
12
b
c
a TA = 55C
b TA = + 25C
c TA = + 125C
8.0
a
4.0
b 5.0 Vdc
c
0
8.0
6.0
4.0
2.0
Figure 2. Typical Output Source Characteristics
2.0
4.0
6.0
8.0
10
Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
MC14007UB
625
VDD
500 F
0.01 F
CERAMIC
ID
VDD
VSS
tPHL
Vout
20 ns
90%
50%
10%
Vin
14
Vin
PULSE
GENERATOR
20 ns
VOH
90%
50%
10%
Vout
CL
VSS
tPLH
VOL
tTHL
tTLH
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
The MC14007UB dual pair plus inverter, which has access
to all its elements offers a number of unique circuit applications. Figures 1, 5, and 6 are a few examples of the device
flexibility.
VDD
14
OUT = A+BC
13
+ VDD
2
11
DISABLE 3
10
12
1
8
OUTPUT
11
9
INPUT 10
12 OUTPUT
3
C
9
8
6
A
DISABLE 6
7
INPUT
DISABLE
OUTPUT
1
0
X
0
0
1
0
1
OPEN
Substrates of Pchannel devices internally connected to VDD;

Substrates of Nchannel devices internally connected to VSS.
Figure 6. AOI Functions Using Tree Logic
X = Dont Care
Figure 5. 3State Buffer
MC14007UB
626
MOTOROLA
MC14008B
4-Bit Full Adder
L SUFFIX
CERAMIC
CASE 620
The MC14008B 4bit full adder is constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic structure. This
device consists of four full adders with fast internal lookahead carry output.
It is useful in binary addition and other arithmetic applications. The fast
parallel carry output bit allows highspeed operation when used with other
adders in a system.
P SUFFIX
PLASTIC
CASE 648
LookAhead Carry Output

D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
260
_C
BLOCK DIAGRAM
HIGHSPEED
PARALLEL CARRY
B4 15
A4
14 Cout
ADDER
4
13 S4
C4
B3
A3
B2
A2
B1
A1
Cin
ADDER
3
12 S3
C3
ADDER
2
11 S2
Plastic
Ceramic
SOIC
TRUTH TABLE
(One Stage)
Cin
Cout
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
PIN ASSIGNMENT
A4
16
VDD
B3
15
B4
A3
14
Cout
B2
13
S4
A2
12
S3
B1
11
S2
A1
10
S1
VSS
Cin
C2
ADDER
1
10 S1
VDD = PIN 16
VSS = PIN 8
MC14008B
627

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc
be left open.
MC14008B
628

Characteristic
Symbol

tTLH,
tTHL

Sum in to Sum Out
Sum In to Carry Out
Carry In to Sum Out
Carry In to Carry Out
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
tPLH, tPHL
ns
5.0
10
15
400
160
115
800
320
230
5.0
10
15
305
145
110
610
290
220
5.0
10
15
375
155
115
750
310
230
5.0
10
15
170
75
55
340
150
110
VDD = VGS
VDD = VGS
Vout
16
16
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
S3
S2
IOH
Cout
VSS
EXTERNAL
POWER
SUPPLY
Figure 1. Typical Source Current

Vout
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
S3
S2
IOL
Cout
VSS
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Sink Current

MC14008B
629
VDD
16
20 ns
Vin
20 ns
90%
10%
VDD
VSS
PULSE
GENERATOR
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
Cout
VSS
S3
S2
CL
CL
CL
CL
CL
IDD
500 F
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD
16
B4
A4
B3
A3
B2
A2
B1
A1
PULSE
GENERATOR
Cin
8
S4
S3
S2
CL
S1
CL
CL
Cout
CL
CL
VSS
IDD
20 ns
Cin
20 ns
VDD
90%
50%
10%
VSS
tPHL
90%
50%
10%
S1 S4
tPLH
VOH
VOL
tTHL
tTLH
VOH
Cout
50%
VOL
tPLH
tPHL
MC14008B
630
Cout
B4
S4
A4
B3
S3
A3
B2
S2
A2
B1
S1
A1
Cin
Figure 5. Logic Diagram
MC14008B
631
TYPICAL APPLICATION
WORD A + B INPUTS
A1
B4
CHIP
1
Cin
S1
Cout
S4
A1
Cin
S1
B4
CHIP
2
Cout
S4
A1
Cin
S1
B4
CHIP
3
Cout
S4
A1
Cin
B4
CHIP
4
S1
Cout
S4
SUM OUTPUTS
Calculation of 16bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16bit adder speed at 10 V, 25C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16Bit Adder Configuration
MC14008B
632
MOTOROLA
MC14013B
Dual Type D Flip-Flop
L SUFFIX
CERAMIC
CASE 632
The MC14013B dual type D flipflop is constructed with MOS Pchannel

and Nchannel enhancement mode devices in a single monolithic structure.
Each flipflop has independent Data, (D), Direct Set, (S), Direct Reset, (R),
and Clock (C) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flipflops for counter and
toggle applications.
P SUFFIX
PLASTIC
CASE 646
Static Operation
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positivegoing edge
of the clock pulse

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
D SUFFIX
SOIC
CASE 751A
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
BLOCK DIAGRAM
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
TRUTH TABLE
Inputs
Clock
Plastic
Ceramic
SOIC
13
12
4
8
9
11
Outputs
Data
Reset
Set
10
No
Change
VDD = PIN 14
VSS = PIN 7
X = Dont Care
= Level Change
MC14013B
633

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

MC14013B
634
PIN ASSIGNMENT
QA
14
VDD
QA
13
QB
CA
12
QB
RA
11
CB
DA
10
RB
SA
DB
VSS
SB

Characteristic
Symbol

tTLH,
tTHL

Clock to Q, Q
tPLH
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
175
75
50
350
150
100
Set to Q, Q
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
5.0
10
15
225
100
75
450
200
150
Setup Times**
tsu
5.0
10
15
40
20
15
20
10
7.5
ns
Hold Times**
th
5.0
10
15
40
20
15
20
10
7.5
ns
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
fcl
5.0
10
15
4.0
10
14
2.0
5.0
7.0
MHz
tTLH
tTHL
5.0
10
15
15
5.0
4.0
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
5
10
15
80
45
35
0
5
5
5
10
15
50
30
25
35
10
5
Clock Pulse Width
Clock Pulse Rise and Fall Time
Set and Reset Pulse Width
trem
Removal Times
Set
Reset
ns
** Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM
S
C
D
C
C
C
C
C
MC14013B
635
20 ns
20 ns
90%
50%
10%
tsu (L)
th
tsu (H)
C
tWH
SET OR
RESET
20 ns
VDD
90%
50%
tw
VSS
10%
tPHL
VSS
20 ns
90%
50%
tw
tPLH
tPHL
VOH
10%
VDD
VSS
VOH
50%
Q OR Q
VOL
tTLH
trem
20 ns
CLOCK
90%
50%
10%
20 ns
VSS
20 ns
VDD
90%
50%
10%
tWL
1
fcl
tPLH
VDD
VOL
tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms

(Data, Clock, and Output)

(Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
nSTAGE SHIFT REGISTER
1
D
nth
CLOCK
BINARY RIPPLE UPCOUNTER (Divideby2n)

1
CLOCK
nth
T FLIPFLOP
MODIFIED RING COUNTER (Divideby(n+1))

1
nth
CLOCK
MC14013B
636
MOTOROLA
MC14014B
MC14021B

The MC14014B and MC14021B 8bit static shift registers are constructed
with MOS Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. These shift registers find primary use in parallelto
serial data conversion, synchronous and asynchronous parallel input, serial
output data queueing; and other general purpose register applications
requiring low power and/or high noise immunity.
L SUFFIX
CERAMIC
CASE 620
Synchronous Parallel Input/Serial Output (MC14014B)

Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
Q Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
MC14014B PinforPin Replacement for CD4014B
MC14021B PinforPin Replacement for CD4021B
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
TRUTH TABLE
SERIAL OPERATION:
t
Clock DS P/S
0
0
1
0
0
0
1
0
n
n+1
n+2
n+3
P2
7
P3
6
Q7
t=n+7
Q8
t=n+8
0
1
0
1
?
0
1
0
?
?
0
1
Q6
Q7
Q8
Clock
MC14014B MC14021B DS
X
X
X
P/S
Pn
0
*Qn
1
1
* Q6, Q7, & Q8 are available externally

X = Dont Care
LOGIC DIAGRAM
P1
Q6
t=n+6
PARALLEL OPERATION:
Plastic
Ceramic
SOIC
P6
5
P7
14
P8
15
P/S
11
DS
D
C
10
CLOCK
VDD = PIN 16
VSS = PIN 8
P4 = PIN 4
P5 = PIN 13
2
Q6
12
Q7
3
Q8
MC14014B MC14021B
637

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
15
0.005
0.010
0.015
5.0
10
15
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc

MC14014B MC14021B
638
PIN ASSIGNMENT
P8
16
VDD
Q6
15
P7
Q8
14
P6
P4
13
P5
P3
12
Q7
P2
11
DS
P1
10
VSS
P/S
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
400
170
115
800
340
230
Unit
ns

tTLH,
tTHL
Propagation Delay Time (Clock to Q, P/S to Q)

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPLH,
tPHL
Clock Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
ns
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
tWH
5.0
10
15
400
175
135
150
75
40
ns
Setup Time
P/S to Clock
tsu
5.0
10
15
200
100
80
100
50
40
ns
Hold Time
Clock to P/S
th
5.0
10
15
20
20
25
2.5
10
0
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
tsu
5.0
10
15
350
80
60
150
50
30
ns
Hold Time
Clock to Ds
th
5.0
10
15
45
35
35
0
0
5
ns
Hold Time
Clock to Pn
th
5.0
10
15
50
45
45
25
20
20
ns
tr(cl)
5.0
10
15
15
5
4
Clock Frequency
Parallel/Serial Control Pulse Width
Input Clock Rise Time
ns
VDD
PULSE
GENERATOR
P/S
C
P6
P7
P8
DS
Vout
Q6
PULSE
GENERATOR
Q7
Q8
VDD
IOH
EXTERNAL
POWER
SUPPLY
P/S
C
P6
P7
P8
DS
Vout
Q6
Q7
Q8
IOL
EXTERNAL
POWER
SUPPLY
Preset output under test to a logic 1 level.
Figure 1. Output Source Current Test Circuit
Figure 2. Output Sink Current Test Circuit
MC14014B MC14021B
639
VDD
500 F
ID
0.01 F
CERAMIC
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
PULSE
GENERATOR 1
PULSE
GENERATOR 2
Q6
CL
Q7
CL
Q8
VSS
CL
1
f
CLOCK
50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
SW 1
VDD
1
PULSE
GENERATOR 1
PULSE
GENERATOR 2
2
1
2
1
SWITCH POSITION 1 = PARALLEL IN

SWITCH POSITION 2 = SERIAL IN
VDD
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
20 ns
PARALLEL OR
SERIAL DATA
INPUT
Q6
90%
50%
10%
tsu
tWH
Q7
90%
50%
10%
tWH
tPLH
90%
50%
10%
CL
VSS
VSS
tTHL
CLOCK OR P/S
INPUT
Q8
20 ns
VDD
Q
OUTPUT
SW 2
tTLH
VDD
VSS
tWL
tPHL
VOH
VOL
tTHL
tWL = tWH = 50% DUTY CYCLE
MC14014B MC14021B
640
MOTOROLA
MC14015B
Dual 4-Bit Static Shift Register
L SUFFIX
CERAMIC
CASE 620
The MC14015B dual 4bit static shift register is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. It consists of two identical, independent 4state
serialinput/paralleloutput registers. Each register has independent Clock
and Reset inputs with a single serial Data input. The register states are type
D masterslave flipflops. Data is shifted from one stage to the next during
the positivegoing clock transition. Each register can be cleared when a high
level is applied on the Reset line. These complementary MOS shift registers
find primary use in buffer storage and serialtoparallel conversion where
low power dissipation and/or noise immunity is desired.
information is transferred to the output only on the positive going edge
of the clock pulse.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
BLOCK DIAGRAM
7
Q0
Q1
Q2
C
R Q3
10
Q0
13
Q1
12
Q2
11
6
15
C
R Q3
TRUTH TABLE
C
14
Q0
Qn
Qn1
Qn1
No Change
No Change
VDD = PIN 16
VSS = PIN 8
X = Dont Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn1 = Output of prior stage.
MC14015B
641

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or .05 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc
IT = (1.2 A/kHz)f + IDD

Adc

MC14015B
642
PIN ASSIGNMENT
CB
16
VDD
Q3B
15
DB
Q2A
14
RB
Q1A
13
Q0B
Q0A
12
Q1B
RA
11
Q2B
DA
10
Q3A
VSS
CA

Characteristic
Symbol

tTLH,
tTHL

Clock, Data to Q
Reset to Q
tPLH,
tPHL
Clock Pulse Width
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
310
125
90
750
250
170
5.0
10
15
460
180
120
750
250
170
tWH
5.0
10
15
400
175
135
185
85
55
ns
fcl
5.0
10
15
2.0
6.0
7.5
1.5
3.0
3.75
MHz
tTLH, tTHL
5.0
10
15
15
5
4
tWH
5.0
10
15
400
160
120
200
80
60
ns
tsu
5.0
10
15
350
100
75
100
50
40
ns
Clock Pulse Rise and Fall Times
VDD
Reset Pulse Width
Setup Time
* The formulas given are for typical characteristics only at 25_C.

VDD
PULSE
GENERATOR
2
500 F
D
PULSE
GENERATOR
1
0.01 F
CERAMIC
ID
C
R
VDD
Q0
Q1
Q2
Q3
CL
CL
CL
CL
VSS
1
f
CLOCK
50%
DATA
MC14015B
643
tTLH
DATA
INPUT
tTHL
VDD
90%
50%
10%
0V
tsu
PULSE
GENERATOR
2
VDD
D
Q0
PULSE
GENERATOR
1
CL
Q2
C
R
CLOCK
INPUT
CL
Q1
SYNC
tTLH
tWH
tPLH
CL
Q3
CL
tTHL
90%
50%
10%
tWL
Q0
tWL = tWH = 50% Duty Cycle
tTLH = tTHL 20 ns
0V
tPHL
90%
VSS
VDD
tTLH
50%
10%
tTHL
Figure 2. Switching Test Circuit and Waveforms
PULSE
GENERATOR
2
VDD
D
CL
Q1
SYNC
PULSE
GENERATOR
1
Q0
0V
tsu
CL
Q3
CL
VSS
VDD
50%
CL
Q2
C
R
CLOCK
INPUT
th
DATA
INPUT
50%
VDD
0V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
MC14015B
644
SINGLE BIT
VDD
RESET
CLOCK
TO D OF
NEXT BIT
VSS
DATA INPUT BUFFER
RESET INPUT BUFFER
DATA TO
FIRST BIT
MC14015B
645
VSS
VDD
VDD
VDD
DATA
IN
CLOCK INPUT BUFFER
RESET
TO 4 BITS
RESET
IN
VSS
CLOCK
TO 4 BITS
CLOCK
IN
VSS
CIRCUIT SCHEMATICS
DATA
IN
LOGIC DIAGRAMS
SINGLE BIT
C
TO D OF
NEXT BIT
DATA
C
RESET
C
C
C
COMPLETE DEVICE
5
4
Q0
3
Q1
10
Q2
Q3
DATA INPUT BUFFER

D
D
CLOCK INPUT BUFFER
Q
R
9
R
6
13
RESET INPUT BUFFER
12
Q0
11
Q1
2
Q2
Q3
DATA INPUT BUFFER

D
D
15
CLOCK INPUT BUFFER
C
Q
R
1
VDD = PIN 16
VSS = PIN 8
R
14
RESET INPUT BUFFER
MC14015B
646
MOTOROLA

MC14016B
Quad Analog Switch/Quad
Multiplexer
L SUFFIX
CERAMIC
CASE 632
The MC14016B quad bilateral switch is constructed with MOS Pchannel

Each MC14016B consists of four independent switches capable of
controlling either digital or analog signals. The quad bilateral switch is used
in signal gating, chopper, modulator, demodulator and CMOS logic
implementation.
P SUFFIX
PLASTIC
CASE 646

Linearized Transfer Characteristics
Low Noise 12 nV/Cycle, f 1.0 kHz typical
PinforPin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
For Lower RON, Use The HC4016 HighSpeed CMOS Device or The
MC14066B
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.
D SUFFIX
SOIC
CASE 751A
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Vin, Vout
lin
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
Input Current (DC or Transient),

per Control Pin
10
mA
Isw
PD
Switch Through Current
25
mA
Tstg
TL
Storage Temperature
500
mW
65 to + 150
_C
260
_C
BLOCK DIAGRAM
CONTROL 1
IN 1
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4

LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
13
2
OUT 1
1
5
3
OUT 2
4
6
9
OUT 3
8
12
10
OUT 4
11
VDD = PIN 14
VSS = PIN 7
Control
Switch
0 = VSS
Off
1 = VDD
On
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS
VSS Vin VDD
VSS Vout VDD
IN
MC14016B
647

Characteristic
Input Voltage
Control Input
Min
Typ #
Max
Min
Max
Unit
VIL
5.0
10
15
1.5
1.5
1.5
0.9
0.9
0.9
Vdc
VIH
5.0
10
15
3.0
8.0
13
2.0
6.0
11
Vdc
15
0.1
0.00001
0.1
1.0
Adc
5.0
5.0
5.0
0.2
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
5.0
600
600
600
300
300
280
660
660
660
840
840
840
7.5
360
360
360
240
240
180
400
400
400
520
520
520
10
600
600
600
260
310
310
660
660
660
840
840
840
15
360
360
360
260
260
300
400
400
400
520
520
520
Iin
Input Capacitance
Control
Switch Input
Switch Output
Feed Through
Cin
Quiescent Current
(Per Package)
2,3
IDD
4,5,6
RON
(Vin = + 7.5 Vdc)

(Vin = 7.5 Vdc) VSS = 7.5 Vdc
(Vin = 0.25 Vdc)
(Vin = + 10 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 5.6 Vdc)
(Vin = + 15 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 9.3 Vdc)
Input/Output Leakage Current

(VC = VSS)
(Vin = + 7.5, Vout = 7.5 Vdc)
(Vin = 7.5, Vout = + 7.5 Vdc)
125_C
Max
ON Resistance
Between any 2 circuits in a common
package
(VC = VDD)
(Vin = 5.0 Vdc, VSS = 5.0 Vdc)
(Vin = 7.5 Vdc, VSS = 7.5 Vdc)
25_C
Min
Symbol
Input Current Control
ON Resistance
(VC = VDD, RL = 10 k)
(Vin = + 5.0 Vdc)
(Vin = 5.0 Vdc) VSS = 5.0 Vdc
(Vin = 0.25 Vdc)
55_C
VDD
Vdc
Figure
pF
Adc
Ohms
RON
Ohms
5.0
7.5
15
10
Adc
7.5
7.5
0.1
0.1
0.0015
0.0015
0.1
0.1
1.0
1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
** For voltage drops across the switch (V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
MC14016B
648
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic
VDD
Vdc
Min
Typ #
Max
Unit
tPLH,
tPHL
5.0
10
15
15
7.0
6.0
45
15
12
ns
tPHZ,
tPLZ,
tPZH,
tPZL
5.0
10
15
34
20
15
90
45
35
5.0
10
15
30
50
100
mV
5.0
80
dB
10,11
5.0
10
15
24
25
30
nV/Cycle
5.0
10
15
12
12
15
0.16
Figure
Symbol
Propagation Delay Time (VSS = 0 Vdc)

Vin to Vout
(VC = VDD, RL = 10 k)
Control to Output
(Vin
10 Vdc, RL = 10 k)
Crosstalk, Control to Output (VSS = 0 Vdc)

(VC = VDD, Rin = 10 k, Rout = 10 k,
f = 1.0 kHz)
Crosstalk between any two switches (VSS = 0 Vdc)

(RL = 1.0 k, f = 1.0 MHz,
V
crosstalk
20 log10 out1)
Vout2
Noise Voltage (VSS = 0 Vdc)
(VC = VDD, f = 100 Hz)
(VC = VDD, f = 100 kHz)
ns
Second Harmonic Distortion (VSS = 5.0 Vdc)

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)
5.0
Insertion Loss (VC = VDD, Vin = 1.77 Vdc,

VSS = 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
V
Iloss
20 log10 out)
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
12
5.0
Bandwidth ( 3.0 dB)

(VC = VDD, Vin = 1.77 Vdc, VSS = 5.0 Vdc,
RMS centered @ 0.0 Vdc)
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
dB
12,13
BW
2.3
0.2
0.1
0.05
5.0
MHz
OFF Channel Feedthrough Attenuation

(VSS = 5.0 Vdc)
Vout
50 dB)
(VC = VSS, 20 log10
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
54
40
38
37
5.0
kHz
1250
140
18
2.0
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
CONTROL 1
OUT 2
12
CONTROL 4
IN 2
11
IN 4
CONTROL 2
10
OUT 4
CONTROL 3
OUT 3
VSS
IN 3
MC14016B
649
VC
IS
Vin
Vout
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
PD , POWER DISSIPATION (W)
VDD = 15 Vdc
VDD
ID
PULSE
GENERATOR
TO ALL
4 CIRCUITS
VDD
Vout
10 k
CONTROL
INPUT
fc
VSS
Vin
TA = 25C
5.0 Vdc
1000
100
10
1.0
5.0 k 10 k
PD = VDD x ID
10 Vdc
Figure 2. Quiescent Power Dissipation

Test Circuit
100 k
1.0 M
fc, FREQUENCY (Hz)
10 M
50 M
Figure 3. Typical Power Dissipation per Circuit

(1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE

700
RL = 10 k
TA = 25C
600
R ON, ON RESISTANCE (OHMS)
R ON, ON RESISTANCE (OHMS)
700
500
400
VC = VDD = 5.0 Vdc

VSS = 5.0 Vdc
300
200
100
0
10 8.0
VC = VDD = 7.5 Vdc

VSS = 7.5 Vdc
500
400
VC = VDD = 10 Vdc
300
200
VC = VDD = 15 Vdc
100
0
4.0
0
4.0
Figure 4. VSS = 5.0 V and 7.5 V
MC14016B
650
VSS = 0 Vdc
RL = 10 k
TA = 25C
600
8.0
10
2.0
6.0
10
14
18
20
Figure 5. VSS = 0 V
Vout
RL
CL
Vin
Vout
20 ns
RL
20 ns
90%
50%
Vin
VC
tPLH
Figure 6. RON Characteristics

Test Circuit
10%
tPHL
VSS
50%
Vout
Vin
VDD
Figure 7. Propagation Delay Test Circuit

and Waveforms
Vout
VC
RL
CL
VX
Vin
20 ns
50%
VC
10%
tPZL
10 k
VC
15 pF
Vin
tPLZ
1k
90%
Vout
Vout
VSS
tPHZ
Vin = VDD
90%
Vx = VSS
tPZH
Vout
VDD
90%
10%
10%
Vin = VSS
Vx = VDD
Figure 8. TurnOn Delay Time Test Circuit

and Waveforms
Figure 9. Crosstalk Test Circuit
35
OUT
VC = VDD
IN
QUANTECH
MODEL
2283
OR EQUIV
NOISE VOLTAGE (nV/ CYCLE)
30
VDD = 15 Vdc
25
10 Vdc
20
5.0 Vdc
15
10
5.0
0
10
Figure 10. Noise Voltage Test Circuit
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 11. Typical Noise Characteristics
MC14016B
651
2.0
TYPICAL INSERTION LOSS (dB)
RL = 1 M AND 100 k
0
10 k
2.0
1.0 k
4.0
3.0 dB (RL = 1.0 M )
6.0
3.0 dB (RL = 10 k )
Vout
8.0
10
Vin
12
10 k
100 k
1.0 M
10 M
fin, INPUT FREQUENCY (Hz)
RL
VC
3.0 dB (RL = 1.0 k )
100 M
Figure 12. Typical Insertion Loss/Bandwidth

Characteristics
+ 2.5 Vdc
0.0 Vdc
2.5 Vdc
Figure 13. Frequency Response Test Circuit
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. V Across Switch
MC14016B
652
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0to5 V
Digital Control signal is used to directly control a 5 V pp analog signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V logic high at
the control inputs; V SS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and V SS. The analog voltage must not swing higher than
V DD or lower than V SS.
The example shows a 5 V pp signal which allows no

margin at either peak. If voltage transients above V DD and/or
below V SS are anticipated on the analog channels, external
diodes (Dx) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
The absolute maximum potential difference between V DD
and VSS is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
V DD and V SS.
+5 V
VDD
+5 V
5 Vpp
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
VSS
SWITCH
IN
SWITCH
OUT
+ 5.0 V
5 Vpp
ANALOG SIGNAL
+ 2.5 V
0TO5 V DIGITAL
GND
CONTROL SIGNALS
MC14016B
Figure A. Application Example
VDD
VDD
Dx
Dx
SWITCH
IN
SWITCH
OUT
Dx
VSS
Dx
VSS
Figure B. External Germanium or Schottky Clipping Diodes
MC14016B
653
MOTOROLA
MC14017B
Decade Counter
L SUFFIX
CERAMIC
CASE 620
The MC14017B is a fivestage Johnson decade counter with builtin code

converter. High speed operation and spikefree outputs are obtained by use
of a Johnson decade counter design. The ten decoded outputs are normally
low, and go high only at their appropriate decimal time period. The output
changes occur on the positivegoing edge of the clock pulse. This part can
be used in frequency division applications as well as decade counter or
decimal decode display applications.

DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
DividebyN Counting
Triple Diode Protection on All Inputs
D SUFFIX
SOIC
CASE 751B

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
P SUFFIX
PLASTIC
CASE 648
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
FUNCTIONAL TRUTH TABLE

(Positive Logic)
Clock
Clock
Enable
0
X
X
X
1
X
0
X
X
1
Reset
Decode
Output=n
0
0
1
0
0
0
0
n
n
Q0
n+1
n
n
n+1
X = Dont Care. If n < 5 Carry = 1,

Otherwise = 0.
LOGIC DIAGRAM
Q5
1
Q1
2
Q7
6
Q3
7
Q9
BLOCK DIAGRAM
11
CLOCK 14
14
CLOCK
CLOCK
ENABLE
RESET
12
13
15
C
C
D
R
Q
R
C
D
R
Q
R
C
D
R
Q
R
C
D
R
Q
R
C
D
R
Q
R
CARRY
CLOCK
13
ENABLE
RESET 15
5
Q0
MC14017B
654
4
Q6
9
Q2
Cout
3
2
4
7
10
1
5
6
9
11
12
VDD = PIN 16
VSS = PIN 8
10
Q3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q4

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

PIN ASSIGNMENT
Q5
16
VDD
Q1
15
RESET
Q0
14
CLOCK
Q2
13
CE
Q6
12
Cout
Q7
11
Q9
Q3
10
Q4
VSS
Q8
MC14017B
655

Characteristic
Symbol

tTLH,
tTHL

Reset to Decode Output
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH,
tPHL

Clock to Cout
tPLH,
tPHL

Clock to Decode Output
tPLH,
tPHL
TurnOff Delay Time

Reset to Cout
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
tw(H)
5.0
10
15
250
100
75
125
50
35
ns
fcl
5.0
10
15
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tw(H)
5.0
10
15
500
250
190
250
125
95
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
ns
Clock Input Rise and Fall Time
tTLH,
tTHL
5.0
10
15
tsu
5.0
10
15
350
150
115
175
75
52
ns
trem
5.0
10
15
420
200
140
260
100
70
ns
Clock Frequency
Clock Enable Setup Time
Clock Enable Removal Time
No Limit
MC14017B
656
VDD
VDD
VSS
A
B
Vout
CLOCK Q0
ENABLE
Q1
Q2
Q3
Q4
RESET Q5
Q6
Q7
Q8
Q9
CLOCK Cout
VSS
S1
S1
Output
Sink Drive
Output
Source Drive
Decode
Outputs
(S1 to A)
Clock to
desired
outputs
(S1 to B)
Carry
Clock to 5
thru 9
(S1 to B)
S1 to A
VGS =
VDD
VDD
VDS =
Vout
Vout VDD
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 F
0.01 F
CERAMIC
ID
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CLOCK
ENABLE
RESET
PULSE
GENERATOR
fc
CLOCK
Cout
VSS
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
Figure 2. Typical Power Dissipation Test Circuit
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET
CLOCK
CE MC14017B
RESET
CLOCK
CE MC14017B
Q0 Q1 Q8 Q9
Q0Q1 Q8 Q9
9 DECODED
OUTPUTS
8 DECODED
OUTPUTS
RESET
CLOCK
CE MC14017B
Q1 Q8 Q9
8 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
MC14017B
657
Pcp
Ncp
90%
CLOCK
50%
CLOCK
ENABLE
trem
RESET
20 ns
Q0
Q2
Q3
Q4
tsu
20 ns
20 ns
20 ns
20 ns
20 ns
tPLH
tPLH
tPHL
90%
10%
tPHL
tPLH
50%
tTHL
tTLH
tPHL
tPLH
VOH
V
OL
tTLH
VOH
VOL
VOH
VOL
tTHL
tTLH
tPHL
VOH
VOL
tPHL
tPLH
tTHL
tTLH
tTLH
Q5
tPLH
Q6
VDD
VSS
50%
tPLH
10%
tTHL
tPLH
tPHL
tTLH
tPHL
90%
VOH
VOL
tTHL
tTHL
Q8
tTHL
tPHL
VOH
VOL
VOH
VOL
tPLH
tTLH
tTHL
tPLH
tPHL
Q9
Cout
tPHL
VOH
VOL
VOH
VOL
Q7
tTHL
VDD
VSS
VDD
VSS
tPHL
tPLH
Q1
trem
10%
tTLH
tPLH
tPHL
tTHL
tTLH
tTHL
VOH
VOL
VOH
VOL
Figure 4. AC Measurement Definition and Functional Waveforms
MC14017B
658
MOTOROLA
MC14018B
Presettable Divide-By-N
Counter
L SUFFIX
CERAMIC
CASE 620
The MC14018B contains five Johnson counter stages which are

asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on
the Jam inputs will then be transferred to their respective Q outputs
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection
table. Antilock gating is included in the MC14018B to assure proper
counting sequence.
Schmitt Trigger on Clock Input
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL


Clock
Reset
Preset
Enable
Jam
Input
Qn
X
X
X
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn
Dn*
1
0
1
* Dn is the Data input for that stage. Stage 1

has Data brought out to Pin 1.
PIN ASSIGNMENT
Din
16
VDD
JAM 1
15
JAM 2
14
Q2
13
Q5
Q1
12
JAM 5
Q3
11
Q4
JAM 3
10
PE
VSS
JAM 4
MC14018B
659

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc
MC14018B
660

Characteristic
Symbol

All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
tTLH, tTHL
ns
tPLH,
tPHL

Clock to Q
Unit
ns
5.0
10
15
310
120
85
620
240
170
Reset to Q
tPLH = (0.90 ns/pF) CL + 325 ns
tPLH = (0.36 ns/pF) CL + 132 ns
5.0
10
15
370
150
100
740
300
200
Preset Enable to Q
5.0
10
15
370
150
100
740
300
200
5.0
10
15
200
100
80
0
0
0
5.0
10
15
200
100
80
0
0
0
ns
th
5.0
10
15
540
500
480
270
250
240
ns
Clock Pulse Width
tWH
5.0
10
15
400
200
160
200
100
80
ns
Reset or Preset Enable

Pulse Width
tWH
5.0
10
15
290
130
110
145
65
55
ns
tTLH, tTHL
5.0
10
15
ns
ns
tsu
Setup Time
Data (Pin 1) to Clock
ns
Jam Inputs to Preset Enable
Data (Jam Inputs)toPreset

Enable Hold Time
Clock Rise and Fall Time
fcl
ns
No Limit
5.0
10
15
2.5
6.5
8.0
1.25
3.25
4.0
MHz
20 ns
20 ns
VDD
90%
50%
10%
ANY INPUT
VSS
tPLH
tPHL
VOH
90%
ANY OUTPUT
50%
10%
tTLH
VOL
tTHL
Figure 1. Switching Time Waveforms
MC14018B
661
CLOCK
0
1
0
1
0
1
0
1
0
RESET
PRESET ENABLE
JAM 1
JAM 2
TIMING DIAGRAM
(Q5 Connected to Data Input)
JAM 3
JAM 4
1
0
1
0
1
0
1
DONT CARE
UNTIL PRESET ENABLE
GOES HIGH
JAM 5
Q1
0
1
Q2
0
1
0
1
0
1
Q3
Q4
Q5
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
Q1
No external
components needed.
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 Q4
Q4 Q3
Q3 Q2
Q2 Q1
Gate package needed

to provide AND
function. Counter
Skips all 1s state
Comments
CLOCK 14
DATA
LOGIC DIAGRAM
JAM 1
2
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK
SHAPER
D
Q
R P
R P
R P
R P
R P
RESET 15
PRESET ENABLE 10
VDD = PIN 16
VSS = PIN 8
4
Q1
MC14018B
662
Q2
11
Q3
13
Q4
Q5
MOTOROLA
MC14020B
14-Bit Binary Counter
L SUFFIX
CERAMIC
CASE 620
The MC14020B 14stage binary counter is constructed with MOS

monolithic structure. This part is designed with an input wave shaping circuit
and 14 stages of ripplecarry binary counter. The device advances the count
on the negativegoing edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequencydividing circuits.
P SUFFIX
PLASTIC
CASE 648

Buffered Outputs Available from stages 1 and 4 thru 14
Common Reset Line
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
TRUTH TABLE
Clock
Reset
Output State
0
0
1
No Change
Advance to Next State
All Outputs are Low
X = Dont Care
LOGIC DIAGRAM
Q1
Q4
9
CLOCK
10
C
C
Q5
7
Q12
1
Q13
2
Q14
3
RESET
11
Q6 = PIN 4
Q7 = PIN 6
Q8 = PIN 13
Q9 = PIN 12
Q10 = PIN 14
Q11 = PIN 15
VDD = PIN 16
VSS = PIN 8
MC14020B
663

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

MC14020B
664
PIN ASSIGNMENT
Q12
16
VDD
Q13
15
Q11
Q14
14
Q10
Q6
13
Q8
Q5
12
Q9
Q7
11
Q4
10
VSS
Q1

Characteristic
Symbol

tTLH,
tTHL

Clock to Q1
tPLH,
tPHL
Clock to Q14
tPHL, tPLH (1.7 ns/pF) CL + 1735 ns
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
260
115
80
520
230
160
5.0
10
15
1820
805
560
3900
1725
1200
ns

Reset to Qn
tPHL = (0.66 ns/pF) CL + 122 ns
tPHL
Clock Pulse Width
ns
5.0
10
15
370
155
115
740
310
230
tWH
5.0
10
15
500
165
125
140
55
38
ns
fcl
5.0
10
15
2.0
6.0
8.0
1.0
3.0
4.0
MHz
tTLH, tTHL
5.0
10
15
No Limit
Reset Pulse Width
tWL
5.0
10
15
3000
550
420
320
120
80
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
ns
VDD
VDD
500 F
PULSE
GENERATOR
0.01 F
CERAMIC
ID
C Q1
Q4
Qn
R
C Q1
Q4
Qn
R
VSS
CL
CL
CL
CL
CL
VSS
20 ns
CLOCK
PULSE
GENERATOR
90%
50%
10%
50% DUTY CYCLE
20 ns
CL
CLOCK
90%
50%
10%
20 ns
VDD
VSS
tPLH
Q
tTLH
Figure 1. Power Dissipation Test Circuit

and Waveform
20 ns
tWH
tPHL
90%
50%
10%
tTHL
Figure 2. Switching Time Test Circuit

and Waveforms
MC14020B
665
16
32
64
128
256
512
1024
2048
4096
8192
16,384
CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Figure 3. Timing Diagram
MC14020B
666
MOTOROLA
MC14022B
Octal Counter
L SUFFIX
CERAMIC
CASE 620
The MC14022B is a fourstage Johnson octal counter with builtin code

converter. Highspeed operation and spikefree outputs are obtained by
use of a Johnson octal counter design. The eight decoded outputs are
normally low, and go high only at their appropriate octal time period. The
output changes occur on the positivegoing edge of the clock pulse. This
part can be used in frequency division applications as well as octal counter
or octal decode display applications.
P SUFFIX
PLASTIC
CASE 648

DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Clock
Tstg
Storage Temperature
65 to + 150
_C
260
_C
0
X
TL
1
Q4

(Positive Logic)
Clock
Enable
X
1
0
X
1
X
X
Reset
Output=n
0
0
0
0
0
0
1
n
n
n+1
n
n+1
n
Q0
X = Dont Care. If n < 4 Carry = 1,

Otherwise = 0.
LOGIC DIAGRAM
11
Plastic
Ceramic
SOIC
5
Q1
7
Q6
Q3
BLOCK DIAGRAM
CLOCK
14
13
CLOCK
ENABLE
15
RESET
VDD
VSS
C Q
C
D RQ
C Q
C
D RQ
C Q
C
D RQ
C Q
C
D RQ
CLOCK
14
CLOCK
ENABLE
13
RESET
15
CARRY
12
VDD = PIN 16
VSS = PIN 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
2
1
3
7
11
4
5
10
12
NC = PIN 6, 9
Q0
2
Q5
4
Q2
3
Q7
10
MC14022B
667

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

PIN ASSIGNMENT
Q1
16
VDD
Q0
15
Q2
14
Q5
13
CE
Q6
12
Cout
NC
11
Q4
Q3
10
Q7
VSS
NC
NC = NO CONNECTION
MC14022B
668

Characteristic
Symbol

tTLH,
tTHL

Reset to Decode Output
tPLH,
tPHL

Clock to Cout
tPLH,
tPHL

Clock to Decode Output
tPLH,
tPHL
TurnOff Delay Time

Reset to Cout
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
500
230
175
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
ns
5.0
10
15
275
125
95
1000
460
350
ns
5.0
10
15
400
175
125
800
350
250
tWH
5.0
10
15
250
100
75
125
50
35
ns
fcl
5.0
10
15
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tWH
5.0
10
15
500
250
190
250
125
95
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
ns
tTLH, tTHL
5.0
10
15
Clock Frequency
Clock Enable Setup Time
Clock Enable Removal Time
No Limit
tsu
5.0
10
15
350
150
115
175
75
52
ns
trem
5.0
10
15
420
200
140
260
100
70
ns
MC14022B
669
VDD
CLOCK Q0
ENABLE Q1
Q2
Q3
Q4
RESET
Q5
Q6
Q7
CLOCK C
out
VSS
A
VDD
VSS
S1
Output
Sink Drive
Output
Source Drive
Outputs
(S1 to A)
Clock to desired
Output
(S1 to B)
Carry
Clock to Q5
thru Q7
(S1 to B)
S1 to A
VGS =
VDD
VDD
VDS =
Vout
Vout VDD
Vout
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 F
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
CLOCK
ENABLE
RESET
PULSE
GENERATOR
0.01 F
CERAMIC
ID
fc
CLOCK
CL
VSS
CL
CL
CL
CL
CL
CL
CL
CL
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
CE MC14022B
Q0 Q1 Q6 Q7
7 DECODED
OUTPUTS
CE MC14022B
Q0 Q1 Q6 Q7
6 DECODED
OUTPUTS
CE MC14022B
Q1 Q6 Q7
6 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
MC14022B
670
tWH
tWL
90%
CLOCK
trel
CLOCK
ENABLE
RESET
Q0
tsu
20 ns
trem
20 ns
20 ns
20 ns
Q2
tPLH
50%
tPHL
tTHL
90%
tPLH
tPLH
tPHL
VOH
VOL
VOH
VOL
50%
10%
tTLH
tPHL
VDD
VSS
VDD
VSS
tPLH
tPHL
tPLH
Q1
20 ns
V
50% DD
VSS
10%
VOH
VOL
tTLH
VOH
VOL
Q3
tPLH
Q4
tPLH
Q5
tTLH
tPHL
tTLH
tPHL
tPLH
tTLH
tTHL
tTLH
tPHL
Q6
tPLH
tPHL
Q7
Cout
tPHL
tTLH
tTHL
tPLH
tPHL
tTLH
VOH
VOL
tPHL
VOH
VOL
tTHL
VOH
VOL
VOH
VOL
VOH
VOL
tTHL
Figure 4. AC Measurement Definition and Functional Waveforms
MC14022B
671
MOTOROLA
MC14024B
7-Stage Ripple Counter
L SUFFIX
CERAMIC
CASE 632
The MC14024B is a 7stage ripple counter with short propagation delays

and high maximum clock rates. The Reset input has standard noise
immunity, however the Clock input has increased noise immunity due to
Hysteresis. The output of each counter stage is buffered.

Output Transitions Occur on the Falling Edge of the Clock Pulse
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
LOGIC DIAGRAM
1
C
CLOCK
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
CLOCK
14
VDD
RESET
13
NC
Q7
12
Q1
Q6
11
Q2
Q5
10
NC
Q4
Q3
VSS
NC
Q
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
2
RESET
12
Q1
11
Q2
4
Q6
3
Q7
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
MC14024B
672

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc
be left open.
MC14024B
673

Characteristic
Symbol

tTLH,
tTHL

Clock to Q1
Clock to Q7
Reset to Qn
tPLH,
tPHL
Clock Pulse Width
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
380
150
110
600
230
175
5.0
10
15
1000
400
300
2000
750
565
5.0
10
15
500
250
180
800
400
300
tWH
5.0
10
15
500
165
125
200
60
40
ns
Reset Pulse Width
tWH
5.0
10
15
600
350
260
375
200
150
ns
Reset Removal Time
trem
5.0
10
15
625
190
145
250
75
50
ns
tTLH, tTHL
5.0
10
15
1.0
8.0
200
s
ms
s
fcl
5.0
10
15
2.5
8.0
12
1.0
3.0
4.0
MHz
Input Pulse Frequency
TRUTH TABLE
MC14024B
674
Clock
Reset
State
No Change
All Outputs Low
No Change
All Outputs Low
No Change
All Outputs Low
Advance One Count
All Outputs Low
VDD
VDD
VDD
VOL = Vout
C Qn
C Qn
IOH
COUNT Qn TO A
LOGIC 1 LEVEL.
VSS
VOH = Vout
IOL
EXTERNAL
POWER
SUPPLY
VSS

EXTERNAL
POWER
SUPPLY

VDD
500 F
PULSE
GENERATOR
0.01 F
CERAMIC
ID
C Q1
Q2
Q3
Q4
Q5
Q6
R Q7
CL
CL
CL
CL
CL
CL
CL
VSS
MC14024B
675
MC14024B
676
t WL
t WH
1
VDD
50%
16
32
64
128
255
VSS
CLOCK (1)
RESET (2)
t rem
VDD
50%
t PLH1
t PHL1
t R1
VOH
90%
50%
Figure 4. Functional Waveforms
10%
Q1 (12)
t TLH
t PHL2
t PLH2
90%
t THL
t R2
t TLH
t THL
t R3
VOL
VOH
50%
10%
Q2 (11)
VSS
VOL
t PHL3
t PLH3
VOH
50%
VOL
Q3 (9)
t TLH
t PHL4
t PLH4
t THL
t R4
t THL
t R5
t THL
t R6
VOH
50%
Q4 (6)
t TLH
t PHL5
t PLH5
VOL
VOH
50%
Q5 (5)
t TLH
t PHL6
t PLH6
10%
Q6 (4)
t TLH
VOH
90%
50%
t PLH7
t PHL7
VOL
t THL
t R7
VOL
VOH
VOL
Q7 (3)
t TLH
Input t TLH and t THL = 20 ns
t THL
MOTOROLA
MC14027B
Dual J-K Flip-Flop
The MC14027B dual JK flipflop has independent J, K, Clock (C), Set (S)
and Reset (R) inputs for each flipflop. These devices may be used in
control, register, or toggle functions.
L SUFFIX
CERAMIC
CASE 620

information is transferred to the output only on the positivegoing edge
of the clock pulse

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
TRUTH TABLE
Inputs
C
Outputs*
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
BLOCK DIAGRAM
7
6
Qn+1
Qn+1
10
13
Qo
Qo
Qo
11
Qn
Qn
X = Dont Care
= Level Change
1
X
= Present State
* = Next State
15
14
Qn
Plastic
Ceramic
SOIC
No
Change
12
VDD = PIN 16
VSS = PIN 8

MC14027B
677

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc
PIN ASSIGNMENT
MC14027B
678
QA
16
VDD
QA
15
QB
CA
14
QB
RA
13
CB
KA
12
RB
JA
11
KB
SA
10
JB
VSS
SB

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Times**

Clock to Q, Q
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
175
75
50
350
150
100
Set to Q, Q
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
5.0
10
15
350
100
75
450
200
150
Setup Times
tsu
5.0
10
15
140
50
35
70
25
17
ns
Hold Times
th
5.0
10
15
140
50
35
70
25
17
ns
tWH, tWL
5.0
10
15
330
110
75
165
55
38
ns
fcl
5.0
10
15
3.0
9.0
13
1.5
4.5
6.5
MHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
Set
5
10
15
90
45
35
10
5
3
Reset
5
10
15
50
25
20
30
15
10
5.0
10
15
250
100
70
125
50
35
Clock Pulse Width
Removal Times
Set and Reset Pulse Width
trem
tWH
ns
ns
MC14027B
679
20 ns
20 ns
VDD
90%
50%
10%
20 ns
K
90%
50%
10%
tsu
tsu
20 ns
th
90%
50%
10%
C
tWH
VSS
20 ns
VDD
VSS
20 ns
VDD
VSS
20 ns
90%
SET OR
RESET
tw
tWL
1
fcl
tPLH
tPHL
VOH
90%
50%
10%
CLOCK
tTLH
20 ns
VDD
50%
50%
Q or Q
20 ns
10%
tw
tPLH
tPHL
Inputs R and S low.

For the measurement of tWH, I/fcl, and PD
the Inputs J and K are kept high.
VSS
trem
20 ns
90%
VOL
tTHL
10%
VDD
VSS
VOH
50%
VOL

(J, K, Clock, and Output)

(Set, Reset, Clock, and Output)
LOGIC DIAGRAM
S
Q
C
J
C
C
C
K
R
Q
C
C
MC14027B
680
MOTOROLA
MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
L SUFFIX
CERAMIC
CASE 620
The MC14028B decoder is constructed so that an 8421 BCD code on the

four inputs provides a decimal (oneoften) decoded output, while a 3bit
binary input provides a decoded octal (oneofeight) code output with D
forced to a logic 0. Expanded decoding such as binarytohexadecimal
(oneof16), etc., can be achieved by using other MC14028B devices. The
part is useful for code conversion, address decoding, memory selection
control, demultiplexing, or readout decoding.
P SUFFIX
PLASTIC
CASE 648

Positive Logic Design
Low Outputs on All Illegal Input Combinations
Similar to CD4028B.
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
TRUTH TABLE
D C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
BLOCK DIAGRAM
8421
BCD
INPUTS
3BIT
BINARY
INPUTS
10
13
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
3
14
2
15
1
6
7
4
9
5
OCTAL
DECODED
OUTPUTS
DECIMAL
DECODED
OUTPUTS
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDD = PIN 16
VSS = PIN 8
MC14028B
681
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
VOL
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
VOH
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
IOH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
0 Level
1 Level
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
Vdc
1 Level
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
mAdc
Source
Sink

Per Package)
buffers switching)

Adc

MC14028B
682
PIN ASSIGNMENT
Q4
16
VDD
Q2
15
Q3
Q0
14
Q1
Q7
13
Q9
12
Q5
11
Q6
10
VSS
Q8

Characteristic
Symbol

tTLH,
tTHL

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
300
130
90
600
260
180
Unit
ns
ns
Inputs B, C, and D
switching in respect
to a BCD code.
20 ns
20 ns
VDD
90%
INPUT A
50%
10%
VSS
All outputs connected

to respective CL loads.
f in respect to a system
clock.
1/f
20 ns
20 ns
VDD
90%
INPUT C
50%
10%
Inputs A, B, and D low.
VSS
tPLH
tPHL
VOH
90%
Q4
50%
10%
VOL
tTLH
tTHL
MC14028B
683
LOGIC DIAGRAM
Q0
Q1
A
Q2
Q3
B
Q4
Q5
C
Q6
Q7
Q8
Q9
INPUTS
Expanded decoding can be performed by using the

MC14028B and other CMOS Integrated Circuits. The circuit
in Figure 2 converts any 4bit code to a decimal or hexadecimal code. The accompanying table shows the input binary
combinations, the associated output numbers that go high
when selected, and the redefined output numbers needed
for the proper code. For example: For the combination DCBA
= 0111 the output number 7 is redefined for the 4bit binary,
4bit gray, excess3, or excess3 gray codes as 7, 5, 4, or 2,
respectively. Figure 3 shows a 6bit binary 1of64 decoder
using nine MC14028B circuits and two MC14069UB inverters.
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
MC14028B
MC14028B
Q9
Q0
15
Q9
Q0
15
OUTPUT NUMBERS
Figure 2. Code Conversion Circuit and Truth Table
Code and Redefined

Output Numbers
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
2
3
0
1
3
2
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
5
6
7
7
6
4
5
1
2
3
4
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
10
11
15
14
12
13
5
6
7
8
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
13
14
15
8
9
11
10
MC14028B
684
4221
Aiken
Decimal
Excess3
Gray
4Bit
Gray
Output Numbers
4Bit
Binary
Inputs
Excess3
Hexadecimal
0
3
0
1
2
3
0
1
2
4
3
4
1
2
5
6
9
5
5
6
8
7
6
7
8
9
7
8
9
INPUTS
A
INHIBIT
C
MC14028B
Q0
(NO SELECTION)
Q9
A B C D A B C D
A B C D A B C D A B C D A B C D A B C D
A B C D
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
MC14028B
Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9 Q0
Q9
0
15
*1/6 MC14069UB
16
23
24
31
32
39
40
47
48
55
56
63
64 OUTPUTS (SELECTED OUTPUT IS HIGH)
Figure 3. SixBit Binary 1of64 Decoder
A
B
MC14028B
C
D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
APPROPRIATE
VOLTAGE
APPROPRIATE
VOLTAGE
INCANDESCENT
DISPLAY
NEON
DISPLAY
OR
Figure 4. Decimal Digit Display Application
MC14028B
685
MOTOROLA

MC14029B
Binary/Decade Up/Down
Counter
L SUFFIX
CERAMIC
CASE 620
The MC14029B Binary/Decade up/down counter is constructed with MOS

monolithic structure. The counter consists of type D flipflop stages with a
gating structure to provide toggle flipflop capability. The counter can be
used in either Binary or BCD operation. This complementary MOS counter
finds primary use in up/down and difference counting and frequency
synthesizer applications where low power dissipation and/or high noise
immunity is desired. It is also useful in A/D and D/A conversion and for
magnitude and sign generation.

Internally Synchronous for High Speed
Logic EdgeClocked Design Count Occurs on Positive Going Edge
of Clock
Asynchronous Preset Enable Operation
Pin for Pin Replacement for CD4029B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
Tstg
Storage Temperature
TL
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
PE
16
VDD
Q3
15
CLK
P3
14
Q2
P0
13
P2
Cin
12
P1
mW
Q0
11
Q1
65 to + 150
_C
Cout
10
U/D
260
_C
VSS
B/D
TRUTH TABLE
Carry In
Up/Down
Preset
Enable
Action
No Count
Count Up
Count Down
Preset
X = Dont Care
MC14029B
686

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14029B
687
All Types
Characteristic
Symbol

tTLH,
tTHL

Clk to Q
tPLH,
tPHL
Clk to Cout
tPLH,
tPHL
Cin to Cout
tPLH,
tPHL
PE to Q
tPLH,
tPHL
PE to Cout
tPLH, tPHL = (1. 7 ns/pF) CL + 465 ns
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
200
100
90
400
200
180
5.0
10
15
250
130
85
500
260
190
5.0
10
15
175
50
50
360
120
100
5.0
10
15
235
100
80
470
200
160
5.0
10
15
320
145
105
640
290
210
tW(cl)
5.0
10
15
180
80
60
90
40
30
ns
fcl
5.0
10
15
4.0
8.0
10
2.0
4.0
5.0
MHz
Preset Removal Time

The Preset Signal must be low prior to a positivegoing
transition of the clock.
trem
5.0
10
15
160
80
60
80
40
30
ns
tr(cl)
tf(cl)
5.0
10
15
15
5
4
tsu
5.0
10
15
150
60
40
75
30
20
ns
Up/Down Setup Time
5.0
10
15
340
140
100
170
70
50
ns
Binary/Decade Setup Time
5.0
10
15
320
140
100
160
70
50
ns
5.0
10
15
130
70
50
65
35
25
ns
Clock Pulse Width
Carry In Setup Time
Preset Enable Pulse Width
tW
ns
ns
ns
ns
MC14029B
688
VDD
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PULSE
GENERATOR
0.01 F
CERAMIC
ID
500 pF
Q0
Q1
Q2
CL
CL
Q3
CL
Cout
CL
CL
20 ns
20 ns
50%
CLK
90%
10%
VARIABLE
WIDTH
VDD
VSS
VDD
PE
Cin
B/D
U/D
CLK
P0
P1
P2
P3
PROGRAMMABLE
PULSE
GENERATOR
Q0
Q1
Q2
CL
CL
Q3
CL
CL
Cout
CL
VSS
tW
tsu
CARRY IN OR
UP/DOWN
OR BINARY/DECADE
trem
1/fcl
VDD
VSS
VDD
VSS
VDD
VSS
50%
CLOCK
50%
tW
PRESET ENABLE
20 ns
Cout ONLY
90%
10%
Q0 OR CARRY OUT
10%
tTLH
90%
VOH
VOL
tPLH
tTHL
tPHL
tPLH
MC14029B
689
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0
Q3 Q2 Q1 Q0
Cin
Cout
MC14029B
U/D
MSD
PE
B/D
P3 P2 P1 P0 CLK
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
PE
B/D
P3 P2 P1 P0 CLK
VDD
Q3 Q2 Q1 Q0
Cout
Cin
MC14029B
U/D
LSD
PE
B/D
P3 P2 P1 P0 CLK
VDD
OUTPUT
VDD VDD
INPUT
CLOCK
CLOCK
Cout 1 (LSD)
Cout 2
Cout 3 (MSD)
* tW
122
123
10
11
99
100
101
119
120
121
122
COUNT
123
PE
^ 900 ns @ VDD = 5 V
Figure 3. Divide by N BCD Down Counter and Timing Diagram

(Shown for N = 123)
MC14029B
690
P0
12
P1
13
P2
P3
BINARY/DECADE
1
PRESET ENABLE
PE P0
PE P1
PE P2
PE P3
TE Q0
TE Q1
TE Q2
TE Q3
CLK Q0
CLK Q1
CLK Q2
7
CARRY OUT
CLK Q3
10
UP/DOWN
15
CLOCK
6
Q0
Q1
14
Q2
Q3
LOGIC DIAGRAM
5
CARRY IN
MC14029B
691
MOTOROLA
MC14032B
MC14038B
Triple Serial Adders

The MC14032B and MC14038B triple serial adders have the clock and
carry reset inputs common to all three adders. The carry is added on the
positivegoing clock transition for the MC14032B, and on the negative
going clock transition for the MC14038B. Typical applications include serial
arithmetic units, digital correlators, digital servo control systems, datalink
computers, and flight control computers.
L SUFFIX
CERAMIC
CASE 620
Buffered Outputs
SinglePhase Clocking
PinforPin Replacement for CD4032B and CD4038B.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
MC14032B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
BLOCK DIAGRAM
A1 10
B1 11
INVERT 1 7
A2 13
B2 12
INVERT 2 5
A3
B3
INVERT 3
CLOCK
CARRY RESET
9 S1
ADDER 2
4 S2
15
14
2
3
6
ADDER 3
1 S3
MC14038B
A
B
D Q
D Q
CR
CR
INVERT
CARRY
RESET
ADDER 1
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAMS
(ONE SECTION AND COMMON INPUTS SHOWN)
A
B
Plastic
Ceramic
SOIC
INVERT
CARRY
RESET
D Q
C
CLOCK
MC14032B MC14038B
692
TO
NEXT
STAGE
D Q
C
CLOCK
TO
NEXT
STAGE

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
S3
16
VDD
INV 3
15
A3
14
B3
S2
13
A2
INV 2
CARRY
RESET
INV 1
12
B2
11
B1
10
A1
VSS
S1
MC14032B MC14038B
693

Characteristic
Symbol

tTLH,
tTHL

A, B or Invert to Sum
tPLH,
tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
Clock to Sum
5.0
10
15
280
120
90
1400
300
230
5.0
10
15
500
180
135
2400
600
450
ns
Input Setup Time
tsu
5.0
10
15
10
10
10
10
0
0
ns
fcl
5.0
10
15
4.0
10
12
1.0
2.5
4.0
MHz
tTHL, tTLH
5.0
10
15
15
5
4
Clock Rise and Fall Times
TIMING DIAGRAMS
MC14032B
WORD 1 + WORD 2
MC14038B
WORD 3 + WORD 4
A
B
C
INV
A
B
C
INV
CR
S
CR
S
TRUE SUM
WORD 1: 0.0111100 = + 60
WORD 2: 0.0110010 = + 50
0.1101110 = + 110
COMPLEMENTED
SUM
WORD 3: 1.1011011 = 37
WORD 4: 1.1001110 = 50
1.0101001 = 87
WORD 1 + WORD 2
WORD 3 + WORD 4
TRUE SUM
COMPLEMENTED
SUM
WORD 1: 1.1000011 = 61
WORD 2: 1.1001101 = 51
1.0010000 = 112
WORD 3: 0.0100100 = + 36
WORD 4: 0.0110001 = + 49
0.1010101 = + 85
NOTE: Unused input pins must be connected to either VDD or VSS.
MC14032B MC14038B
694
VDS = VOL
VDS = VOH VDD

VDD = VGS
VDD = VGS
VOH
VOL
VDD
VDD
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
IOH
EXTERNAL
POWER
SUPPLY
VSS
IOL
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source Test Circuit
Figure 2. Typical Output Sink Test Circuit
VDD
500 pF
0.01 F
CERAMIC
ID
VDD
PROGRAMMABLE
PULSE
GENERATOR
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
VSS
20 ns
50%
CLOCK
VARIABLE
WIDTH
CL
20 ns
90%
VDD
10%
VSS
VDD
90%
CL
A,B
10%
tTHL
VSS
tTLH
CL
MC14032B MC14038B
695
VDD
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
PROGRAMMABLE
PULSE
GENERATOR
CL
CL
VSS
CL
MC14032B
VDD
A
50%
VSS
VDD
50%
VSS
tsu
VDD
50%
CLOCK
VSS
tPLH
tPHL
tPLH
tPHL
VOH
90%
50%
10%
SUM
VOL
tTLH
tTHL
MC14038B
A
VDD
50%
VSS
VDD
50%
tsu
CLOCK
VSS
VDD
50%
VSS
SUM
tPHL
90%
50%
10%
tTHL
tPLH
tPHL
tPLH
VOH
VOL
tTLH
MC14032B MC14038B
696
MOTOROLA
MC14034B
8-Bit Universal Bus Register
L SUFFIX
CERAMIC
CASE 623
The MC14034B is a bidirectional 8bit static parallel/serial, input/output

bus register. The device contains two sets of input/output lines which allows
the bidirectional transfer of data between two buses; the conversion of serial
data to parallel form, or the conversion of parallel data to serial form.
Additionally the serial data input allows data to be entered shift/right, while
shift/left can be accomplished by hardwiring each parallel output to the
previous parallel bit input.
Other useful applications for this device include pseudorandom code
generation, sample and hold register, frequency and phasecomparator,
address or buffer register, and serial/parallel input/output conversions.
DW SUFFIX
SOIC
CASE 751E
Bidirectional Parallel Data Input

PinforPin Replacement for CD4034B.

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

P SUFFIX
PLASTIC
CASE 709
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
B8
24
VDD
B7
23
A8
B6
22
A7
B5
21
A6
B4
20
A5
B3
19
A4
B2
18
A3
B1
17
A2
A ENABLE
16
A1
DS
10
15
A/B
11
14
A/S
VSS
12
13
P/S
MC14034B
697

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
3State Output Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
MC14034B
698

Characteristic
Symbol
Output Rise Time A or B

tTLH
Output Fall Time A or B

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

A (B) Synchronous Parallel Data Input,
B (A) Parallel Data Output
tPHL, tPHL = (0.66 ns/pF) CL + 172 ns
tPLH,
tPHL

A (B) Asynchronous Parallel Data Input
B (A) Parallel Data Output
tPLH,
tPHL
Clock Pulse Width
VDD
Vdc
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
ns
ns
ns
5.0
10
15
Clock Pulse Rise
A, B Input Setup Time
High Level SE, P/S, A/S Pulse Width
Unit
525
205
145
1050
410
290
ns
5.0
10
15
505
180
130
1010
360
260
tWH
5.0
10
15
340
140
110
170
70
55
ns
fcl
5.0
10
15
2.5
6.0
8.0
1.2
3.0
4.0
MHz
tTLH, tTHL
5.0
10
15
15
5
4
tsu
5.0
10
15
100
45
35
35
15
12
ns
tWH
5.0
10
15
600
270
200
200
90
80
ns
TRUTH TABLE
A Enable
P/S
A/B
A/S
Mode
Serial
Synchronous Serial data input, A and B Parallel data outputs disabled.
Operation
Serial
Synchronous Serial data input, BParallel data output.
Parallel
B Synchronous Parallel data inputs, AParallel data outputs disabled.
Parallel
B Asynchronous Parallel data inputs, AParallel data outputs disabled.
Parallel
AParallel data inputs disabled, BParallel data outputs.
Parallel
AParallel data inputs disabled, BParallel data outputs.
Serial
Synchronous serial data input, AParallel data output.
Serial
Synchronous serial data input, BParallel data output.
Parallel
BSynchronous Parallel data input, AParallel data output.
Parallel
BAsynchronous Parallel data input, AParallel data output.
Parallel
ASynchronous Parallel data input, BParallel data output.
Parallel
AAsynchronous Parallel data input, BParallel data output.
X = Dont Care
Outputs change at positive transition of clock in the serial mode and when the A/S input is low in the parallel mode. During transfer from parallel
to serial operation, A/S should remain low in order to prevent DS transfer into flipflops.
MC14034B
699
EXPANDED BLOCK DIAGRAM
A1
A2
DATA
A4
A5
A3
A6
A7
A8
SERIAL DATA INPUT

ENABLE A
A/B
PARALLEL/SERIAL P/S
CONTROL
LOGIC
8BIT REGISTER
ASYN/SYN A/S
CLOCK
B1
B2
B3
B4
B5
DATA
B6
B7
B8
OPERATING CHARACTERISTICS
B; when low, the data flows from bus B to bus A.
P/S Input (Parallel/Serial) This input controls the data
input mode (parallel or serial). When high, the data is transferred to the register in a parallel asynchronous mode or a
parallel synchronous mode (positive clock transition). When
low, the data is entered into the register in a serial synchronous mode (positive clock transition).
A/S Input (Asynchronous/Synchronous to the Clock)
When this input is high, the data is transferred independently from the clock rate; when low, the clock is enabled and
the data is transferred synchronously.
The MC14034B is composed of eight register cells connected in cascade with additional control logic. Each register
cell is composed of one D masterslave flipflop with separate internal clocks, and two data transfer gates allowing the
data to be transferred bidirectionally from bus A to bus B
and from bus B to bus A, and to be memorized. Besides the
single phase clock and the serial data inputs, the control logic provides four other features:
A Enable Input When high, this input enables the bus A
data lines.
A/B Input (Data A or B) This input controls the direction of data flow: when high, the data flows from bus A to bus
LOGIC DIAGRAM
A1
16
A2 A3 A4 A5 A6 A7
17 18 19 20 21 22
A8
23
VDD
VDD
A ENABLE
A/B 11
SERIAL DATA 10
*D
FLIP
FLOP
*D FLIP FLOP
6 STAGES
(SAME AS
STAGE 1)
PARALLEL SERIAL 13
CM
ASYN/SYN 14
D Q
CM CS
CS
VDD
CLOCK 15
8
B1
MC14034B
6100
7 6 5 4 3 2
B2 B3 B4 B5 B6 B7
1
B8
INPUT
A(B)
tsu
20 ns
20 ns
CLOCK
90%
10%
50%
tPLH
tPHL
OUTPUT
B(A)
tTLH
tTHL
Figure 1. Propagation Delay and Transition Times Waveforms
PROPAGATION AND TRANSITION TIME TEST CIRCUITS

VDD
VDD
CL
A1 A2 A3 A4 A5 A6 A7 A8
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
A ENABLE
P/S
P/S
PROGRAMMABLE
PULSE
GENERATOR
PROGRAMMABLE
PULSE
GENERATOR
DS
A/B
DS
A/B
A/S
A/S
C
B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 B7 B8
VSS
CL
Figure 2. A Synchronous Data Input, B Parallel

Data Output and Setup Time
VSS
Figure 3. B Synchronous Data Input, A Parallel

Data Output and Setup Time
MC14034B
6101
VDD
20 ns
20 ns
A1 A2 A3 A4 A5 A6 A7 A8
90%
50%
CLOCK
AE
P/S
10%
VSS
tWH
DS
A/B
PROGRAMMABLE
PULSE
GENERATOR
VDD
tWL
DS
A/S
C
90%
10%
VSS
20 ns
B1 B2 B3 B4 B5 B6 B7 B8
VDD
50%
20 ns
1/f
tWH = tWL = 50% DUTY CYCLE
VSS
CL
CL
CL
CL
CL
CL
CL
CL
VDD
VDD
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
A1 A2 A3 A4 A5 A6 A7 A8
A ENABLE
SERIAL
DATA
VDD
SERIAL
DATA
P/S
DS
A/B
MC14034B
VDD
P/S
DS
A/B
A/S
A/S
C B1 B2 B3 B4 B5 B6 B7 B8
C B1 B2 B3 B4 B5 B6 B7 B8
SERIAL
DATA
P/S
A/S
CLOCK
Figure 5. 16Bit Parallel In/Parallel Out, Parallel In/Serial Out,

Serial In/Parallel Out, Serial In/Serial Out Register
MC14034B
6102
SHIFT LEFT OUTPUT
A ENABLE
AE
P/S
SHIFT LEFT/
SHIFT RIGHT
SHIFT RIGHT
OUTPUT
A1
AE
SHIFT RIGHT
INPUT
REGISTER 1
MC14034B
A8
P/S
P/S
DS
A/B
DS
A/B
A/S
A/S
C B1
CLOCK
A1
AE
A8
REGISTER 2
MC14034B
CB1
B8
B8
SHIFT LEFT
INPUT*
A/S PARALLEL
ENTRY
A/S
COCK
AE
A1
AE
A1
AE
A8
P/S
P/S
DS
A/B
A8
REGISTER 3
MC14034B
DS
A/B
A/S
A/S
C B1
VDD
REGISTER 4
MC14034B
C B1
B8
B8
VDD
A High (Low) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register
on the positive transition of the lock signal. A high on the A Enable Input disables the A parallel data lines on Reg. 1 and 2
and enables the A data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be
used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used, Reg. 3 and 4 and associated logic are not required.
*Shift left input must be disabled during parallel entry.
Figure 6. Shift Right/Shift Left with Parallel Inputs
MC14034B
6103
MOTOROLA
MC14035B
4-Bit Parallel-In/Parallel-Out
Shift Register
The MC14035B 4bit shift register is constructed with MOS Pchannel
It consists of a 4stage clocked serialshift register with synchronous
parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input
allows serialright shifting of data or synchronous parallel loading via inputs
DP0 thru DP3. The True/Complement (T/C) input determines whether the
outputs display the Q or Q outputs of the flipflop stages. JK logic forms the
serial input to the first stage. With the J and K inputs connected together they
operate as a serial D input.
This device may be effectively used for shiftright/shiftleft registers,
paralleltoserial/serialtoparallel conversion, sequence generation, up/
down Johnson or ring counters, pseudorandom code generation, frequency and phase comparators, sample and hold registers, etc . . .
4Stage Clocked SerialShift Operation

Synchronous Parallel Loading of all Four Stages
JK Serial Inputs on First Stage
Asynchronous True/Complement Control of all Outputs
Asynchronous Master Reset
Data Transfer Occurs on the PositiveGoing Clock Transition
No Limit on Clock Rise and Fall Times
All Inputs are Buffered
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD

Storage Temperature
TL
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Vin, Vout
Tstg
D SUFFIX
SOIC
CASE 751B

Parameter
P SUFFIX
PLASTIC
CASE 648
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Symbol
L SUFFIX
CERAMIC
CASE 620
500
mW
65 to + 150
_C
260
_C
Q0
16
VDD
T/C
15
Q1
14
Q2
13
Q3
12
DP3
11
DP2
P/S
10
DP1
VSS
DP0
TRUTH TABLE
Inputs
C
tn Output
Q0
0
0
1
0
1
0
0
0
0
0
Q0 (n 1)
Q0 (n 1)
1
X
X
1
X
X
0
0
1
1
Q0 (n 1)
0
MC14035B
6104
X = Dont Care
P/S = 0 = Serial Mode
T/C = 1 = True Outputs

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
(CL = 50 pF on all outputs all
buffers switching)
mAdc

Adc
be left open.
MC14035B
6105
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C, See Figure 1)

Characteristic
Symbol

TTLH, TTHL = (1.5 ns/pF) CL + 25 ns
TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns
Propagation Delay Time, Clock or Reset to Q
TPLH, TPHL = (1.75 ns/pF) CL + 223 ns
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
300
130
95
600
260
190
tTLH,
tTHL
Unit
ns
tPLH,
tPHL
ns
Clock Pulse Width
tWH
5.0
10
15
335
165
125
135
45
40
ns
Reset Pulse Width
tWH
5.0
10
15
400
175
130
80
40
35
ns
Reset Removal Time
trem
5.0
10
15
80
30
25
40
15
10
ns
tTLH, tTHL
5.0
10
15
No Limit
fcl
5.0
10
15
2.5
6.0
10
1.2
2.0
3.0
MHz
JK to Clock Setup Time
tsu
5.0
10
15
500
200
150
120
50
30
ns
Clock to JK Hold Time
th
5.0
10
15
40
30
25
40
5
0
ns
P/S to Clock Setup Time
tsu
5.0
10
15
500
200
150
25
10
7.5
ns
Clock to P/S Hold Time
th
5.0
10
15
30
20
20
70
20
10
ns
DP to Clock Setup Time
tsu
5.0
10
15
500
200
150
90
20
15
ns
Clock to DP Hold Time
th
5.0
10
15
90
40
40
25
0
5
ns
50%
RESET
trem
CLOCK
INPUT
JK
INPUT
50%
tWH
1/fcl
50%
th
tsu
tsu
P/S
INPUT
50%
DP0
INPUT
Q0
tsu
th
50%
tTHL
90%
tTLH
10%
th
50%
tsu
T/C INPUT LOW

tPHL
tPLH
tPHL
tPLH

MC14035B
6106
LOGIC DIAGRAM
DP3 12
DP2 11
DP1 10
DP0 9
P/S
D
K
D
C
D
C
D
C
13 Q3
R
14 Q2
6
15 Q1
T/C
1 Q0
APPLICATION DIAGRAM
Shift Left/Shift Right Register
Q0
LEFT SHIFT
SERIAL OUTPUT
Q1
Q2
LEFT SHIFT
SERIAL INPUT
VDD
Q3
16 15
VDD Q1
Q0 T/C
1
2
RIGHT SHIFT
SERIAL INPUT
RIGHT SHIFT
SERIAL OUTPUT
14 13 12 11 10 9
Q2 Q3 DP3 DP2 DP1 DP0
K
3
J
4
R
5
C
6
P/S VSS
7
8
VDD
RESET
CLOCK
LEFT/RIGHT
SHIFT SELECT
MC14035B
6107
MOTOROLA
MC14040B
12-Bit Binary Counter
L SUFFIX
CERAMIC
CASE 620
The MC14040B 12stage binary counter is constructed with MOS

monolithic structure. This part is designed with an input wave shaping circuit
and 12 stages of ripplecarry binary counter. The device advances the count
on the negativegoing edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequencydriving circuits.
P SUFFIX
PLASTIC
CASE 648

Common Reset Line
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
lin, lout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
TRUTH TABLE
Clock
Reset
Output State
0
0
1
No Change
Advance to next state
All Outputs are low
X = Dont Care
LOGIC DIAGRAM
Q1
Q2
9
CLOCK
10
C
C
Q3
6
Q10
14
Q11
15
Q12
1
RESET
11
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
MC14040B
6108
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
VDD = PIN 16
VSS = PIN 8

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

PIN ASSIGNMENT
Q12
16
VDD
Q6
15
Q11
Q5
14
Q10
Q7
13
Q8
Q4
12
Q9
Q3
11
Q2
10
VSS
Q1
MC14040B
6109

Characteristic
Symbol

TTLH, TTHL = (1.5 ns/pF) CL + 25 ns
tTLH,
tTHL

Clock to Q1
tPLH,
tPHL
Clock to Q12
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
260
115
80
520
230
160
5.0
10
15
1625
720
500
3250
1440
1000
Unit
ns
ns
ns

Reset to Qn
tPHL = (0.86 ns/pF) CL + 182 ns
tPHL
Clock Pulse Width
ns
5.0
10
15
370
155
115
740
310
230
tWH
5.0
10
15
385
150
115
140
55
38
ns
fcl
5.0
10
15
2.1
7.0
10.0
1.5
3.5
4.5
MHz
tTLH, tTHL
5.0
10
15
ns
No Limit
Reset Pulse Width
tWH
5.0
10
15
960
360
270
320
120
80
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
ns
VDD
VDD
500 F
0.01 F
CERAMIC
ID
PULSE
GENERATOR
C Q1
Q2
Q
R n
PULSE
GENERATOR
CL
CL
CL
CL
CLOCK
20 ns
90%
50%
10%
20 ns
20 ns
20 ns
VDD
VSS
50% DUTY CYCLE

and Waveform
MC14040B
6110
CL
CL
VSS
VSS
CLOCK
C Q1
Q2
Q
R n
tPLH
Q
90%
50%
10%
tWH
tPHL
90%
50%
10%
tTLH tTHL

and Waveforms
16
32
64
128
256
512
1024
2048
4096
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
TIMEBASE GENERATOR
A 60 Hz sinewave obtained through a 1.0 Megohm resistor
connected directly to a standard 120 Vac power line is
applied to the clock input of the MC14040B. By selecting
outputs Q5, Q10, Q11, and Q12 division by 3600 is accomplished. The MC14012B decodes the counter outputs,
produces a single output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute.
VDD
1.0 M
MC14040B
Q5
C
20 pF
Q10
120 Vac
60 Hz
Q11
R
1/2
MC14012B
1/2
MC14012B
1.0 PULSE/MINUTE
OUTPUT
Q12
VSS
MC14040B
6111
MOTOROLA
MC14042B
Quad Transparent Latch
L SUFFIX
CERAMIC
CASE 620
The MC14042B Quad Transparent Latch is constructed with MOS

monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity input.
Information present at the data input is transferred to outputs Q and Q during
the clock level which is determined by the polarity input. When the polarity
input is in the logic 0 state, data is transferred during the low clock level,
and when the polarity input is in the logic 1 state the transfer occurs during
the high clock level.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Buffered Data Inputs

Common Clock
Clock Polarity Control
Q and Q Outputs
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Vin, Vout
lin, lout
PD
Tstg
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA

Storage Temperature
PIN ASSIGNMENT
Q3
16
VDD
Q0
15
Q3
Q0
14
D3
13
D2
12
Q2
500
mW
D0
65 to + 150
_C
CLOCK
POLARITY
11
Q2
D1
10
Q1
VSS
Q1
TL
260
_C
LOGIC DIAGRAM
5
D0
4
CLOCK
POLARITY
LATCH
1
Q0
3
6
D1
7
LATCH
2
TRUTH TABLE
Q0
2
Q1
10
Clock
Polarity
0
1
1
0
0
0
1
1
Data
Latch
Data
Latch
Q1
9
D2
13
VDD = PIN 16
VSS = PIN 8
LATCH
3
Q2
11
Q2
12
D3
14
LATCH
4
Q3
1
Q3
15
MC14042B
6112

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14042B
6113

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time, D to Q, Q

tPLH,
tPHL
Propagation Delay Time, Clock to Q, Q

tPLH,
tPHL
Clock Pulse Width
tWH
tTLH,
tTHL
Hold Time
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
90
60
440
180
120
5.0
10
15
220
90
60
440
180
120
5.0
10
15
300
100
80
150
50
40
5.0
10
15
15
5.0
4.0
5.0
10
15
100
50
40
50
25
20
5.0
10
15
50
30
25
0
0
0
ns
no
ns
ns
th
Setup Time
Unit
ns
tsu
ns
VDD
1
f
16
20 ns
5
6
PULSE
GENERATOR 1
4
7
13
CLOCK
POLARITY
D0
D1
D2
14
D3
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
2
3
10
9
11
12
1
15
20 ns
90%
50%
DATA INPUT
tPLH
tPHL
90%
Q OUTPUT
For Power Dissipation test, each output

is loaded with capacitance CL.
VSS
tTHL
tPHL
90%
10%
50%
10%
tTLH
Q OUTPUT
10%
tTHL
50%
tTLH
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram

(Data to Output)
MC14042B
6114
VDD
16
PULSE
GENERATOR 1
PULSE
GENERATOR 2
7
13
14
NOTE: CL connected to output under test.
20* ns
CLOCK
POLARITY
D0
D1
D2
D3
8
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
2
3
10
9
11
12
1
15
VSS
20 ns
90%
50%
CLOCK INPUT
P.G. 1
10%
tWH
20 ns
90%
50%
DATA INPUT
P.G. 2
tsu
th
tPLH
Q OUTPUT
90%
50%
10%
* Input clock rise time is 20 ns except for maximum rise time test.
Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)
MC14042B
6115
MOTOROLA
MC14043B
MC14044B
CMOS MSI
Quad RS Latches
The MC14043B and MC14044B quad RS latches are constructed with
MOS Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. Each latch has an independent Q output and set and
reset inputs. The Q outputs are gated through threestate buffers having a
common enable input. The outputs are enabled with a logical 1 or high on
the enable input; a logical 0 or low disconnects the latch from the Q
outputs, resulting in an open circuit at the Q outputs.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648

ThreeState Outputs with Common Enable
Outputs Capable of Driving Two Lowpower TTL Loads or One Low
Power Schottky TTL Load Over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
MC14043B
S0
R0
S1
R1
S2
R2
S3
MC14044B
2
R0
Q0
3
S0
6
R1
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
10
Q2
S1
R2
11
S2
14
TRUTH TABLE
1
Q3
S R E
X X 0
High
Impedance
15
R3
5
ENABLE
0
0
1
1
0
1
0
1
1 No Change
1
0
1
1
1
1
X = Dont Care
MC14043B MC14044B
6116
R3
13
Q0
3
6
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
10
Q2
11
14
TRUTH TABLE
1
Q3
S R E
X X 0
High
Impedance
15
S3
5
ENABLE
0
0
1
1
0
1
0
1
1
0
1
1
1
0
1 No Change
X = Dont Care

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ThreeState Output Leakage

Current
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
Temperature Derating: Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages 12 mW/_C From 100_C To 125_C
MC14043B MC14044B
6117
v
v

Symbol
VDD
Vin, Vout
lin, lout
PD
Tstg
TL
Parameter
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA
DC Supply Voltage

Storage Temperature
500
mW
65 to + 150
_C
260
_C

to the range VSS
(Vin or Vout)
VDD.
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
175
75
60
350
175
120
tPHL
5.0
10
15
175
75
60
350
175
120
ns
Set, Set Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
ns
Reset, Reset Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
ns
Characteristic
Symbol
Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns
Output Fall Time
tTHL = (1.35 ns/pF) CL + 32.5 ns
tTLH

tPLH = (0.90 ns/pF) CL + 130 ns
tPHL = (0.90 ns/pF) CL + 130 ns
tPLH
Unit
ns
tTHL
ns
ns
ThreeState Enable/Disable Delay
tPLZ,
5.0
150
300
tPHZ,
10
80
160
tPZL,
15
55
110
tPZH
ns
AC WAVEFORMS
MC14043B
MC14044B
20 ns
50%
10%
VSS
20 ns
RESET
20 ns
VDD
90%
SET
20 ns
20 ns
SET
20 ns
50%
tPHL
10%
VSS
50%
RESET
tTLH
90%
50%
10%
tTLH
VOH
Q
50%
VOL
tTHL
90%
10%
VSS
VOH
VOL
tPLH
tPLH
MC14043B MC14044B
6118
VSS
20 ns
90% VDD
VDD
10%
10%
VDD
90%
20 ns
90%
tTHL
50%
tPHL
THREESTATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3State Tests
MC14043B
Test
tPZH
Enable
VDD
MC14044B
S1
S2
Open
Closed
VDD
VSS
VSS
VDD
tPZL
Closed
Open
VSS
VDD
VDD
VSS
tPHZ
Open
Closed
VDD
VSS
VSS
VDD
tPLZ
Closed
Open
VSS
VDD
VDD
VSS
S1
TO
OUTPUT
UNDER
TEST
1k
CL
50 pF
S2
VSS
VDD
ENABLE
50%
VSS
tPZH
VDD
90%
QA
10%
tPZL
tPHZ
VOL
tPLZ
VOH
QB
10%
VSS
PIN ASSIGNMENT
MC14043B
MC14044B
Q3
16
VDD
Q3
16
VDD
Q0
15
R3
NC
15
S3
R0
14
S3
S0
14
R3
S0
13
NC
R0
13
Q0
12
S2
12
R2
S1
11
R2
R1
11
S2
R1
10
Q2
S1
10
Q2
VSS
Q1
VSS
Q1
NC = NO CONNECTION
MC14043B MC14044B
6119
MOTOROLA
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a
voltagecontrolled oscillator (VCO), source follower, and zener diode. The
comparators have two common signal inputs, PCAin and PCBin. Input PCAin
can be used directly coupled to large voltage signals, or indirectly coupled
(with a series capacitor) to small voltage signals. The selfbias circuit
adjusts small voltage signals in the linear region of the amplifier. Phase
comparator 1 (an exclusive OR gate) provides a digital error signal PC1out,
and maintains 90 phase shift at the center frequency between PCAin and
PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading
edge sensing logic) provides digital error signals, PC2 out and LD, and
maintains a 0 phase shift between PCA in and PCB in signals (duty cycle is
immaterial). The linear VCO produces an output signal VCO out whose
frequency is determined by the voltage of input VCO in and the capacitor and
resistors connected to pins C1A, C1B, R1, and R2. The sourcefollower
output SFout with an external resistor is used where the VCO in signal is
needed but no loading can be tolerated. The inhibit input Inh, when high,
disables the VCO and source follower to minimize standby power
consumption. The zener diode can be used to assist in power supply
regulation.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltagetofrequency
conversion and motor speed control.
Buffered Outputs Compatible with MHTL and LowPower TTL

Supply Voltage Range = 3.0 to 18 V
Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited
Phase Comparator 2 switches on Rising Edges and is not Duty Cycle
Limited
BLOCK DIAGRAM
PCAin 14
SELF BIAS
CIRCUIT
PCBin 3
2 PC1out
PHASE
COMPARATOR 2
13 PC2out
1 LD
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
VCOin 9
VDD = PIN 16
VSS = PIN 8
SOURCE FOLLOWER
INH 5
VSS
MC14046B
6120
PHASE
COMPARATOR 1
4
11
12
6
7
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
LD
16
VDD
PC1out
15
ZENER
PCBin
14
PCAin
VCOout
13
PC2out
12
R2
INH
C1A
11
R1
C1B
10
SFout
VSS
VCOin
VCOout
R1
R2
C1A
C1B
10 SFout
15 ZENER

Rating
Symbol
DC Supply Voltage
Value
Unit
VDD
0.5 to + 18
Vdc
Input Voltage, All Inputs
Vin
0.5 to VDD + 0.5
Vdc
DC Input Current, per Pin
Iin
10
mAdc
PD
500
mW
TA
55 to + 125
_C
Tstg
65 to + 150
_C
Operating Temperature Range

Storage Temperature Range

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage #
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
1 Level
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Iin
Cin
15
0.1
0.00001
0.1
1.0
Adc
5.0
7.5
pF
Quiescent Current
(Per Package) Inh = PCAin = VDD,
Zener = VCOin = 0 V, PCBin = VDD
or 0 V, Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Total Supply Current

(Inh = 0, fo = 10 kHz, CL = 50 pF,
R1 = 1.0 M, R2 =
RSF = ,
and 50% Duty Cycle)
IT
5.0
10
15
Output Voltage
Vin = VDD or 0
Vin = 0 or VDD
Vdc
VIH
IOH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
mAdc
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Input Current
Input Capacitance
Vdc

mAdc
#Noise immunity specified for worstcase input combination.

Noise Margin for both 1 and 0 level = 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
To Calculate Total Current in General:
VCOin 1.65 VDD 1.35 3/4
VCOin 1.65 3/4
IT
2.2 x VDD
+ 1 x 103 (CL + 9) VDD f +
+
+ 1.6 x
RSF
R1
R2
1 x 101 VDD2
100% Duty Cycle of PCAin

100
+ IQ
where: IT in A, CL in pF, VCOin, VDD in Vdc, f in kHz, and

R1, R2, RSF in M, CL on VCOout.
MC14046B
6121
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25C)

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
VDD
Vdc
Minimum
Maximum
Device
Typical
Device
5.0
10
15
180
90
65
350
150
110
5.0
10
15
100
50
37
175
75
55
Units
ns
ns
PHASE COMPARATORS 1 and 2

Input Resistance PCAin
Rin
5.0
10
15
1.0
0.2
0.1
2.0
0.4
0.2
PCBin
Rin
15
150
1500
Minimum Input Sensitivity

AC Coupled PCAin
C series = 1000 pF, f = 50 kHz
Vin
5.0
10
15
200
400
700
300
600
1050
mV pp
DC Coupled PCAin, PCBin
5 to 15
fmax
5.0
10
15
0.5
1.0
1.4
0.7
1.4
1.9
MHz
Temperature Frequency Stability

(R2 = )
5.0
10
15
0.12
0.04
0.015
%/_C
Linearity (R2 = )
(VCOin = 2.5 V 0.3 V, R1 > 10 k)
(VCOin = 5.0 V 2.5 V, R1 > 400 k)
(VCOin = 7.5 V 5.0 V, R1 1000 k)
5.0
10
15
1.0
1.0
1.0
See Noise Immunity
VOLTAGE CONTROLLED OSCILLATOR (VCO)

Maximum Frequency
(VCOin = VDD, C1 = 50 pF
R1 = 5.0 k, and R2 = )
Output Duty Cycle
5 to 15
50
Input Resistance VCOin
Rin
15
150
1500
Offset Voltage
(VCOin minus SFout, RSF > 500 k)
5.0
10
15
1.65
1.65
1.65
2.2
2.2
2.2
Linearity
(VCOin = 2.5 V 0.3 V, RSF > 50 k)
(VCOin = 5.0 V 2.5 V, RSF > 50 k)
(VCOin = 7.5 V 5.0 V, RSF > 50 k)
5.0
10
15
0.1
0.6
0.8
SOURCEFOLLOWER
ZENER DIODE
Zener Voltage (Iz = 50 A)
VZ
6.7
7.0
7.3
Dynamic Resistance (Iz = 1.0 mA)
RZ
100
* The formula given is for the typical characteristics only.
MC14046B
6122
PHASE COMPARATOR 1
Input Stage
00
01
11
10
X X
PCAin
PCBin
PC1out
PHASE COMPARATOR 2
Input Stage
X X
PCAin
00
PCBin
01
00
10
10
00
01
01
10
11
11
11
PC2out
3State
Output Disconnected
LD
(Lock Detect)
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
v v
v v
v v
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
No signal on input PCAin.
VCO in PLL system adjusts to center

frequency (f0).
VCO in PLL system adjusts to minimum

frequency (fmin).
Phase angle between PCAin and PCBin.
90 at center frequency (f0), approaching 0_

and 180 at ends of lock range (2fL)
Always 0_ in lock (positive rising edges).
Locks on harmonics of center frequency.
Yes
No
Signal input noise rejection.
High
Low
Lock frequency range (2fL).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax fmin.
Capture frequency range (2fC).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Depends on lowpass filter characteristics
(see Figure 3). fC
fL
Center frequency (f0).
VCO output frequency (f).
Note: These equations are intended to be

a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than 20%.
fC = fL
The frequency of VCOout, when VCOin = 1/2 VDD

fmin =
fmax =
(VCO input = VSS)
R2(C1 + 32 pF)
1
R1(C1 + 32 pF)
+ fmin
(VCO input = VDD)
Where: 10K
R1
1M
10K
R2
1M
100pF
C1
.01 F
Figure 2. Design Information
MC14046B
6123
SOURCE
FOLLOWER
VCOin
PCAin
@ FREQUENCY f
PCBin
14
3
PHASE
2 OR 13
COMPARATOR PC1out
OR
PC2out
EXTERNAL
LOWPASS
FILTER
SFout
10
RSF
9
11
7
CIA
R1
VCOout
@ FREQUENCY Nf = f
VCO
6
12
CIB
R2
CI
EXTERNAL
N
COUNTER
Typical LowPass Filters

(a)
INPUT
R3
OUTPUT
C2
2fC
[p
2 p fL
R3 C2
(a)
INPUT
Typically:
R3
OUTPUT
R4 C2
R4
(R3
C2
6N
+ fmax
pD
Df
) 3, 000W) C2 + 100N
fmax2
R 4 C2
f = fmax fmin
NOTE: Sometimes R3 is split into two series resistors each R3 2. A capacitor CC is then placed from the midpoint to ground. The value for
CC should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the
damping, R4
(0.1)(R3) for optimum results.
LOWPASS FILTER
Filter A
Definitions: N = Total division ratio in feedback loop
K = VDD/ for Phase Comparator 1
K = VDD/4 for Phase Comparator 2
2 p D fVCO
KVCO
VDD 2 V
2 p fr
for a typical design n
(at phase detector input)
10
0.707
wn +
KfKVCO
NR3C2
Nw
z + 2K K n
f VCO
F(s)
wn +
KfKVCO
NC2(R3 R4)
z + 0.5 wn
+ R3C21S ) 1
Filter B
) KfKNVCO)
R3C2S ) 1
F(s) +
S(R3C2 ) R4C2) ) 1
(R3C2
Waveforms
Phase Comparator 1
PCAin
Phase Comparator 2
VDD
VSS
VDD
PCAin
VSS
VOH
VOH
PCBin
PC1out
VCOin
VOL
VOH
VOL
VOH
PCBin
VOL
VOH
LD
VOL
VOH
PC2out
VOL
VOH
VOL
VCOin
VOL
Note: for further information, see:
(1) F. Gardner, PhaseLock Techniques, John Wiley and Son, New York, 1966.
(2) G. S. Moschytz, Miniature RC Filters Using PhaseLocked Loop, BSTJ, May, 1965.
(3) Garth Nash, PhaseLock Loop Design Fundamentals, AN535, Motorola Inc.
(4) A. B. Przedpelski, PhaseLocked Loop Design Articles, AR254, reprinted by Motorola Inc.
Figure 3. General PhaseLocked Loop Connections and Waveforms
MC14046B
6124
MOTOROLA
MC14049B
MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex
Buffer are constructed with MOS PChannel and NChannel enhancement
mode devices in a single monolithic structure. These complementary MOS
devices find primary use where low power dissipation and/or high noise
immunity is desired. These devices provide logic level conversion using only
one supply voltage, VDD.
The inputsignal high level (VIH) can exceed the VDD supply voltage for
logic level conversions. Two TTL/DTL loads can be driven when the devices
are used as a CMOStoTTL/DTL converter (VDD = 5.0 V, VOL
0.4 V,
IOL 3.2 mA).
Note that pins 13 and 16 are not connected internally on these devices;
consequently connections to these terminals will not affect circuit operation.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
High Source and Sink Currents

HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
VIN can exceed VDD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
MAXIMUM RATINGS1 (Voltages Referenced to VSS)

Characteristic
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
Symbol
Value
Unit
VDD
VIN
0.5 to + 18.0
Vdc
0.5 to + 18.0
Vdc
0.5 to VDD + 0.5
Vdc
Input Current (DC or Transient), per Pin
Vout
Iin
10
mA
VDD
16
NC
Output Current (DC or Transient), per Pin
Iout
+ 45
mA
OUTA
15
OUTF
mW
INA
14
INF
OUTB
13
NC
INB
12
OUTE
OUTC
11
INE
INC
10
OUTD
VSS
DC Supply Voltage
Input Voltage (DC or Transient)
Output Voltage (DC or Transient)
Power Dissipation, per Package2

(Plastic/Ceramic)
(SOIC)
PD
Storage Temperature
Tstg
825
740
_C
65 to + 150
Lead Temperature (8 Second Soldering)

TL
260
_C
1Maximum Ratings are those values beyond which damage to the device may occur.
2Temperature Derating: See Figure 3.
LOGIC DIAGRAM
MC14049B
2
10
10
11
12
11
12
14
15
14
15
IND
MC14050B
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
PIN ASSIGNMENT
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
MC14049B MC14050B
6125

Characteristic
Output Voltage
Vin = VDD
Symbol
+ 25_C
+ 125_C
Min
Max
Min
Typ1
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
10
15
1.6
1.6
4.7
1.25
1.30
3.75
2.5
2.6
10
1.0
1.0
3.0
IOL
5.0
10
15
3.75
10
30
3.2
8.0
24
6.0
16
40
2.6
6.6
19
mAdc
Iin
15
0.1
0.00001
0.1
1.0
Adc
Vin = 0
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
55_C
VDD
Vdc
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Input Current
mAdc
Input Capacitance (Vin = 0)
Cin
10
20
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
Total Supply Current 2,3

per package)
buffers switching
IT
5.0
10
15

Adc
1 Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
2 The formulas given are for the typical characteristics only at + 25_C
3 To calculate total supply current at loads other than 50 pF:
Where: IT is in A (per Package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency and k = 0.002.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields
referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high-impedance circuit. For proper operation, the ranges VSS
Vin
18 V and VSS
Vout
VDD are
recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be
left open.
MC14049B MC14050B
6126
AC SWITCHING CHARACTERISTICS1 (CL = 50 pF, TA = + 25_C)

Characteristic
Symbol
Output Rise Time

tTLH = (0.25 ns/pF) CL + 37.5 ns
tTLH
Output Fall Time

tTHL

tPLH = (0.33 ns/pF) CL + 63.5 ns
tPLH = (0.19 ns/pF) CL + 30.5 ns
tPLH
VDD
Vdc
Min
Typ2
Max
5.0
10
15
100
50
40
160
80
60
5.0
10
15
40
20
15
60
40
30
5.0
10
15
80
40
30
140
80
60
Unit
ns
ns
ns

tPHL
5.0
40
80
10
20
40
tPHL = (0.05 ns/pF) CL + 12.5 ns
15
15
30
1 The formulas given are for the typical characteristics only at 25_C.
2 Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
MC14049B
VDD
1
MC14050B
VDD
1
IOH
MC14049B
VDD
1
IOL
VOH
8
VSS
VSS
VDS = VOH VDD
IOH
VOL
VSS
VOH
VSS
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
0
I OH , OUTPUT SOURCE CURRNT (mAdc)
MC14050B
VDD
1
IOL
VOL
ns
VGS = 5.0 Vdc
10
VGS = 15 Vdc
120
20
VGS = 10 Vdc
30
40
VGS = 15 Vdc
50
10
MAXIMUM CURRENT LEVEL
8.0
6.0
4.0
2.0
VGS = 10 Vdc
80

40
VGS = 5.0 Vdc
0
2.0
4.0
6.0
8.0
10
MC14049B MC14050B
6127
PD , MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE
1200
1100
1000
900
825
800
740
700
600
(L) CERAMIC
(P) PDIP
500
400
300
(D) SOIC
200
100
0
25
50
260 mW (L)
175 mW (P)
120 mW (D)
75
100
125
TA, AMBIENT TEMPERATURE (C)
150
175
Figure 3. Ambient Temperature Power Derating
20 ns
20 ns
VDD
10%
#
Vin
Vout
VSS
# Invert on MC14049B only
CL
VOH
90%
50%
10%
OUTPUT
MC14049B
VSS
tPLH
tPHL
1
PULSE
GENERATOR
VDD
90%
50%
INPUT
tPLH
tTHL
tPHL
tTLH
tPHL
90%
50%
OUTPUT
MC14050B
10%
tTLH
VOL
VOH
VOL
tTHL
MC14049B MC14050B
6128
MOTOROLA
MC14049UB
Hex Buffers
L SUFFIX
CERAMIC
CASE 620
The MC14049UB hex inverter/buffer is constructed with MOS Pchannel

This complementary MOS device finds primary use where low power
dissipation and/or high noise immunity is desired. This device provides
logiclevel conversion using only one supply voltage, VDD. The inputsignal
high level (V IH ) can exceed the V DD supply voltage for logiclevel
conversions. Two TTL/DTL Loads can be driven when the device is used as
CMOStoTTL/DTL converters (VDD = 5.0 V, VOL
0.4 V, IOL 3.2 mA).
Note that pins 13 and 16 are not connected internally on this device;
consequently connections to these terminals will not affect circuit operation.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
High Source and Sink Currents

HightoLow Level Converter
Meets JEDEC UB Specifications
VIN can exceed VDD
Improved ESD Protection on All Inputs

Rating
Symbol
Value
Unit
VDD
0.5 to + 18
Vin
0.5 to + 18
Vout
0.5 to VDD + 0.5
Iin
10
mA
Iout
+ 45
mA

Plastic/Ceramic
SOIC
PD
Storage Temperature
Tstg
65 to + 150
_C
TL
260
_C
DC Supply Voltage
mW
825
740
Temperature Derating: All Packages: See Figure 4.
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
MC14049UB
VDD
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
MC14049UB
3
10
11
12
14
15
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
VSS
MC14049UB
6129

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
10
15
1.6
1.6
4.7
1.25
1.3
3.75
2.5
2.6
10
1.0
1.0
3.0
IOL
5.0
10
15
3.75
10
30
3.2
8.0
24
6.0
16
40
2.6
6.6
19
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
10
20
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14049UB
6130

Characteristic
Symbol
Output Rise Time

tTLH = (0.27 ns/pF) CL + 26.5 ns
tTLH
Output Fall Time

tTHL

tPLH = (0.11 ns/pF) CL + 24.5 ns
tPLH

tPHL = (0.12 ns/PF) CL + 9 ns
tPHL = (0.11 ns/pF) CL + 4.5 ns
tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
160
100
60
5.0
10
15
40
20
15
60
40
30
5.0
10
15
80
40
30
120
65
50
5.0
10
15
30
15
10
60
30
20
Unit
ns
ns
ns
ns
18
15
10
VDD = 15 Vdc
VDD = 10 Vdc
55C
VDD = 5 Vdc
+125C
5
10
15
18
Figure 1. Typical Voltage Transfer Characteristics versus Temperature
MC14049UB
6131
VDD
1
VDD
1
IOH
8
IOL
VOH
8
VSS
VDS = VOH VDD
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
I OH , OUTPUT SOURCE CURRNT (mAdc)
VOL
VSS
VGS = 5.0 Vdc
10
VGS = 15 Vdc
120
20
VGS = 10 Vdc
30
40
VGS = 15 Vdc
50
10
8.0
6.0
4.0
2.0
VGS = 10 Vdc
80

40
VGS = 5.0 Vdc
0
2.0
4.0
6.0
8.0
10

VDD
PD , MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE
1
PULSE
GENERATOR
1200
1100
1000
Vout
Vin
8
900
825
800
740
700
600
20 ns
(L) CERAMIC
INPUT
(P) PDIP
CL
VSS
20 ns
VDD
90%
50%
500
400
10%
300
(D) SOIC
200
100
0
25
50
75
100
125
260 mW (L)
175 mW (P)
120 mW (D)
150
175
This device contains circuitry to protect the inputs against damage

due to high static voltages or electric fields referenced to the VSS pin,
only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high-impedance circuit. For proper operation, the ranges VSS Vin 18 V and VSS Vout VDD
are recommended.
VSS
tPHL
OUTPUT
tPLH
VOH
90%
50%
10%
tTHL
tTLH
VOL

and Waveforms
PIN ASSIGNMENT
VDD
16
NC
OUTA
15
OUTF
INA
14
INF
OUTB
13
NC
12
OUTE
INB
OUTC
11
INE
INC
10
OUTD
VSS
IND
NC = NO CONNECTION
MC14049UB
6132
MOTOROLA
MC14051B
Analog
MC14052B
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitallycontrolled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage
range can be achieved.
MC14053B
L SUFFIX
CERAMIC
CASE 620
Triple Diode Protection on Control Inputs

Switch Function is Break Before Make
Analog Voltage Range (VDD VEE) = 3.0 to 18 V
Note: VEE must be
VSS
Lownoise 12 nV/Cycle, f 1.0 kHz Typical
PinforPin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower RON, Use the HC4051, HC4052, or HC4053 HighSpeed
CMOS Devices
P SUFFIX
PLASTIC
CASE 648
MAXIMUM RATINGS*
Symbol
VDD
Vin, Vout
Iin
Parameter
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
10
mA
25
mA
500
mW
65 to + 150
_C
DC Supply Voltage (Referenced to VEE,

VSS VEE)

(Referenced to VSS for Control Inputs and
VEE for Switch I/O)
per Control Pin
Isw
PD
Tstg
Storage Temperature
Power Dissipation. per Package
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TL
260
_C
Temperature Derating: P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
MC14051B
8Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
6
11
10
9
13
14
15
12
1
5
2
4
INHIBIT
A
B
C
X0
X1
X
3
X2
COMMON
X3
OUT/IN
X4
X5
X6
X7
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
MC14052B
Dual 4Channel Analog
CONTROLS
SWITCHES
IN/OUT
6
10
9
12
14
15
11
1
5
2
4
INHIBIT
A
X
B
X0
X1
X2
X3
Y0
Y
Y1
Y2
Y3
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
CONTROLS
13
COMMONS
OUT/IN
3
MC14053B
Triple 2Channel Analog
SWITCHES
IN/OUT
6
11
10
9
12
13
2
1
5
3
INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1
14
15
COMMONS
OUT/IN
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be VSS.
MC14051B MC14052B MC14053B

6133
v
v
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage
Range
VDD
VDD 3.0 VSS VEE
3.0
18
3.0
18
3.0
18
Quiescent Current Per

Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VEE VI/O
VDD, and
Vswitch
500 mV**
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
ID(AV)
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus
Quiescent, Per Package
(0.07 A/kHz) f + IDD

Typical
CONTROL INPUTS INHIBIT, A, B, C (Voltages Referenced to VSS)

LowLevel Input Voltage
VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
HighLevel Input Voltage
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Input Leakage Current
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN X, Y, Z (Voltages Referenced to VEE)

Recommended
PeaktoPeak Voltage
Into or Out of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
VPP
Recommended Static or
Dynamic Voltage Across
the Switch** (Figure 5)
Vswitch
Channel On
600
600
300
mV
Output Offset Voltage
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
5.0
10
15
Vswitch
500 mV**,
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

(Control) Channel to
Channel or Any One
Channel
100
0.05
100
1000
nA
Capacitance, Switch I/O
CI/O
Inhibit = VDD
10
pF
Capacitance, Common O/I
CO/I
Inhibit = VDD
(MC14051B)
(MC14052B)
(MC14053B)
60
32
17
Pins Not Adjacent

Pins Adjacent
0.15
0.47
ON Resistance Between
Any Two Channels in the
Same Package
OffChannel Leakage
Current (Figure 10)
Capacitance, Feedthrough
(Channel Off)
CI/O
pF
pF
#Data labeled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential performance.
* For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
MC14051B MC14052B MC14053B

6134
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE

Characteristic
Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 k)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
MC14052
VSS unless otherwise indicated)

VDD VEE
Typ #
Vdc
All Types
Symbol
Unit
ns
5.0
10
15
35
15
12
90
40
30
5.0
10
15
30
12
10
75
30
25
5.0
10
15
25
8.0
6.0
65
20
15
ns
MC14053
Inhibit to Output (RL = 10 k, VEE = VSS)

Output 1 or 0 to High Impedance, or
High Impedance to 1 or 0 Level
MC14051B
Max
tPLH, tPHL
ns
tPHZ, tPLZ,
tPZH, tPZL
ns
5.0
10
15
350
170
140
700
340
280
MC14052B
5.0
10
15
300
155
125
600
310
250
ns
MC14053B
5.0
10
15
275
140
110
550
280
220
ns
5.0
10
15
360
160
120
720
320
240
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
ns
10
0.07
BW
10
17
MHz
10
50
dB
Channel Separation (Figure 8)

(RL = 1 k, Vin = 1/2 (VDDVEE) pp,
fin = 3.0 MHz
10
50
dB
Crosstalk, Control Input to Common O/I (Figure 9)

(R1 = 1 k, RL = 10 k
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
10
75
mV
Control Input to Output (RL = 10 k, VEE = VSS)

MC14051B
Second Harmonic Distortion

(RL = 10K, f = 1 kHz) Vin = 5 VPP
Bandwidth (Figure 7)
(RL = 1 k, Vin = 1/2 (VDDVEE) pp, CL = 50pF
20 Log (Vout/Vin) = 3 dB)
Off Channel Feedthrough Attenuation (Figure 7)
RL = 1K, Vin = 1/2 (VDD VEE) pp
fin = 4.5 MHz MC14051B
fin = 30 MHz MC14052B
tPLH, tPHL
ns
#Data labelled Typ is not lo be used for design purposes but In intended as an indication of the ICs potential performance.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs
must be left open.
MC14051B MC14052B MC14053B

6135
VDD
VDD V
DD
OUT/IN
IN/OUT
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE
16
Control Inputs
ON Switches
Select
Inhibit
C*
MC14051B
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
None
MC14052B
Y0
Y1
Y2
Y3
X0
X1
X2
X3
MC14053B
Z0
Z0
Z0
Z0
Y0
Y0
Y1
Y1
X0
X1
X0
X1
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
None
None
* Not applicable for MC14052

x = Dont Care
16
INH
A
B
C
6
11
10
9
VDD
8
X0 13
X1 14
VSS
VEE
X2 15
X3 12
3 X
X4 1
X5 5
X6 2
X7 4
Figure 2. MC14051B Functional Diagram
VDD
16
INH 6
BINARY TO 1OF4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
A 10
B 9
8
X0 12
X1 14
VSS
BINARY TO 1OF8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INH
A
B
C
VEE
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
MC14051B MC14052B MC14053B

6136
6
11
10
9
BINARY TO 1OF2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
8
13 X
VDD
VSS
VEE
X0 12
14 X
X1 13
Y0 2
3 Y
15 Y
Y1 1
Z0 5
4 Z
Z1 3
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
Vout
LOAD
V
INH
CL
RL
SOURCE
VDD VEE
VEE VDD
Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON or OFF

the switch under test.
RL
A
B
C
VSS
Vout
INH
RL
A
B
C
ON
INH
OFF
CL = 50 pF
Vout
RL
Vin
VDD VEE
2
VDD VEE
2
Figure 7. Bandwidth and OffChannel

Feedthrough Attenuation
CL = 50 pF
Vin
Figure 8. Channel Separation

(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST
A
B
C
Vout
RL
INH
CONTROL
SECTION
OF IC
VDD
VEE
OTHER
CHANNEL(S)
VEE
VDD
CL = 50 pF
R1
COMMON
VEE
VDD
Figure 9. Crosstalk, Control Input to

Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 on Page 651.
MC14051B MC14052B MC14053B

6137
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
XY
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
300
300
250
200
150
TA = 125C
100
25C
55C
50
0
10
RON , ON RESISTANCE (OHMS)
R ON , ON RESISTANCE (OHMS)
350
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
250
200
150
25C
55C
50
0
10
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = 7.5 V
700
350
600
300
500
400
300
TA = 125C
200
25C
100
0
10
TA = 125C
100
10
TYPICAL RESISTANCE CHARACTERISTICS

350
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
10
TA = 25C
250
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
0
10
10
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 15. Comparison at 25C, VDD = VEE
10
PIN ASSIGMENT
MC14051B
MC14052B
MC14053B
X4
16
VDD
Y0
16
VDD
Y1
16
VDD
X6
15
X2
Y2
15
X2
Y0
15
14
X1
14
X1
Z1
14
X7
13
X0
Y3
13
13
X1
X5
12
X3
Y1
12
X0
Z0
12
X0
INH
11
INH
11
X3
INH
11
VEE
10
VEE
10
VEE
10
VSS
VSS
VSS
MC14051B MC14052B MC14053B

6138
Figure A illustrates use of the onchip level converter detailed in Figures 2, 3, and 4. The 0to5 V Digital Control signal is used to directly control a 9 Vpp analog signal.
V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at
the control inputs; V SS = GND = 0 V = logic low.
The maximum analog signal level is determined by V DD
and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the
maximum swing below V SS. For the example, V DD V SS =
5 V maximum swing above V SS ; V SS V EE = 5 V maximum
swing below VSS. The example shows a 4.5 V signal which
allows a 1/2 volt margin at each peak. If voltage transients
above V DD and/or below V EE are anticipated on the analog

channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
and V EE is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
V DD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to V EE. For example, V DD = + 10 V,
V SS = + 5 V, and V EE 3 V is acceptable. See the Table
below.
+5 V
5 V
VDD
VSS
VEE
+ 4.5 V
9 Vpp
ANALOG SIGNAL
SWITCH
I/O
MC14051B
MC14052B
MC14053B
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
0TO5 V DIGITAL
COMMON
O/I
9 Vpp
ANALOG SIGNAL
GND
4.5 V
INHIBIT,
A, B, C
CONTROL SIGNALS

VDD
VDD
DX
DX
ANALOG
I/O
COMMON
O/I
DX
DX
VEE
VEE
POSSIBLE SUPPLY CONNECTIONS

VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
+8
+ 8/0
+ 8 to 8 = 16 Vpp
+5
12
+ 5/0
+ 5 to 12 = 17 Vpp
+5
+ 5/0
+ 5 to 0 = 5 Vpp
+5
+ 5/0
+ 5 to 5 = 10 Vpp
+ 10
+5
+ 10/ + 5
+ 10 to 5 = 15 Vpp
Maximum Analog Signal Range

In Volts
MC14051B MC14052B MC14053B

6139
MOTOROLA
MC14060B
14-Bit Binary Counter and
Oscillator
L SUFFIX
CERAMIC
CASE 620
The MC14060B is a 14stage binary ripple counter with an onchip

oscillator buffer. The oscillator configuration allows design of either RC or
crystal oscillator circuits. Also included on the chip is a reset function which
places all outputs into the zero state and disables the oscillator. A negative
transition on Clock will advance the counter to the next state. Schmitt trigger
action on the input line permits very slow input rise and fall times.
Applications include time delay circuits, counter controls, and frequency
dividing circuits.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Fully static operation

Buffered Outputs Available from Stages 4 Through 10 and
12 Through 14
Common Reset Line
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TRUTH TABLE
Clock
Reset
Output State
L
L
H
No Change
Advance to next state
All Outputs are low
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Q12
16
VDD
Q13
15
Q10
Q14
14
Q8
Q6
13
Q9
Q5
12
RESET
Q7
11
CLOCK
Q4
10
OUT 1
VSS
OUT 2
X = Dont Care
LOGIC DIAGRAM
OUT 2
9
Q4
OUT 1
Q5
7
10
Q12
1
Q13
2
Q14
3
CLOCK
11
C
C
RESET
12
Q6 = PIN 4
Q7 = PIN 6
MC14060B
6140
Q8 = PIN 14
Q9 = PIN 13
Q10 = PIN 15
VDD = PIN 16
VSS = PIN 8
v
v

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Symbol
VDD
Vdc
55_C
Min
Max
Min
25_C
Typ #
Max
125_C
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Input Voltage
(VO = 4.5 or 0.5 V)
(VO = 9.0 or 1.0 V)
(VO = 13.5 or 1.5 V)
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
(VO = 0.5 or 4.5 V)

(VO = 1.0 or 9.0 V)
(VO = 1.5 or 13.5 V)
1 Level
VIH
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
Input Voltage
0 Level
(VO = 4.5 Vdc)
(For Input 11
(VO = 9.0 Vdc) and Output 10)
(VO = 13.5 Vdc)
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mA
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
IT
5.0
10
15
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
1 Level
VIH

(VOH = 2.5 V)
(Except Source
(VOH = 4.6 V)
Pins 9 and 10)
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Sink

Per Package)
(CL = 50 pF on all outputs,
all buffers switching)
Vdc
Vdc
mA

# Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
MC14060B
6141

Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time (Counter Outputs)
tTLH
5.0
10
15
40
25
20
200
100
80
ns
Output Fall Time (Counter Outputs)
tTHL
5.0
10
15
50
30
20
200
100
80
ns

Clock to Q4
tPLH
tPHL
5.0
10
15
415
175
125
740
300
200
ns
5.0
10
15
1.5
0.7
0.4
2.7
1.3
1.0
twH
5.0
10
15
100
40
30
65
30
20
ns
5.0
10
15
5
14
17
3.5
8
12
MHz
tTLH
tTHL
5.0
10
15
tw
5.0
10
15
120
60
40
40
15
10
5.0
10
15
170
80
60
350
160
100
Clock to Q14
Clock Pulse Width
Reset Pulse Width

Reset to On
tPHL
ns
No Limit
ns
ns
VDD
VDD
500 F
PULSE
GENERATOR
NC
NC
Q4
OUT1 Q5
OUT2 Qn
R
20 ns
NC
NC
90%
50%
10%
Q4
OUT1 Q5
OUT2
Qn
R
CL
VSS
CL
CL
CL
20 ns
CL
CL
20 ns
90%
50%
10%
CLOCK
20 ns
tPLH
VDD
VSS
50% DUTY CYCLE

and Waveform
MC14060B
6142
CLOCK
CLOCK
VSS
CLOCK
PULSE
GENERATOR
0.01 F
ID
Q
tTLH
tWH
tPHL
90%
50%
10%
tTHL

and Waveforms
CLOCK 11
f
10 OUT 1
RESET
if 1 kHz f 100 kHz

and 2Rtc < RS < 10Rtc
(f in Hz, R in ohms, C in farads)
9 OUT 2
Rtc
RS
[ 2.3 R1tcCtc
The formula may vary for other frequencies. Recommended

maximum value for the resistors in 1 M.
Ctc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS

100
VDD = 15 V
4.0
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
8.0
0
1.0 V
4.0
8.0
5.0 V
12
RTC = 56 k
C = 1000 pF
16
55
25
100
CLOCK
11
5
2
1
0.5
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
125
0.1
1.0 k
10 k
100 k
RTC, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (F)
10 OUT 1
9 OUT 2
18M
RO
CT
Figure 6. Typical Crystal Oscillator Circuit
1.0 M
0.1
Figure 5. RC Oscillator Frequency as a

Function of RTC and C
500 kHz
Circuit
32 kHz
Circuit
Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
32
6.2
kHz
k
External Resistor/Capacitor Values

RO
CT
CS
47
82
20
750
82
20
k
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
+ 100
+ 120
ppm
160
560
ppm
Characteristic
RESET
CS
10
0.0001
Figure 4. RC Oscillator Stability
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
0.2
RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
VDD = 10 V
50
Frequency Stability
Frequency Changes as a Function
of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
Frequency Change as a Function
of Temperature (VDD = 10 V)
TA Change from 55_C to
+ 25_C Complete Oscillator*
TA Change from + 25_C to
+ 125_C Complete Oscillator*
* Complete oscillator includes crystal, capacitors, and resistors.
Figure 7. Typical Data for Crystal Oscillatgor Circuit
MC14060B
6143
MOTOROLA

MC14066B
Quad Analog Switch/Quad
Multiplexer
L SUFFIX
CERAMIC
CASE 632
The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switch is useful
in signal gating, chopper, modulator, demodulator and CMOS logic
implementation.
The MC14066B is designed to be pinforpin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings as
large as the full supply voltage can be controlled via each independent
control input.
D SUFFIX
SOIC
CASE 751A
Triple Diode Protection on All Control Inputs

Low Noise 12 nV/Cycle, f 1.0 kHz typical
PinforPin Replacement for CD4016, CD4016, MC14016B
For Lower RON, Use The HC4066 HighSpeed CMOS Device

Symbol
VDD
Vin, Vout
Parameter
DC Supply Voltage
P SUFFIX
PLASTIC
CASE 646
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
Iin
Input Current (DC or Transient), per

Control Pin
10
mA
Isw
25
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
260
_C
* Maximum Ratings are those values beyond which damage to the may occur.
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
CONTROL 1
13
2
OUT 1
1
IN 1
5
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
CIRCUIT SCHEMATIC
IN 4
3
OUT 2
4
6
9
8
OUT 3
12
10
11
OUT 4
VDD = PIN 14
VSS = PIN 7
VDD VDD
VDD
LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)
VSS
VDD
CMOS
INPUT
VDD
OUT/IN
CONTROL
VDD
300
VSS
MC14066B
6144
VDD
IN/OUT
Control
Switch
0 = VSS
OFF
1 = VDD
ON
Logic Diagram Restrictions

VSS Vin VDD
VSS Vout VDD
VSS
v
v
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
3.0
18
3.0
18
3.0
18
0.25
0.5
1.0
0.005
0.010
0.015
0.25
0.5
1.0
7.5
15
30

Range
VDD

Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
Vswitch
500 mV**
ID(AV)
5.0
10
15
TA = 25_C only The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus Quiescent,
Per Package
Typical

CONTROL INPUTS (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN AND OUT (Voltages Referenced to VSS)

Recommended Peakto
Peak Voltage Into or Out
of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
5.0
10
15
Vswitch
500 mV**,
Vin = VIL or VIH
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Switch Off
10
15
pF
(Switch Off)
CI/O
0.47
pF
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 6)
** For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
MC14066B
6145
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C unless otherwise noted.)

Characteristic
Propagation Delay Times

Input to Output (RL = 10 k)
Symbol
VSS = 0 Vdc
Control to Output (RL = 1 k) (Figure 2)

Output 1 to High Impedance
VDD
Vdc
Min
Typ #
Max
Unit
tPLH, tPHL
ns
5.0
10
15
20
10
7.0
40
20
15
5.0
10
15
40
35
30
80
70
60
tPHZ
ns
tPLZ
5.0
10
15
40
35
30
80
70
60
ns
High Impedance to Output 1
tPZH
5.0
10
15
60
20
15
120
40
30
ns
High Impedance to Output 0
tPZL
5.0
10
15
60
20
15
120
40
30
ns

VSS = 5 Vdc
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)
5.0
0.1
Bandwidth (Switch ON) (Figure 3)

VSS = 5 Vdc
(RL = 1 k, 20 Log (Vout/Vin) = 3 dB, CL = 50 pF,
Vin = 5 Vpp)
5.0
65
MHz
Feedthrough Attenuation (Switch OFF)

VSS = 5 Vdc
(Vin = 5 Vpp, RL = 1 k, fin = 1.0 MHz) (Figure 3)
5.0
50
dB

(Vin = 5 Vpp, RL = 1 k, fin = 8.0 MHz)
(Switch A ON, Switch B OFF)
VSS = 5 Vdc
5.0
50
dB
Crosstalk, Control Input to Signal Output (Figure 5)

VSS = 5 Vdc
(R1 = 1 k, RL = 10 k, Control tTLH = tTHL = 20 ns)
5.0
300
mVpp

MC14066B
6146
PIN ASSIGNMENT
IN 1
14
VDD
OUT 1
13
CONTROL 1
OUT 2
12
CONTROL 4
IN 2
11
IN 4
CONTROL 2
10
OUT 4
CONTROL 3
OUT 3
VSS
IN 3
TEST CIRCUITS
Vout
VC
RL
ON SWITCH
CONTROL
SECTION
OF IC
20 ns
Vout
VSS
tPHZ
90%
tPZL
tPLZ
90%
Vin = VDD
Vx = VSS
10%
Vout
SOURCE
VDD
tPZH
LOAD
V
Vx
Vin
90%
50%
10%
VC
CL
Vin = VSS
Vx = VDD
10%

and Waveforms
VDD VSS
2
VC = VDD FOR BANDWIDTH TEST

VC = VSS FOR FEEDTHROUGH TEST
Vin
VDD VSS
2
VDD
Vin
RL
CL
RL
CL
Vout
RL
CL
VC
VSS
VDD VSS
Figure 3. Bandwidth and


VDD
Vin
Vout
1k
RL
10 k
CL = 50 pF
VSS
CONTROL
SECTION
OF IC
VSS
VDD
VC = 5.0 V TO + 5.0 V SWING
Figure 5. Crosstalk,
Control to Output
MC14066B
6147
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
XY
PLOTTER
VSS
350
300
300
250
200
150
100
25C
55C
50
0
10
TA = 125C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
350
250
200
150
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
Figure 8. VDD = 7.5 V, VSS = 7.5 V
350
600
300
500
400
300
TA = 125C
200
25C
100
55C
8.0 6.0 4.0 2.0
MC14066B
6148
25C
50
700
0
10
TA = 125C
100
0
10
10
0.2
4.0
6.0
8.0
10
8.0
10
TA = 25C
250
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
0
10
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 11. Comparison at 25C, VDD = VSS
10
Figure A illustrates use of the Analog Switch. The 0
to5 volt digital control signal is used to directly control a
5 volt peaktopeak analog signal.
V SS. The V DD voltage is the logic high voltage, the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at
and VSS. The analog voltage must not swing higher than V DD
or lower than V SS.
The example shows a 5 volt peaktopeak signal which
allows no margin at either peak. If voltage transients above

V DD and/or below V SS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in
Figure B. These diodes should be small signal types able to
absorb the maximum anticipated current surges during
clipping.
and V SS is 18.0 volts. Most parameters are specified up to
15 volts which is the recommended maximum difference
between V DD and V SS.
+5 V
VDD
VSS
+ 5.0 V
5 Vpp
ANALOG SIGNAL
SWITCH
IN
SWITCH
OUT
+5 V
5 Vpp
ANALOG SIGNAL
+ 2.5 V
GND
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
0TO5 V DIGITAL
MC14066B
CONTROL SIGNALS
VDD
VDD
DX
DX
SWITCH
IN
SWITCH
OUT
DX
VSS
DX
VSS
MC14066B
6149
MOTOROLA
MC14067B
MC14097B
Analog
Multiplexers/Demultiplexers
The MC14067 and MC14097 multiplexers/demultiplexers are digitally
controlled analog switches featuring low ON resistance and very low
leakage current. These devices can be used in either digital or analog
applications.
The MC14067 is a 16channel multiplexer/demultiplexer with an inhibit
and four binary control inputs A, B, C, and D. These control inputs select
1of16 channels by turning ON the appropriate analog switch (see
MC14067 truth table.)
The MC14097 is a differential 8channel multiplexer/demultiplexer with an
inhibit and three binary control inputs A, B, and C. These control inputs
select 1 of 8 pairs of channels by turning ON the appropriate analog switches
(see MC14097 truth table).
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
Low OFF Leakage Current

Matched Channel Resistance
Low Quiescent Power Consumption
Low Crosstalk Between Channels
Wide Operating Voltage Range: 3 to 18 V
Low Noise
Pin for Pin Replacement for CD4067B and CD4097B
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14067B
16Channel Analog
CONTROLS
SWITCHES
IN/OUT
15
10
11
14
13
9
8
7
6
5
4
3
2
23
22
21
20
19
18
17
16
INHIBIT
A
B
C
D
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
MC14067B MC14097B
6150
Plastic
Ceramic
SOIC
MC14097B
Dual 8Channel Analog
CONTROLS
13
10
11
14
INHIBIT
A
B
C
SWITCHES
IN/OUT
9
8
7
6
5
4
3
2
23
22
21
20
19
18
16
15
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
COMMON
1
OUT/IN
VDD = PIN 24
VSS = PIN 12
COMMONS
OUT/IN
17

Symbol
VDD
Parameter
DC Supply Voltage
Vin, Vout
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
mA
Iin

per Control Pin
10
Isw
25
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

to the range VSS
(Vin or Vout)
VDD.
MC14067 TRUTH TABLE

Control Inputs
MC14097 TRUTH TABLE

Control Inputs
Inh
Selected
Channel
Inh
X
0
1
0
X
0
0
1
X
0
0
0
X
0
0
0
1
0
0
0
None
X0
X1
X2
X
0
1
0
X
0
0
1
X
0
0
0
1
0
0
0
X0
X1
X2
Y0
Y1
Y2
1
0
1
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
X3
X4
X5
X6
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
X7
X8
X9
X10
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
X3
X4
X5
X6
X7
Y3
Y4
Y5
Y6
Y7
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X11
X12
X13
X14
X15
INHIBIT
A
B
C
D
X
IN/OUT
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
MC14097 FUNCTIONAL DIAGRAM
CONTROL
INPUTS
1OF16 DECODER
None
X = Dont Care
MC14067 FUNCTIONAL DIAGRAM
CONTROL
INPUTS
Selected
Channels
X
IN/OUT
X
OUT/IN
Y
IN/OUT
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1OF8 DECODER
X
OUT/IN
Y
OUT/IN
MC14067B MC14097B
6151
v
v
25_C
55C
Characteristic
Symbol
VDD
Test Conditions
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
3.0
18
3.0
18
3.0
18
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)

Range
VDD

Package
IDD
5.0
10
15
Control Inputs: Vin =

VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
Vswitch 500 mV**
ID(AV)
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus
Quiescent,
Per Package

Typical
CONTROL INPUTS INHIBIT, A, B, C, D (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN X, Y (Voltages Referenced to VSS)

Recommended Peakto
Peak Voltage Into or
Out of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Dynamic Voltage
Across the Switch*
(Figure 1)
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
5.0
10
15
Vswitch
500 mV**,
Vin = VIL or VIH
(Control), and Vin
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1300
550
320
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Inhibit = VDD
10
pF
CO/I
Inhibit = VDD
(MC14067B)
(MC14097B)
100
60
0.47
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 2)
(Channel Off)
CI/O
Pins Not Adjacent

Pins Adjacent
pF
pF
Data labeled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential performance.
** For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
MC14067B MC14097B
6152
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)

Characteristic
Symbol
VDD VSS
Vdc
Typ #
Max
tPLH, tPHL

Channel InputtoChannel Output (RL = 200 k)
MC14067B
(Figure 3)
MC14097B
Control InputtoChannel Output

Channel TurnOn Time (RL = 10 k)
MC14067B/097B
tPZH, tPZL
Channel TurnOff Time (RL = 300 k)

MC14067B/097B
tPHZ, tPLZ
(Figure 4)
(Figure 4)
ns
5.0
10
15
35
15
12
90
40
30
5.0
10
15
25
10
7
65
25
18
5.0
10
15
240
115
75
600
290
190
ns
5.0
10
15
250
120
75
625
300
190
ns
5.0
10
15
280
115
85
700
290
215
(Figure 10)
5.0
10
15
250
100
75
625
250
190
10
0.3
MC14097B
ns

(RL = 10 k, f = 1 kHz, Vin = 5 Vpp)
ON Channel Bandwidth
[RL = 1 k, Vin = 1/2 (VDD VSS) pp(sinewave)]
20 Log10 (Vout/Vin) = 3 dB
BW
MC14067B
MC14097B
Off Channel Feedthrough Attenuation

[RL = 1 k, Vin = 1/2 (VDDVSS) pp(sinewave)]
Channel Separation
[RL = 1 k, Vin = 1/2 (VDDVSS) pp (sinewave)]
MHz
(Figure 5)
10
10
15
25
10
40
dB
10
40
dB
10
30
mV
(Figure 5)
fin = 20 MHz
Crosstalk, Control InputstoCommon O/I

(R1 = 1 k, RL = 10 k,
Control tr = tf = 20 ns, Inhibit = VSS)
ns
ns
tPLH, tPHL
Any Pair of Address Inputs to Output

MC14067B
Unit
(Figure 6)
(Figure 7)
MC14067B MC14097B
6153

VDD
A
VSS
ON SWITCH
CONTROL
SECTION
OF IC
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
LOAD
VSS
VDD
SOURCE
VSS
VDD
MC14067B
PIN ASSIGNMENT
MC14097B
PIN ASSIGNMENT
24
VDD
24
VDD
X7
23
X8
X7
23
Y0
X6
22
X9
X6
22
Y1
X5
21
X10
X5
21
Y2
X4
20
X11
X4
20
Y3
X3
19
X12
19
Y4
X2
18
X13
X2
18
Y5
X1
17
X14
X1
17
X0
16
X15
X0
16
Y6
10
15
INHIBIT
10
15
Y7
11
14
11
14
VSS
12
13
INHIBIT
VSS
12
MC14067B MC14097B
6154
13
X3
VC
PULSE
GENERATOR
VDD
A
B
C
D
Vout
INH
VDD VSS VSS VDD

20 ns
Vin
90%
50%
tPLH
20 ns
90%
50%
10%
VC
20 ns
Vin
VX
Vin
CL = 50 pF
RL
VDD
10%
90%
Vout
VSS
tPHL
50%
tPZH, tPZL
50%
Vout
Vout

and Waveforms Vin to Vout
A
B
C
D
tPHZ, tPLZ
50%
10%
VDD
Vin = VSS
VX = VDD
RL
A
B
C
D
ON
INH
OFF
Vout
RL
Vin = VDD
VX = VSS
Figure 4. TurnOn and Delay TurnOff

Test Circuit and Waveforms
A, B, and C inputs used to turn ON or OFF

INH
CL = 50 pF
RL
Vout
INH
20 ns
A
B
C
D
RL
CL = 50 pF
Vout
CL = 50 pF
Vin
Vin

VC

(Adjacent Channels Used for Setup)
A
B
C
D
Vout
RL
INH
CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
MC14067B MC14097B
6155
VA
VB
A
B
C
D
INH
CL
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
VDD
1 k
RANGE
XY
PLOTTER
VDD
Vout
VA
50%
VB
50%
tPHL
VSS
tPLH
50%
Vout
Figure 9. Propagation Delay, Any Pair of

Address Inputs to Output
350
300
300
250
200
150
100
25C
55C
50
0
10
TA = 125C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
350
250
200
150
25C
55C
50
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
700
350
600
300
500
400
300
TA = 125C
200
25C
100
0
10
TA = 125C
100
0
10
10
55C
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
10
TA = 25C
250
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
0
10
8.0 6.0 4.0 2.0
0.2
4.0
6.0
8.0
Figure 13. Comparison at 25C, VDD = VSS
MC14067B MC14097B
6156
10
10
Figure A illustrates use of the Analog Multiplexer/Demultiplexer. The 0to5 volt Digital Control signal is used to
directly control a 5 Vpp analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example. VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.
and V SS. The analog voltage must swing neither higher than
V DD nor lower than V SS. The example shows a 5 V pp signal
which allows no margin at either peak. If voltage transients

above V DD and/or below V SS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between VDD
and VSS is 18.0 volts. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VSS.
+5 V
VDD
VSS
+ 5.0 V
5 Vpp
ANALOG SIGNAL
SWITCH
I/O
COMMON
O/I
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
5 Vpp
ANALOG SIGNAL
GND
MC14067B
MC14097B
0TO5 V DIGITAL
+ 2.5 V
CONTROL SIGNALS
VDD
VDD
DX
DX
SWITCH
I/O
COMMON
O/I
DX
VSS
DX
VSS
MC14067B MC14097B
6157
MOTOROLA
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high
noise immunity is desired. Each of the six inverters is a single stage to
minimize propagation delays.
L SUFFIX
CERAMIC
CASE 632

Capable of Driving Two LowPower TTL Loads or One LowPower
Triple Diode Protection on All Inputs (see Page 52)
PinforPin Replacement for CD4069UB
Meets JEDEC UB Specifications
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
PIN ASSIGNMENT
LOGIC DIAGRAM
1
11
10
13
12
CIRCUIT SCHEMATIC
VDD
IN 1
14
VDD
OUT 1
13
IN 6
IN 2
12
OUT 6
OUT 2
11
IN 5
IN 3
10
OUT 5
OUT 3
IN 4
VSS
OUT 4
VDD = PIN 14
VSS = PIN 7
INPUT*
OUTPUT
VSS
* Double diode protection on all
inputs not shown.
20 ns
PULSE
GENERATOR
Plastic
Ceramic
SOIC
VDD
14
OUTPUT
INPUT
INPUT
7
VSS
CL
20 ns
VDD
90%
50%
10%
tPHL
tPLH
90%
50%
10%
OUTPUT
tTHL
VSS
VOH
VOL
tTLH
MC14069UB
6158

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
1 Level
VIH
(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Gate) (CL = 50 pF)
Output Rise and Fall Times**

(CL = 50 pF)
tTLH,
tTHL

(CL = 50 pF)
tPLH,
tPHL
mAdc
IT = (0.3 A/kHz) f + IDD/6

IT = (0.6 A/kHz) f + IDD/6
IT = (0.9 A/kHz) f + IDD/6
Adc
ns
5.0
10
15
100
50
40
200
100
80
ns
5.0
10
15
65
40
30
125
75
55
be left open.
MC14069UB
6159
MOTOROLA
MC14070B
MC14077B
CMOS SSI
Quad Exclusive OR and NOR Gates

The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS Pchannel and Nchannel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired.
L SUFFIX
CERAMIC
CASE 632

MC14070B Replacement for CD4030B and CD4070B Types
MC14077B Replacement for CD4077B Type
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
MC14070B
QUAD Exclusive OR
Gate
20 ns
Vin
IDD
Vin
3
2
5
6
8
6
8
10
VSS
10
9
12
1/f
50% DUTY CYCLE
1
3
2
5
VDD
90%
50%
10%
MC14077B
QUAD Exclusive NOR
Gate
20 ns
VDD
Plastic
Ceramic
SOIC
9
12
11
11
13
CL
13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
* Inverted output on MC14077B only.
PULSE
GENERATOR
INPUT
*
#
VSS
20 ns
20 ns
VDD
CL
90%
50%
10%
tPHL
OUTPUT
tPLH
90%
50%
10%
tTHL
* Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
MC14070B MC14077B
6160
PIN ASSIGNMENT
VDD
IN 1A
14
VDD
VSS
IN 2A
13
IN 2D
VOH
OUTA
12
IN 1D
OUTB
11
OUTD
VOL
tTLH
IN 1B
10
OUTC
IN 2B
IN 2C
VSS
IN 1C

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink

Per Package)
buffers switching)
Output Rise and Fall Times**

(CL = 50 pF)
tTLH,
tTHL

(CL = 50 pF)
tPLH,
tPHL
mAdc

Adc
ns
5.0
10
15
100
50
40
200
100
80
ns
5.0
10
15
175
75
55
350
150
110
where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
be left open.
MC14070B MC14077B
6161
MOTOROLA
MC14076B
4-Bit D-Type Register
with Three-State Outputs
L SUFFIX
CERAMIC
CASE 620
The MC14076B 4Bit Register consists of four Dtype flipflops operating

synchronously from a common clock. OR gated outputdisable inputs force
the outputs into a highimpedance state for use in bus organized systems.
OR gated datadisable inputs cause the Q outputs to be fed back to the D
inputs of the flipflops. Thus they are inhibited from changing state while the
clocking process remains undisturbed. An asynchronous master root is
provided to clear all four flipflops simultaneously independent of the clock
or disable inputs.
ThreeState Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
Four Bus Buffer Registers
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
DC Supply Voltage
Vin, Vout
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
BLOCK DIAGRAM
15
14
13
12
11
10
9
7
2
1
RESET
Q0
Q1
DATA
DISABLE
Q2
CLOCK
B OUTPUT
A DISABLE
Q3
D0
D1
D2
D3
B
A
VDD = PIN 16
VSS = PIN 8
FUNCTION TABLE
Inputs
Data Disable
Reset
Clock
Data
D
Output
Q
Qn
Qn
Qn
When either output disable A or B (or both) is (are) high the

output is disabled to the highimpedance state; however
sequential operation of the flipflops is not affected.
X = Dont Care.
MC14076B
6162

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ThreeState Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
MC14076B
6163

Characteristic
Symbol

tTLH, tTHL

Clock to Q
tPLH, tPHL
Reset to Q
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
300
125
90
600
250
180
5.0
10
15
300
125
90
600
250
180
3State Propagation Delay, Output 1 or 0

to High Impedance
tPHZ, tPLZ
5.0
10
15
150
60
45
300
120
90
ns
3State Propagation Delay, High Impedance

to 1 or 0 Level
tPZH, tPZL
5.0
10
15
200
80
60
400
160
120
ns
Clock Pulse Width
tWH
5.0
10
15
260
110
80
130
55
40
ns
Reset Pulse Width
tWH
5.0
10
15
370
150
110
185
75
55
ns
Data Setup Time
tsu
5.0
10
15
30
10
4
15
5
2
ns
Data Hold Time
th
5.0
10
15
130
60
50
65
30
25
ns
Data Disable Setup Time
tsu
5.0
10
15
220
80
50
110
40
25
ns
tTLH, tTHL
5.0
10
15
15
5
4
fcl
5.0
10
15
3.6
9.0
12
1.8
4.5
6.0
MHz
be left open.
MC14076B
6164
20 ns
INPUT RISE AND FALL 20 ns

90%
50%
10%
th
tsu
INPUT
INFORMATION
tsu
OUTPUT
DISABLE
A OR B
th
90%
10%
tWL
fcl
90%
OUTPUT
ANY Q
OUTPUT
10%
tPHZ
90%
ANY Q
OUTPUT
tTHL
OUTPUTS
DISCONNECTED
VOH
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
tPZH
10%
OUTPUTS
CONNECTED
VOL
tPZL
90%
ANY Q
OUTPUT
RL = 1 k
50%
10%
tTLH
VSS
tPHL
tPLH
Q
VDD
VDD
10%
tPLZ
20 ns
50%
tWH
50%
VDD
VSS
20 ns
90%
50%
CL
Figure 2. ThreeState Propagation Delay

Waveshape and Circuit
OUTPUT
DISABLE
D
C
DATA DISABLE A
DATA DISABLE B
9
10
D1 13
D
C
CLOCK
PIN ASSIGNMENT
1
2
D0 14
VOH
2.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
VDD FOR tPLZ AND tPZL

VSS FOR tPHZ AND tPZH
MC14076B
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A
OUTPUT DISABLE B
VSS
Q
R Q
3 Q0
Q
R Q
{B
16
VDD
15
Q0
14
D0
Q1
13
D1
Q2
12
D2
Q3
11
D3
10
VSS
} DATA
DISABLE
4 Q1
D2 12
D3 11
R Q
R Q
5 Q2
6 Q3
RESET 15
MC14076B
6165
MOTOROLA
MC14093B
Quad 2-Input NAND"
Schmitt Trigger
L SUFFIX
CERAMIC
CASE 632
The MC14093B Schmitt trigger is constructed with MOS Pchannel and

Nchannel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the
MC14011B quad 2input NAND gate for enhanced noise immunity or to
square up slowly changing waveforms.
PinforPin Compatible with CD4093
Can be Used to Replace MC14011B
Independent SchmittTrigger at each Input
D SUFFIX
SOIC
CASE 751A

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
P SUFFIX
PLASTIC
CASE 646
EQUIVALENT CIRCUIT SCHEMATIC

MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
1
2
5
6
8
9
10
12
13
11
VDD = PIN 14
VSS = PIN 7

MC14093B
6166

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Hysteresis Voltage
VH
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
VT
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vin = 0 or VDD

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
NegativeGoing
mAdc

Adc
Vdc
Vdc
Vdc
MC14093B
6167

Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
#Data labeled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
VDD
20 ns
14
PULSE
GENERATOR
INPUT
OUTPUT
20 ns
VDD
90%
50%
10%
tPHL
INPUT
7
VSS
CL
OUTPUT
tPLH
90%
50%
10%
tTHL
VSS
VOH
VOL
tTLH
VH
VH
VDD
Vin
VDD
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
(a) Schmitt Triggers will square up

(a) inputs with slow rise and fall times.
VSS
(b) A Schmitt trigger offers maximum

(b) noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
MC14093B
6168
14
14
IOH
Vout
All unused inputs

connected to ground.
7
All unused inputs
VGS
10
c
b
VGS = 5.0 Vdc
2.0
a
b
b
4.0
TA = 55C
TA = + 25C
TA = + 125C
c
6.0
10 Vdc
8.0
10
10
15 Vdc
a
8.0
6.0
4.0
b c
15 Vdc
a
8.0
VGS = 10 Vdc
b
c
6.0
a
b
c
4.0
TA = 55C
TA = + 25C
TA = + 125C
2.0
5.0 Vdc
c
a
2.0

2.0
4.0
6.0
8.0
10

VDD
PIN ASSIGNMENT

0
Vout
IOL , DRAIN CURRENT (mAdc)
IOH, DRAIN CURRENT (mAdc)
IOL
VGS
VT
VT+
VH
IN 1A
14
VDD
IN 2A
13
IN 2D
OUTA
12
IN 1D
OUTB
11
OUTD
IN 1B
10
OUTC
IN 2B
IN 2C
VSS
IN 1C
VDD
MC14093B
6169
MOTOROLA
MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
L SUFFIX
CERAMIC
CASE 620
The MC14094B combines an 8stage shift register with a data latch for
each stage and a threestate output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
highspeed cascaded systems. The QS output data is shifted on the
following negative clock transition for use in lowspeed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by threestate buffers
which are placed in the highimpedance state by a logic Low on Output
Enable.
ThreeState Outputs
Input Diode Protection
Data Latch
Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
Useful for SerialtoParallel Data Conversion
PinforPin Compatible with CD4094B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
VDD
DC Supply Voltage
Plastic
Ceramic
SOIC

Parameter
D SUFFIX
SOIC
CASE 751B
Symbol
P SUFFIX
PLASTIC
CASE 648
Value
Unit
0.5 to + 18.0
PIN ASSIGNMENT
STROBE
16
DATA
15
CLOCK
14
VDD
OUTPUT
ENABLE
Q5
13
Q6
12
Q7
Vin, Vout
0.5 to VDD + 0.5
Q1
Iin, Iout

per Pin
10
mA
Q2
Q3
11
Q8
PD
500
mW
Q4
10
QS
Tstg
Storage Temperature
65 to + 150
_C
VSS
QS
260
_C
TL
Clock
Parallel Outputs
Serial Outputs
Output
Enable
Strobe
Data
Q1
QN
QS*
QS
Q7
No Chg.
No Chg.
Q7
No Chg.
No Chg.
Q7
No Chg.
QN1
Q7
No Chg.
QN1
Q7
No Chg.
No Chg.
No Chg.
No Chg.
Q7

to the range VSS
(Vin or Vout)
VDD.
Z = High Impedance
X = Dont Care
* At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.
MC14094B
6170

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
3State Output Leakage Current
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

IT = (14 A/kHz) f + IDD
0.1
0.0001
0.1
Adc
3.0
MC14094B
6171

Characteristic
Symbol

Clock to Serial out QS
tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
tTLH,
tTHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
tPLH,
tPHL
ns
5.0
10
15
350
125
95
600
250
190
Clock to Serial out QS

5.0
10
15
230
110
75
460
220
150
Clock to Parallel out

5.0
10
15
420
195
135
840
390
270
Strobe to Parallel out

tPLH, tPHL = (0.36 ns/pF) C L + 127 ns
5.0
10
15
290
145
100
580
290
200
tPHZ,
tPZL
5.0
10
15
140
75
55
280
150
110
tPLZ,
tPZH
5.0
10
15
225
95
70
450
190
140
Setup Time
Data in to Clock
tsu
5.0
10
15
125
55
35
60
30
20
ns
Hold Time
Clock to Data
th
5.0
10
15
0
20
20
40
10
0
ns
Clock Pulse Width, High
tWH
5.0
10
15
200
100
83
100
50
40
ns
tr(cl)
tf(cl)
5
10
15
15
5.0
4.0
fcl
5.0
10
15
2.5
5.0
6.0
1.25
2.5
3.0
MHz
tWL
5.0
10
15
200
80
70
100
40
35
ns
Output Enable to Output

tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns
tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns
tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns
Strobe Pulse Width
3STATE TEST CIRCUIT

FOR tPHZ AND tPZH
VSS
O.E.
FOR tPLZ AND tPZL

VDD
1k
DATA
ST
OUTPUT
50 pF
CLOCK
MC14094B
6172
BLOCK DIAGRAM
REGISTER STAGE 1
CLOCK
2
LATCH 1
CLOCK
3STATE BUFFER 1
STROBE
VDD
*
SERIAL
DATA IN
15
CLOCK
CLOCK
STROBE STROBE
CLOCK
CLOCK
STROBE
Q1
*
2
OUTPUT
ENABLE
3
4
5
6
7
REGISTER STAGE 2
LATCH 2
3STATE BUFFER 2
Q2
REGISTER STAGE 3
LATCH 3
3STATE BUFFER 3
Q3
REGISTER STAGE 4
LATCH 4
3STATE BUFFER 4
Q4
REGISTER STAGE 5
LATCH 5
3STATE BUFFER 5
14
Q5
REGISTER STAGE 6
LATCH 6
3STATE BUFFER 6
13
Q6
REGISTER STAGE 7
LATCH 7
3STATE BUFFER 7
12
Q7
LATCH 8
3STATE BUFFER 8
11
Q8
10
QS
QS
REGISTER STAGE 8
CLOCK
STROBE STROBE
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
1
*Input Protection Diodes
STROBE
*
STROBE
CLOCK
STROBE
DYNAMIC TIMING DIAGRAM

tWH
tf
tr
CLOCK
90%
50%
50%
10%
th
tsu
2
DATA IN
tWL
STROBE
15
OUTPUT
ENABLE
50%
tPLH
Q1
Q7
tTLH
90%
tPHL
90%
tPLH
tPHZ
tTHL
QS
tPZL
90%
10%
10%
tPHL
tPLH
50%
50%
tPLH
10 QS
tPLZ
tPZH
90%
10%
10%
50%
50%
tPHL
50%
MC14094B
6173
MOTOROLA
MC14099B
MC14599B
8-Bit Addressable Latches

The MC14099B and MC14599B are 8bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
Serial Data Input

Parallel Output
Master Reset
Capable of Driving Two Lowpower TTL Loads or One LowPower
Schottky TTL Load over the Rated Temperature Range
MC14099B pin for pin compatible with CD4099B
DW SUFFIX
SOIC
CASE 751G

Symbol
Parameter
VDD
Vin, Vout
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA
500
mW
65 to + 150
_C
DC Supply Voltage
Iin, Iout
PD
Tstg
Storage Temperature
MC14099BCP
MC14099BCL
MC14099BDW
L SUFFIX
CERAMIC
CASE 726
TL
260
_C
MC14099B
5
6
DECODER
7
A0
A1
A2
RESET
9
10
11
12
8
13
LATCHES 14
15
1
4
3
WRITE DISABLE
DATA
P SUFFIX
PLASTIC
CASE 707
MC14599B
2
VDD = 16
VSS = 8
8
10
4
3
CHIP ENABLE
WRITE/READ
WRITE DISABLE
Q0
DATA
Q1
Q2
A0
Q3
A1
Q4
A2
Q5
Q6
RESET
Q7
5
6
7
8
DECODER
2
11
12
13
8
14
LATCHES
15
16
17
1
VDD = 18
VSS = 9
PIN ASSIGNMENT
PIN ASSIGNMENT
Q7
18
VDD
RESET
17
Q6
16
Q5
15
Q4
14
Q3
Q7
16
VDD
RESET
15
Q6
DATA
WRITE
DISABLE
A0
14
Q5
13
Q4
DATA
WRITE
DISABLE
A0
12
Q3
A1
13
Q2
A1
11
Q2
A2
12
Q1
A2
10
Q1
CE
11
VSS
Q0
VSS
10
Q0
WRITE/
READ
MC14099B MC14599B
6174
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Plastic
Ceramic
SOIC
MC14599BCP
MC14599BCL
Plastic
Ceramic

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Input Capacitance
MC14599B Data (pin 3)
(Vin = 0)
Cin
15
22.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14099B MC14599B
6175
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
200
75
50
400
150
100
Write Disable to Output Q
5.0
10
15
200
80
60
400
160
120
ns
Reset to Output Q
5.0
10
15
175
80
65
350
160
130
ns
CE to Output Q (MC14599B only)
5.0
10
15
225
100
75
450
200
150
ns
5.0
10
15
200
80
65
400
160
130
5.0
10
15
200
90
75
400
180
150
5.0
10
15
150
75
50
75
40
25
5.0
10
15
320
160
120
160
80
60
5.0
10
15
100
50
35
50
25
20
5.0
10
15
150
75
50
75
40
25
Characteristic
Symbol

tTLH,
tTHL

Data to Output Q
tPHL,
tPLH
Propagation Delay Time, MC14599B only

Chip Enable, Write/Read to Data
tPHL,
tPLH
Address to Data
Pulse Widths
Reset
tw(H)
tw(L)
Write Disable
Unit
ns
ns
ns
ns
ns
ns
Set Up Time
Data to Write Disable
tsu
ns
Hold Time
Write Disable to Data
th
Set Up Time
Address to Write Disable
tsu
5.0
10
15
100
80
40
45
30
10
ns
Removal Time
Write Disable to Address
trem
5.0
10
15
0
0
0
80
40
40
ns
ns
MC14099B MC14599B
6176
MC14099B
FUNCTION DIAGRAM
RESET 2
9 Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES
ZERO
SELECT
10 Q1
A0 5
11 Q2
12 Q3
ADDRESS
DECODER
A1 6
13 Q4
OTHER LATCHES
14 Q5
15 Q6
A2 7
(M.S.B.)
1 Q7
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
Data
Qn*
Data
Reset
Qn*
Qn*
Reset
Reset
CAUTION: To avoid unintentional data changes in the latches, Write

Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
* Qn is previous state of latch.

Reset to zero state.
SWITCHING WAVEFORMS
VDD
DATA OR
WRITE DISABLE
50%
VSS
VDD
tPLH
OUTPUT Q
tPHL
ADDRESS
90%
50%
10%
50%
VSS
tsu
tw(L)
trem
VDD
tTLH
tTHL
WRITE
DISABLE
50%
VSS
tw(H)
tsu
VDD
RESET
50%
VDD
DATA
VSS
th
50%
VSS
tPHL
OUTPUT Q
MC14099B MC14599B
6177
MC14599B
FUNCTION DIAGRAM
RESET 2
11 Q0
DATA 3
VDD
TO
OTHER
LATCHES
VSS
EACH LATCH
ZERO
SELECT
CHIP
8
ENABLE
WRITE/READ 10
WRITE
4
DISABLE
12 Q1
A0 5
13 Q2
14 Q3
ADDRESS
DECODER
A1 6
OTHER LATCHES
15 Q4
16 Q5
17 Q6
A2 7
(M.S.B.)
1 Q7
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
Other
Latches
Data
Pin
Data
Input
Qn
Z/0
X = Dont care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
MC14099B MC14599B
6178
MC14599B
SWITCHING WAVEFORMS
DATA WRITE
50%
Q0
Q7
tPHL
tTLH
90%
10%
tPHL
90%
10%
tTHL
tPLH
tPLH
VDD
RESET
VSS
tw(H)
VDD
CE
VSS
VDD
50%
A2, A1, A0
VSS
VDD
DATA
50%
VSS
tsu
tw(L)
trem
tsu
90%
WRITE DISABLE
10%
50%
10%
20 ns
th
50%
VDD
VSS
20 ns
DATA READ
VDD
W/R
VSS
VDD
50%
tPLH,
tPHL
CE
DATA
VSS
50%
tPLH,
tPHL
VDD
VSS
VDD
A2, A1, A0
VSS
NOTE: 1. Invalid Data Output
2. Reset in LOW State
MC14099B MC14599B
6179
MOTOROLA
MC14106B
Hex Schmitt Trigger
L SUFFIX
CERAMIC
CASE 632
The MC14106B hex Schmitt Trigger is constructed with MOS Pchannel

MC14069UB hex inverter for enhanced noise immunity or to square up
slowly changing waveforms.
P SUFFIX
PLASTIC
CASE 646
Increased Hysteresis Voltage Over the MC14584B

PinforPin Replacement for CD40106B and MM74C14
Can Be Used to Replace the MC14584B or MC14069UB

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
EQUIVALENT CIRCUIT SCHEMATIC

D SUFFIX
SOIC
CASE 751A
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
1
11
10
13
12
VDD = PIN 14
VSS = PIN 7

MC14106B
6180

Characteristic
Output Voltage
Vin = VDD
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Hysteresis Voltage
VH
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
Vdc
VT
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0
NegativeGoing

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
where IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
VH = VT+ VT (But maximum variation of VH is specified as less that VT+ max VT min).
MC14106B
6181

Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
PULSE
GENERATOR
20 ns
VDD
14
OUTPUT
INPUT
INPUT
7
VDD
90%
50%
10%
tPHL
CL
VSS
20 ns
tPLH
90%
50%
10%
OUTPUT
tf
tr
VSS
VOH
VOL
VDD
0
0
VT
VT+
VH
VDD
APPLICATIONS
Vout
Vin
VH
VDD
VH
VDD
Vin
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
VSS
(a) Schmitt Triggers will square up

inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum

noise immunity in gate applications.
Figure 3.
MC14106B
6182
VDD
VDD
R
C
tw
Rs
tw
Rs
Vout
Vout
R
tw = RC IN
VDD
VT+
Useful as Pushbutton/Keyboard Debounce Circuit.
Figure 4. Monostable Multivibrator
1
f
t1
Vin
Vout
C
t2
C
* t1
[ RC ln VTT)
* t2
VDD
Vin VT+
VSS
1
f
[ RC ln
*t1 + t2
VDD VT
RC ln
VDD VT )
VDD VT
VDD VT )
VSS
VT )
VDD
Vout VT+
VSS
VT
& tPHL + tPLH
VDD
VT+
Useful in discriminating against short pulse durations.
Figure 5. Astable Multivibrator
Figure 6. Integrator
C
Vin
Vin
R
+ EDGE
EDGE
EDGE
+ EDGE
Vin
VDD
tw
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.
Figure 7. Differentiator
Figure 8. Positive Edge Time Delay Circuit
MC14106B
6183
MOTOROLA
CMOS MSI
Synchronous Presettable 4Bit Counters
The MC14160B MC14163B are synchronous programmable counters
constructed with complementary MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. These counters
are functionally equivalent to the 74160 74163 TTL counters.
Two are synchronous programmable BCD counters with asynchronous
and synchronous clear inputs respectively (MC14160B, MC14162B). The
other two are synchronous programmable 4bit binary counters with the
asynchronous and synchronous clear respectively (MC14161B, MC14163B).
MC14160B
MC14161B
MC14162B
MC14163B
L SUFFIX
CERAMIC
CASE 620
Internal LookAhead for Fast Counting

Carry Output for NBit Cascading
Synchronously Programmable
Synchronous Counting
Load Control Line
Synchronous or Asynchronous Clear
Positive Edge Clocked
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

MC14160B MC14161B MC14162B MC14163B

6184
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
7
PE
10
TE
CLEAR
LOAD
CLOCK
P1
P2
P3
P4
Q1
14
Q2
13
Q3
12
Q4
11
CARRY
OUT
15
VDD = PIN 16
VSS = PIN 8

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
CLEAR
16
VDD
CLOCK
15
CARRY OUT
P1
14
Q1
P2
13
Q2
P3
12
Q3
P4
11
Q4
PE
10
TE
VSS
LOAD
MC14160B MC14161B MC14162B MC14163B

6185

Characteristic
Output Rise Time
Output Fall Time

Clock to Q
Clock to Carry Out
TE to Carry Out
Clear to Q (MC14160B, MC14161B only)
Symbol
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
tTLH
ns
tTHL
ns
tPLH, tPHL
ns
5.0
10
15
350
150
100
700
300
200
5.0
10
15
440
185
125
880
370
250
5.0
10
15
300
130
90
600
260
180
5.0
10
15
350
150
100
700
300
200
5.0
10
15
320
130
90
160
65
45
5.0
10
15
600
260
180
300
130
90
5.0
10
15
420
170
120
210
85
60
5.0
10
15
310
110
70
155
55
35
5.0
10
15
10
5.0
0
60
25
15
Clock to Load
5.0
10
15
40
10
5.0
195
80
50
Clock to PE
5.0
10
15
40
10
0
175
70
40
Clock to TE
5.0
10
15
150
30
20
280
130
80
Clock to Clear (MC14162B, MC14163B only)
5.0
10
15
80
30
10
40
15
70
5.0
10
15
90
65
55
30
20
20
Setup Times
Data to Clock
Unit
tsu
ns
Load to Clock
Enable to Clock (PE or TE)
Clear to Clock (MC14162B, MC14163B only)
Hold Times
Clock to Data
Clear Removal Time (MC14160B, MC14161B only)
MC14160B MC14161B MC14162B MC14163B

6186
th
trem
ns
ns
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (Continued)

Characteristic
VDD
Vdc
Min
Typ #
Max
Unit
Clear Pulse Width, Low (MC14160B, MC14161B only)
tWL
5.0
10
15
200
90
60
100
45
30
ns
Clock Pulse Width, High
tWH
5.0
10
15
250
100
70
125
50
35
ns
tr, tf
5.0
10
15
15
5.0
4.0
ms
fcl
5.0
10
15
2.0
5.0
8.0
1.0
2.5
4.0
mHz
Symbol
MC14160B MC14161B MC14162B MC14163B

6187
SWITCHING WAVEFORMS
FUNCTIONAL DESCRIPTION
These counters are fully programmable; that is the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the
next clock pulse regardless of the levels of the enable inputs.
The clear function for the MC14160B, MC14161B is asynch
ronous and a low level at the clear input sets all four of the
flipflop outputs low regardless of the levels of the clock,
load or enable inputs. The clear function for the MC14162B
and MC14163B is synchronous and a low level at the clear
inputs sets all four of the flipflop outputs low after the next
clock pulse, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily; decoding the maximum count desired can be ac-
MC14160B MC14161B MC14162B MC14163B

6188
complished with one external NAND gate. The gate output is

connected to the clear input to synchronously clear the
counter to 0000(LLLL).
The carry lookahead circuitry provides for cascading
counters for nbit synchronous applications without additional gating. Instrumental in accomplishing this function are
two countenable inputs and a carry output. Both count
enable inputs (PE, TE) must be high to count, and enable input TE fed forward to enable the carry output. The carry
output thus enabled will produce a positive output pulse with
a duration approximately equal to the positive portion of the
Q1 output. This positive overflow carry pulse can be used to
enable successive cascaded stages.
MC14160B, MC14162B LOGIC DIAGRAM

(Clear is synchronous for MC14162B)
MC14160B MC14161B MC14162B MC14163B

6189
MC14160B, MC14162B TIMING DIAGRAM

Sequence illustrated in waveforms:
1.
2.
3.
4.
Clear outputs to zero.

Preset to BCD seven.
Count to eight, nine, zero, one, two, and three.
Inhibit.
MC14160B MC14161B MC14162B MC14163B

6190
MC14161B, MC14163B LOGIC DIAGRAM

(Clear is synchronous for MC14163B)
MC14160B MC14161B MC14162B MC14163B

6191
MC14161B, MC14163B TIMING DIAGRAM

Sequence illustrated in waveforms:
1.
2.
3.
4.
Clear outputs to zero.

Preset to binary twelve.
Count to thirteen, fourteen, fifteen, zero, one, and two.
Inhibit.
MC14160B MC14161B MC14162B MC14163B

6192
MOTOROLA
MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flipflop is constructed with MOS Pchannel
Data on the D inputs which meets the setup time requirements is transferred
to the Q outputs on the positive edge of the clock pulse. All six flipflops
share common clock and reset inputs. The reset is active low, and
independent of the clock.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
Static Operation
All Inputs and Outputs Buffered
Functional Equivalent to TTL 74174

Symbol
VDD
Parameter
Unit
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
CLOCK
260
_C
RESET
D0
TL
DC Supply Voltage
Value
D SUFFIX
SOIC
CASE 751B
TRUTH TABLE
(Positive Logic)
Inputs
Clock
Output
Data
Reset
0
1
X
X
1
1
1
0
0
1
Q
0
X
X = Dont Care
No
Change
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
Q0
Q1
D1
Q2
D2
Q3
10
11
D3
13
D4
Q4
12
14
D5
Q5
15
VDD = PIN 16
VSS = PIN 8

MC14174B
6193

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14174B
6194
All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
210
85
65
400
160
120
5.0
10
15
250
100
75
500
200
150
tWH
5.0
10
15
150
90
70
75
45
35
ns
tWL
5.0
10
15
200
100
80
100
50
40
ns
fcl
5.0
10
15
7.0
12
15.5
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
40
20
15
20
10
0
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
ns
trem
5.0
10
15
250
100
80
125
50
40
ns
Characteristic
Symbol

Propagation Delay Time Clock to Q
Propagation Delay Time Reset to Q
Clock Pulse Width
tTLH, tTHL
ns
tPLH, tPHL
ns
tPHL
Reset Pulse Width
Reset Removal Time
Unit
ns
PIN ASSIGNMENT
16
Q0
15
Q5
D0
14
D5
D1
13
D4
Q1
12
Q4
VDD
D2
11
D3
Q2
10
Q3
VSS
MC14174B
6195
TIMING DIAGRAM
MC14174B
6196
MOTOROLA
MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flipflop is constructed with MOS Pchannel
Each of the four flipflops is positiveedge triggered by a common clock
input (C). An activelow reset input (R) asynchronously resets all flipflops.
Each flipflop has independent Data (D) inputs and complementary outputs
(Q and Q). These devices may be used as shift register elements or as type
T flipflops for counter and toggle applications.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Output Compatible with Two LowPower TTL Loads or One LowPower
Schottky TTL Load
Functional Equivalent to TTL 74175

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
CLOCK
Tstg
Storage Temperature
65 to + 150
_C
RESET
260
_C
D0
D1
12
D2
13
D3
TL
TRUTH TABLE
Inputs
Clock
BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
10
Q2
11
Q3
15
Q3
14
Outputs
Data
Reset
0
1
X
X
1
1
1
0
0
1
Q
0
1
0
Q
1
X
X = Dont Care
Plastic
Ceramic
SOIC
VDD = PIN 16
VSS = PIN 8
No
Change

MC14175B
6197

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
MC14175B
6198
16
VDD
Q0
15
Q3
Q0
14
Q3
D0
13
D3
D1
12
D2
Q1
11
Q2
Q1
10
Q2
VSS
All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
90
70
400
160
120
5.0
10
15
325
130
100
500
200
150
tWH
5.0
10
15
250
100
75
110
45
35
ns
tWL
5.0
10
15
200
80
60
100
40
30
ns
fcl
5.0
10
15
4.5
11
14
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
120
50
40
60
25
20
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
ns
trem
5.0
10
15
250
100
80
125
50
40
ns
Characteristic

Propagation Delay Time Clock to Q, Q
Propagation Delay Time Reset to Q, Q
tPHL = (0.36 ns/pF) CL + 112 ns
Clock Pulse Width
Reset Pulse Width
Reset Removal Time
Symbol
tTLH, tTHL
Unit
ns
tPLH, tPHL
ns
tPHL, tPLH
ns
MC14175B
6199
TIMING DIAGRAM
MC14175B
6200
MOTOROLA
MC14194B
4-Bit Bidirectional Universal
Shift Register
L SUFFIX
CERAMIC
CASE 620
The MC14194B is a 4bit static shift register capable of operating in the

parallel load, serial shift left, serial shift right, or hold mode. The
asynchronous Reset input, when at a low level, overrides all other inputs,
resets all stages, and forces all outputs low. When Reset is at a logic 1 level,
the two mode control inputs, S0 and S1, control the operating mode as
shown in the truth table. Both serial and parallel operation are triggered on
the positivegoing transition of the Clock input. The Parallel Data, Data Shift,
and mode control inputs must be stable for the specified setup and hold
times before and after the positivegoing Clock transition.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Synchronous Right/Left Serial Operation

Synchronous Parallel Load
Asynchronous Hold (Do Nothing) Mode
Functional Pin for Pin Equivalent of LS194
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
3
4
DP0
DP1
6
DP2
DP3
S1 10
S0
DSR
7
DSL
VDD = PIN 16
VSS = PIN 8
DQ
D Q
D Q
D Q
CR
CR
CR
CR
CLOCK 11
RESET 1
Q0
15
Q1
14
Q2
13
Q3
12
MC14194B
6201

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

MC14194B
6202
PIN ASSIGNMENT
R
16
DSR
15
Q0
DP0
14
Q1
DP1
13
Q2
DP2
12
Q3
DP3
11
DSL
10
S1
VSS
S0
VDD
TRUTH TABLE
p
g
Operating
Mode
Hold
Shift Left
Shift Right
Parallel
Inputs
(Reset = 1)
Outputs
(@ tn+1)
S1
S0
DSR
DSL
DP03
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q1
Q2
Q3
Q1
Q2
Q3
Q0
Q1
Q2
Q0
Q1
Q2
X = Dont Care
tn+1 = State after the next positivegoing transition of the clock.

Characteristic
Symbol

tTLH, tTHL

Clock to Q
tPLH,tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
275
110
85
550
220
170
5.0
10
15
350
140
110
700
280
220
Reset to Q
tPHL = (0.36 ns/pF) CL + 122 ns
Clock Pulse Width
tPHL
tWH
5.0
10
15
280
110
85
140
55
40
ns
Reset Pulse Width
tWH
5.0
10
15
180
70
50
90
35
26
ns
fcl
5.0
10
15
3.6
9.0
12
1.8
4.5
6.0
MHz
tTLH, tTHL
5.0
10
15
15
5
4
5.0
10
15
10
20
40
8.0
0
9.0
5.0
10
15
200
75
55
100
36
27
5.0
10
15
180
50
35
90
25
10
5.0
10
15
0
0
0
40
27
20
ns
5.0
10
15
300
110
80
150
55
40
ns

(Shift Right or Left Mode)
Setup Time
Data to Clock
tsu
M d C
Cl k
Mode
Controll (S) to Clock
Hold Time
Data to Clock
ns
th
M d C
Mode
Controll (S) to Clock
Cl k
Reset Removal Time
ns
trem
ns
ns
MC14194B
6203
Parallel Load
Serial Load
VDD
16
VDD
16
3
4
5
6
11
2
7
9
10
PULSE
GENERATOR
Q0
DP0
DP1
DP2
DP3
CLOCK
DSR
DSL
S0
S1
R
15
3
4
5
6
11
2
7
9
10
CL
Q1
14
CL
Q2
PULSE
GENERATOR
13
CL
Q3
12
CL
VSS
Q0
DP0
DP1
DP2
DP3
CLOCK
DSR
DSL
S0
S1
R
15
CL
Q1
14
CL
Q2
13
CL
Q3
12
CL
VSS
NOTE: Interchange DSR with DSL and S0 with

S1 for testing shift left.
20 ns
DPn
DSR
DSL
20 ns
VDD
90%
50%
10%
tsu
VSS
th
th
tsu
VDD
50%
CLOCK
tWH(cl)
tPLH
90%
50%
10%
tTLH
Qn
VSS
1/fcl
tPHL
VOH
VOL
tTHL
tPHL
trem
50%
RESET
VDD
VSS
tWL
Figure 1. Switching Time Test Circuits and Waveforms
VDD
16
PULSE
GENERATOR
3
4
5
6
11
2
7
9
10
1
DP0
DP1
DP2
DP3
CLOCK
DSR
DSL
S0
S1
R
Q0
15
CL
Q1
14
20 ns
CL
Q2
CL
Q3
90%
50%
VDD
10%
VSS
VDD
1/f
DSR
VSS
VOH
12
CL
CLOCK
13
20 ns
Qn
VOL
VSS
ID
500 F
Figure 2. Dynamic Power Dissipation Test Circuit and Waveforms
MC14194B
6204
MOTOROLA

MC14415
Quad Precision Timer/Driver
L SUFFIX
CERAMIC
CASE 620
MC14415 quad timer/driver is constructed with complementary MOS

enhancement mode devices. The output pulse width of each digital timer is
a function of the input clock frequency. Once the proper input sequence is
detected the output buffer is set (turned on), and after 100 clock pulses are
counted, the output buffer is reset (turned off).
The MC14415 was designed specifically for application in high speed line
printers to provide the critical timing of the hammer drivers, but may be used
in many applications requiring precision pulse widths.
Four Precision Digital Time Delays

Schmitt Trigger Clock Conditioning
NPN Bipolar Output Drivers
Timing Disable Capability Using Inhibit Output
Positive or Negative Edge Strobing on the Inputs
Synchronous Polynomial Counters Used for Delay Counting
DW SUFFIX
SOIC
CASE 751G

Rating
P SUFFIX
PLASTIC
CASE 648
MC14415FP (3.0 V18 V)

MC14415VP (3.0 V6.0 V)
MC14415FL (3.0 V18 V)
MC14415VL (3.0 V6.0 V)
MC14415DW (3.0 V18 V)
Plastic
Plastic
Ceramic
Ceramic
SOIC
Symbol
Value
Unit
DC Supply Voltage MC14415FL, FP,DW

MC14415VL, VP
VDD
0.5 to + 18.0
0.5 to + 6.0
Vin, Vout
0.5 to VDD + 0.5
Iin
10
mA
Iout
20
mA
PD
500
mW
CLOCK
16
VDD
Storage Temperature
Tstg
65 to + 150
_C
SET
15
INH
TL
260
_C
SET A
14
OUT A
SET B
13
OUT B
SET C
12
OUT C
SET D
11
OUT D
ST 1
10
DIS
VSS
ST2
BLOCK DIAGRAM
SET A 3
SET B 4
SET C 5
PIN ASSIGNMENT
14 OUTPUT A
INPUT
LOGIC
DIVIDEBY
100
COUNTERS
SET D 6
OUTPUT
BUFFERS
13 OUTPUT B
12 OUTPUT C
11 OUTPUT D
STROBE 2 9
STROBE 1 7
INPUT DISABLE 10
COMMON
LOGIC
CLOCK
CONDITIONING
CIRCUIT
VDD = PIN 16
VSS = PIN 8
OUTPUT SET 2
CLOCK 1
OUTPUT INHIBIT 15
MC14415
6205
v
v

Characteristic
Output Voltage
(No Load)
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.01
0.01
0
0
0.01
0.01
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
3.0
8.0
4.14
9.09
14.12
Vdc
5.0
10
15
1.5
3.0
1.5
3.0
2.25
4.50
6.75
1.4
2.9
5.0
10
15
1.4
2.9
1.5
3.0
2.25
4.50
6.75
1.5
3.0
5.0
3.0
2.7
2.5
2.2
4.14
3.44
3.30
3.08
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
10
8.0
7.7
7.5
7.1
9.09
8.45
8.30
8.14
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
15
14.12
13.81
13.70
13.61
Vdc
5.0
10
15
0.23
0.60
0.2
0.5
0.78
2.0
7.8
0.16
0.40
Noise Immunity
(Vout
1.5 Vdc)
(Vout
3.0 Vdc)
(Vout
4.5 Vdc)
(Vout
(Vout
(Vout
VNL
1.5 Vdc)
3.0 Vdc)
4.5 Vdc)
VNH
Output Drive Voltage (NPN Driver)

(IOH = 0 mA)
Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
VOH

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOL
Sink
Vdc
mAdc
Iin
15
0.3
0.00001
0.3
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
pF
Quiescent Dissipation
PQ
5.0
10
15
0.25
1.0
0.00005
0.00022
0.00050
0.25
1.0
3.5
14
mW
Power Dissipation**
(Dynamic plus Quiescent)
(CL = 15 pF)
PD
5.0
10
15
PD (56 mW/MHz) f + PQ
mW
** The formulas given are for the typical characteristics only.
be left open.
MC14415
6206

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL
TurnOff Delay Time

tPLH = (0.91 ns/pF) CL + 286 ns
tPLH
TurnOn Delay Time

tPHL = (0.75 ns/pF) CL + 289 ns
tPHL
TurnOn Delay Time (Inhibit to Output)
tPHL
TurnOff Delay Time (Inhibit to Output)
VDD
Vdc
Min
Typ #
Max
5.0
10
15
40
25
20
85
60
5.0
10
15
70
35
25
150
80
5.0
10
15
600
300
150
1200
600
5.0
10
15
600
300
150
1200
600
5.0
10
15
300
225
110
550
425
5.0
10
15
300
225
110
550
425
5.0
10
15
500
450
450
350
5.0
10
15
500
450
450
350
5.0
10
15
0.7
1.0
1.5
5.0
10
15
15
5.0
4.0
ns
ns
ns
ns
ns
tPLH
Input Pulse Coincidence (Figure 3)
ns
PCmin
Input Pulse Width (Figure 1)
ns
tWH
Input Clock Frequency
ns
fcl
Clock Input Rise and Fall Times (Figure 1)
Unit
MHz
tTLH, tTHL
20 ns
90%
50%
INPUT
tPLH
OUTPUT
10%
VSS
tWH
90%
VOH
50%
10%
tTLH
CLOCK
20 ns
VDD
VOL
tTHL
2
100
tPHL
OUTPUT
50%
VDD
VSS
VOH
VOL
Figure 1. Switching Characteristics Waveform Relationships
MC14415
6207
INPUT DISABLE
INPUT DISABLE
STROBE 2
STROBE 2
STROBE 1
STROBE 1
SET A
MINIMUM COINCIDENCE =
500 ns @ VDD = 4.75 Vdc
50%
OUTPUT SET
SET A
500 ns @ VDD = 4.75 Vdc
50%
OUTPUT SET
50%
OUTPUT INHIBIT
OUTPUT INHIBIT
1
CLOCK
CLOCK
100
50%
OUTPUT A
OUTPUT A
tPLH
100
50%
tPLH
tPHL
Mode 1: OUTPUT SET Initiates Time Delay
tPHL
Mode 2: Set A Initiates Time Delay
INPUT DISABLE
STROBE 2
INPUT DISABLE
STROBE 1
STROBE 2
SET A
50%
STROBE 1
50%
OUTPUT SET
500 ns @ VDD = 4.75 Vdc
SET A
50%
OUTPUT INHIBIT
CLOCK
OUTPUT A
OUTPUT SET
2
CLOCK
100
OUTPUT A
50%
tPLH
tPHL
tPLH
tPHL
Mode 3: OUTPUT INHIBIT Disables Time Delay
100
50%
tPLH
tPHL
Mode 4: PositiveEdge Strobe (ST2)

Initiates Time Delay
Figure 2. Typical Operation Modes and Functional Timing Diagram
MC14415
6208

CLOCK 1
INPUT DISABLE 10
STROBE 1 7
STROBE 2 9
OUTPUT SET 2
SET D 6
SET C 5
SET B 4
SET A 3
SCHMITT CLOCK
CONDITIONING
CIRCUIT
Q
R
Q
R
Q
R
Q
R
C1
C2
15
OUTPUT INHIBIT
DIVIDEBY100
SYNCHRONOUS
COUNTER
ENABLE
DIVIDEBY100
SYNCHRONOUS
COUNTER
ENABLE
C1
C2
DIVIDEBY100
C1 SYNCHRONOUS
COUNTER
ENABLE
C2
DIVIDEBY100
C1 SYNCHRONOUS
COUNTER
ENABLE
C2
C1
C2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
11 OUTPUT D
12 OUTPUT C
13 OUTPUT B
14 OUTPUT A
LOGIC DIAGRAM
MC14415
6209
MOTOROLA
MC14490
Hex Contact Bounce Eliminator
L SUFFIX
CERAMIC
CASE 620
The MC14490 is constructed with complementary MOS enhancement

mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact and
generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
make and the break of a contact closure. The clock for operation of the
MC14490 is derived from an internal RC oscillator which requires only an
external capacitor to adjust for the desired operating frequency (bounce
delay). The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after powerup, the outputs of the MC14490 are in
indeterminate states.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G

Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator (RC), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both Make and Break Contacts
Does Not Require Form C (Single Pole Double Throw) Input Signal
Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Chip Complexity: 546 FETs or 136.5 Equivalent Gates
MC14490P
MC14490L
MC14490DW
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
+VDD
DATA
4BIT STATIC SHIFT REGISTER
Ain 1
SHIFT
OSCin 7
OSCout 9
Bin 14
Cin 3
Din 12
Ein 5
Fin 10
MC14490
6210
OSCILLATOR
AND
TWOPHASE
CLOCK GENERATOR
LOAD
1 2
VDD = PIN 16
VSS = PIN 8
1 2
2 Bout
IDENTICAL TO ABOVE STAGE

13 Cout
4 Dout
15 Aout
1/2BIT
DELAY
11 Eout
6 Fout

Symbol
VDD
Vin, Vout
Parameter
DC Supply Voltage
Value
Unit
PIN ASSIGNMENT
0.5 to + 18.0
Ain
16
VDD
0.5 to VDD + 0.5
Bout
15
Aout
Iin
10
mA
Cin
14
Bin
PD
500
mW
13
Cout
Tstg
Storage Temperature
65 to + 150
_C
Dout
Ein
12
Din
Fout
11
Eout
OSCin
10
Fin
VSS
TL
260
_C
Plastic P and D/DW Packages: 7.0 MW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C to 125_C
OSCout

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

Oscillator Output
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
55_C
VDD
Vdc
Vdc
Vdc
IOH
mAdc
Source
Debounce Outputs
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Oscillator Output
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Sink
5.0
5.0
10
15
0.6
0.12
0.23
1.4
0.5
0.1
0.2
1.2
1.5
0.3
0.8
3.0
0.4
0.08
0.16
1.0
5.0
5.0
10
15
0.9
0.19
0.6
1.8
0.75
0.16
0.5
1.5
2.2
0.46
1.2
4.5
0.6
0.12
0.4
1.2
5.0
10
15
0.36
0.9
4.2
0.3
0.75
3.5
0.9
2.3
10
0.24
0.6
2.8
5.0
10
15
2.6
4.0
12
2.2
3.3
10
4.0
9.0
35
1.8
2.7
8.1
IOL
Debounce Outputs
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
mAdc
Input Current
Debounce Inputs (Vin = VDD)
IIH
15
2.0
0.2
2.0
11
Adc
Input Current Oscillator Pin 7

(Vin = VSS or VDD)
Iin
15
620
255
400
250
Adc
Pullup Resistor Source Current

Debounce Inputs
(Vin = VSS)
IIL
5.0
10
15
175
340
505
375
740
1100
140
280
415
190
380
570
255
500
750
70
145
215
225
440
660
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Vin = VSS or VDD, Iout = 0 A)
ISS
5.0
10
15
150
280
840
40
90
225
100
225
650
90
180
550
Adc
MC14490
6211
VDD
Vdc
Min
Typ #
Max
Unit
5.0
10
15
180
90
65
360
180
130
ns
5.0
10
15
100
50
40
200
100
80
ns
5.0
10
15
60
30
20
120
60
40
5.0
10
15
285
120
95
570
240
190
tPLH
5.0
10
15
370
160
120
740
320
240
Clock Frequency (50% Duly Cycle)

(External Clock)
fcl
5.0
10
15
2.8
6
9
1.4
3.0
4.5
MHz
Setup Time (See Figure 1)
tsu
5.0
10
15
100
80
60
50
40
30
ns
Maximum External Clock Input

Rise and Fall Time
Oscillator Input
tr, tf
5.0
10
15
Characteristic
Symbol
Output Rise Time

All Outputs
tTLH
Output Fall Time
Oscillator Output
tTHL
tTHL
Debounce Outputs

Oscillator Input to Debounce Outputs
ns
tPHL
Oscillator Frequency
OSCout
Cext 100 pF*
ns
No Limit
fosc, typ
Note: These equations are intended to be a design guide.

Laboratory experimentation may be required. Formulas
are typically 15% of actual frequencies.
Hz
1.5
Cext (in F)
4.5
Cext (in F)
5.0
10
6.5
Cext (in F)
15
*POWERDOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turnoff time of the power supply must not be faster than t = (VDD VSS) Cext / (10 mA). For example, If VDD VSS = 15 V and
Cext = 1 F, the power supply must turn off no faster than t = (15 V) (1 F) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
VDD
50%
OSCin
0V
tPLH
50%
Aout
90%
10%
D1
tr
tPHL
90%
10%
Aout
OSCin
50%
Ain
50%
9
OSCout
VDD
0V
tsu
D2
VDD
7
50%
tf
OSCin
Cext
VDD
MC14490
VDD
0V
Figure 1. Switching Waveforms

MC14490
6212
Figure 2. Discharge Protection During Power Down

THEORY OF OPERATION
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just after
N + 1, when the input bounces low, all bits are set to a high. At
N + 2 nothing happens because the input and output are low
and all bits of the shift register are high. At time N + 3 and
thereafter the input signal is a high, clean signal. At the positive edge of N + 6 the output goes high as a result of four lows
being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and output
signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency.
Since most relay contacts have more bounce when making
as compared to breaking, the overall delay, counting bounce
period, will be greater on the leading edge of the input signal
than on the trailing edge. Thus, the output signal will be
shorter than the input signal if the leading edge bounce is
included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at
the beginning of the input signal. The input signal goes low
three times before it finally settles down to a valid low state.
The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input
(pin 7). However, if an external clock is not available the user
can place a small capacitor across the oscillator input and
output pins in order to start up an internal clock source (as
shown in Figure 4). The clock signal at the oscillator output
pin may then be used to clock other MC14490 Bounce Eliminator packages. With the use of the MC14490, a large number of signals can be cleaned up, with the requirement of
only one small capacitor external to the Hex Bounce Eliminator packages.
The MC14490 Hex Contact Bounce Eliminator is basically

a digital integrator. The circuit can integrate both up and
down. This enables the circuit to eliminate bounce on both
the leading and trailing edges of the signal, shown in the timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
41/2bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in Figure 4. The shift register requires a series of timing pulses in
order to shift the input signal into each shift register location.
These timing pulses (the clock signal) are represented in the
upper waveform of Figure 3. Each of the six Bounce Eliminator circuits has an internal resistor as shown in Figure 4. A
pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such
as those coming from relay contacts and push buttons. By
switching ground, rather than a power supply lead, system
faults (such as shorts to ground on the signal input leads) will
not cause excessive currents in the wiring and contacts. Signal lead shorts to ground are much more probable than
shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high on
each positive edge of the clock signal. To understand the operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the
shift register to be reset to lows in all four bits thus starting
the timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 31/2 to 41/2 clock period delay between the clean input signal and output signal. In
this example there is a delay of 3.8 clock periods from the
beginning of the clean input signal.
N+1
N+3
N+5
N+7
OSCin OR OSCout
INPUT
OUTPUT
CONTACT
OPEN
CONTACT
BOUNCING
CONTACT CLOSED
(VALID TRUE SIGNAL)
CONTACT OPEN
CONTACT
BOUNCING
MC14490
6213
+VDD
PULLUP RESISTOR
(INTERNAL)
Ain
1
FORM A
CONTACT
OSCin 7
Cext
OSCout
DATA
4BIT STATIC SHIFT REGISTER
SHIFT
OSCILLATOR
AND
TWOPHASE
CLOCK GENERATOR
15
1/2 BIT
DELAY
Aout
LOAD
1 2
1 2
Figure 4. Typical Form A Contact Debounce Circuit

(Only One Debouncer Shown)
The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a builtin pullup resistor on each input. The
worst case value of the pullup resistor (determined from the
Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an
external resistor may be connected between VDD and the
input.
Because of the builtin pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is below 5 V. At this voltage, the input should be driven with paral-
leled standard gates or by the MC14049 or MC14050

buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow clock
edges, eliminating any need for clock preshaping. In addition, other MC14490 oscillator inputs can be driven from a
single oscillator output buffered by an MC14050 (see Figure 5). Up to six MC14490s may be driven by a single buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a
result of the internal input pullup resistors.
NO CONNECTION
9 OSCout
OSCin 7
Cext
OSCin
FROM CONTACTS
MC14490
1/6 MC14050
FROM
CONTACTS
OSCout
TO SYSTEM
LOGIC
MC14490
NO CONNECTION
9 OSCout
OSCin 7
FROM CONTACTS
TO SYSTEM
LOGIC
MC14490
TO SYSTEM
LOGIC
Figure 5. Typical Single Oscillator Debounce System
MC14490
6214
ASYMMETRICAL TIMING
MULTIPLE TIMING SIGNALS
In applications where different leading and trailing edge

delays are required (such as a fast attack/slow release
timer.) Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be interchanged. The clock out lead can then be used to feed clock
signals to the other MC14490 packages where the asymmetrical input/output timing is required.
As shown in Figure 8, the Bounce Eliminator circuits can

be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where it
is required to have a single pulse output for a single operation (make) of the push button or relay contact. This only
requires the series connection of two Bounce Eliminator circuits, one inverter, and one NOR gate in order to generate
the signal AB as shown in Figures 9 and 10. The signal AB is
four clock periods in length. If the inverter is switched to the A
output, the pulse AB will be generated upon release or break
of the contact. With the use of a few additional parts many
different pulses and waveshapes may be generated.
IN
OSCin
OUT
MC14490
OSCout
MC14011B
15
1
A
EXTERNAL
CLOCK
B.E. 1
B
fC
Ain
fC/N
14
Figure 6. Fast Attack/Slow Release Circuit
B.E. 2
Bin
13
LATCHED OUTPUT
B.E. 3
The contents of the Bounce Eliminator can be latched by

using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
IN
Aout
Cout
Cin
12
B.E. 4
Dout
Din
5
B.E. 5
11
Eout
Ein
OUT
10
MC14490
OSCin
Bout
OSCout
B.E. 6
Fout
Fin
MC14011B
CLOCK
OSCin
CLOCK
OSCout
LATCH = 1
UNLATCH = 0
Figure 8. Multiple Timing Circuit Connections

Figure 7. Latched Output Circuit
MC14490
6215
IN
BE 1
OUT
A
IN
OUT
BE 2
AB
A ACTIVE LOW
B ACTIVE LOW
Figure 9. Single Pulse Output Circuit
OSCin OR
OSCout
INPUT
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
be left open.
MC14490
6216
MOTOROLA
MC14500B
Industrial Control Unit
L SUFFIX
CERAMIC
CASE 620
The MC14500B Industrial Control Unit (ICU) is a singlebit CMOS

processor. The ICU is designed for use in systems requiring decisions based
on successive singlebit information. An external ROM stores the control
program. With a program counter (and output latches and input multiplexers,
if required) the ICU in a system forms a storedprogram controller that
replaces combinatorial logic. Applications include relay logic processing,
serial data manipulation and control. The ICU also may control an MPU or be
controlled by an MPU.
16 Instructions
DC to 1.0 MHz Operation at VDD = 5 V
OnChip Clock (Oscillator)
Executes One Instruction per Clock Cycle
3 to 18 V Operation
Low Quiescent Current Characteristic of CMOS Devices
Capable of Driving One LowPower Schottky Load or Two LowPower
TTL Loads over Full Temperature Range
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
DATA
PIN ASSIGNMENT
WRITE
C
D
+V
X1
X2
I0
I1
I2
I3
RST
IEN
14
13
16
OEN
STO
STOC
LU
VDD
VSS
MUX
OSC
D
7
6
5
INST
REG
C
RESULT
REG. (RR)
15
12
11
10
9
RST
16
VDD
WRITE
15
RR
DATA
14
X1
I3
13
X2
I2
12
JMP
I1
11
RTN
I0
10
FLAG O
VSS
FLAG F
RR
JMP
RTN
FLAG O
FLAG F
X1 OSCILLATOR OUTPUT
X2 OSCILLATOR INPUT
MC14500B
6217
v
v

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
Typ #
Max
Min
Max
Unit
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Input Voltage #
0 Level
I0, I1, I2, I3
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Min
5.0
10
15
VIL

Other Outputs
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
125_C
Max
VOL
Input Voltage
0 Level
RST, D, X2
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
25_C
Min
0 Level
Vin = 0 or VDD

Data, Write
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
55_C
VDD
Vdc
Source
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Vdc
5.0
10
15
0.8
1.6
2.4
1.1
2.2
3.4
0.8
1.6
2.4
0.8
1.6
2.4
5.0
10
15
2.0
6.0
10
2.0
6.0
10
1.9
3.1
4.3
2.0
6.0
10
Vdc
IOH
Sink
IOL
Source
IOH
Sink
Vdc
IOL
mAdc
5.0
10
15
1.2
3.6
7.2
1.0
3.0
6.0
2.0
6.0
12
0.7
2.1
4.2
5.0
10
15
1.9
3.6
7.2
1.6
3.0
6.0
3.2
6.0
12
1.1
2.1
4.2
mAdc
mAdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
MC14500B
6218
ELECTRICAL CHARACTERISTICS continued (Voltages Referenced to VSS)

55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
15
25
150
250
Adc
Input Current
Iin
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance (Data)
Cin
15
pF
Input Capacitance (All Other Inputs)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package) Iout = 0 A,
Vin = 0 or VDD
**Total Supply Current at an
External Load Capacitance (CL)
on All Outputs
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
Characteristic
Symbol
Input Current, RST

Adc
SWITCHING CHARACTERISTICS* (TA = 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F;
CL = 130 pF + 1 TTL load for Data and Write.)
All Types
VDD
Vdc
Min
Typ #
Max
Unit
5.0
10
15
250
125
100
500
250
200
ns
X1 to Flag F, Flag O, RTN, JMP
5.0
10
15
200
100
85
400
200
170
X1 to Write
5.0
10
15
225
125
100
450
250
200
X1 to Data
5.0
10
15
250
120
100
500
240
200
RST to RR
5.0
10
15
250
125
100
500
250
200
RST to X1
5.0
10
15
450
200
150
Note 1
RST to Flag F, Flag O, RTN, JMP
5.0
10
15
400
200
150
800
400
300
RST to Write, Data
5.0
10
15
450
225
175
900
450
350
Characteristic
Propagation Delay Time, X1 to RR
Symbol
tPLH,
tPHL
Clock Pulse Width, X1
tW(cl)
5.0
10
15
400
200
180
200
100
90
ns
Rent Pulse Width, RST
tW(R)
5.0
10
15
500
250
200
250
125
100
ns
Setup Time Instruction
tsu(l)
5.0
10
15
400
250
180
200
125
90
ns
tsu(D)
5.0
10
15
200
100
80
100
50
40
th(l)
5.0
10
15
100
50
50
0
0
0
th(D)
5.0
10
15
200
100
100
100
50
50
Data
Hold Time Instruction
Data
ns
NOTE 1. Maximum Reset Delay may extend to onehalf clock period.

MC14500B
6219
f Clk , CLOCK FREQUENCY (Hz)
Pin No.
1M
100 k
10 k
10 k
100 k
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1 M
RC, CLOCK FREQUENCY RESISTOR
Symbols
Chip Reset
Write Pulse
Data In/Out
MSB Instruction Word
Bit 2 Instruction Word
Bit 1 Instruction Word
LSB Instruction Word
Negative Supply (Ground)
Flag on NOP F
Flag on NOP O
Subroutine Return Flag
Jump Instruction Flag
Oscillator Input
Oscillator Output
Result Register
Positive Supply
Figure 1. Typical Clock Frequency

versus Resistor (RC)
RST
Write
Data
I3
I2
I1
I0
VSS
Flag F
Flag O
RTN
JMP
X2
X1
RR
VDD
Table 1. MC14500B Instruction Set
Instruction Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Mnemonic
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NOPO
LD
LDC
AND
ANDC
OR
ORC
XNOR
STO
STOC
IEN
OEN
JMP
RTN
SKZ
NOPF
Action
No change in registers. RR
RR, Flag O
Load result register. Data
RR
RR
Load complement. Data
Logical AND. RR Data
RR
Logical AND complement. RR Data
RR
Logical OR. RR + Data
RR
Logical OR complement. RR + Data
RR
Exclusive NOR. If RR = Data, RR
1
Store. RR
Data Pin, Write
Store complement. RR
Data Pin, Write
Input enable. Data
IEN Register
Output enable. Data
OEN Register
Jump. JMP Flag
Return. RTN Flag
and skip next instruction
Skip next instruction if RR = 0
No change in registers. RR
RR, Flag F
ADDITIONAL
OUTPUT DEVICES
MC14599B
8
8BIT ADDRESSABLE LATCH
OUTPUTS
WITH BIDIRECTIONAL DATA
I/O ADDRESS
MEMORY
PROGRAM
COUNTER
DATA BUS
MEMORY
ADDRESS
4 BIT OP CODE
MC14512
8CHANNEL
DATA SELECTOR
I0, I1, I2, I3
CLOCK
MC14500B
ICU
TO PERIPHERAL
DEVICES
8
INPUTS
ADDITIONAL
INPUT DEVICES
DATA
Figure 2. Outline of a Typical Organization for a MC14500BBased System

MC14500B
6220
TIMING WAVEFORMS
Instructions
Instructions
NOPO, NOPF
RR, IEN, OEN remain unaffected
X1
RST
tW(R)
tPHL
(RESET TO XI)
IEN
REGISTER
OEN
REGISTER
RR
tPHL (RESET TO RR)
4BIT
INSTRUCTION
NOP0
NOPF
NOPO
FLAG 0
tPHL
tPLH
(DATA TO FLAG)
FLAG F
Instructions
Instructions
SKZ, JMP, RTN

RR, IEN, OEN remain unaffected
X1
tW(cl)
4BIT
INSTRUCTION
SKZ
JMP
RTN
JMP
RST
RR
JMP FLAG
RTN FLAG
tPHL
(RESET TO JUMP)
SKP F/F
INTERNAL
* Instructions Ignored.
MC14500B
6221
TIMING WAVEFORMS
Instructions STO, STOC, OEN
X1
4BIT
INSTRUCTION
STO
STOC
STO
STOC
NOP
OEN
DATA
STO
STOC
RR
tPLH, tPHL (X1 TO DATA)
OEN REGISTER
(INTERNAL)
WRITE
tPHL
tPLH
VALID WHEN RST = L
NOTE 1. Valid output data.
Instructions
Instructions
LD, LDC, AND, ANDC

OR, ORC, XNOR, IEN
X1
LD, etc.
4BIT
INSTRUCTION
NOP
tsu(I)
IEN
LD, etc.
th(I)
DATA
tsu(D)
th(D)
RR
tPLH, tPHL (X1 TO RR)
IEN REGISTER
(INTERNAL)
VALID WHEN RST = L
MC14500B
6222
MOTOROLA
MC14501UB
Triple Gate

2Input NOR/OR Gate
8Input AND/NAND Gate
L SUFFIX
CERAMIC
CASE 620
The MC14501UB is constructed with MOS Pchannel and Nchannel

enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.

D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
CIRCUIT SCHEMATIC
VDD
P SUFFIX
PLASTIC
CASE 648
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
13
3
4
11
14 AND
12
5
6
7
9
15 NAND
10
VDD = PIN 16
VSS = PIN 8
Use Dotted Connection Externally to

Obtain 8Input AND/NAND
16
VDD
NOTE: Pin 14 must not be used as an input

NOTE: to the inverter.
11
13 (10)
12
(6) 1
14
(7) 2
15
VSS
(9) 3
(5) 4
VSS
VSS
Numbers in parenthesis are for second 4input gate.
MC14501UB
6223

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
3.75
2.25
4.50
6.75
1.5
3.0
3.75
1.4
2.9
3.6
5.0
10
15
3.6
7.1
11.4
3.5
7.0
11.25
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
VIL

(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
55_C
VDD
Vdc
Vdc
IOH
Source
NAND*
Vdc
mAdc
(VOH = 2.5 Vdc)

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc
(VOH = 13.5 Vdc)
NOR
5.0
5.0
10
15
2.1
0.42
1.06
3.1
1.75
0.35
0.88
2.63
3.0
0.63
1.58
6.12
1.22
0.24
0.62
1.84
mAdc
(VOH = 2.5 Vdc)

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
NOR
5.0
5.0
10
15
3.6
0.72
1.8
5.4
3.0
0.6
1.5
4.5
5.1
1.08
2.7
10.5
2.1
0.42
1.05
3.15
mAdc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
NAND*
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
NOR
5.0
10
15
0.92
2.34
6.12
0.77
1.95
5.1
1.32
3.37
13.2
0.54
1.36
3.57
mAdc
NOR
Inverter
5.0
10
15
1.54
3.90
10.2
1.28
3.25
8.5
2.2
5.63
22
0.90
2.27
5.95
mAdc
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Inverter

Per Package)
buffers switching)
IOL

Adc
MC14501UB
6224
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)

Characteristic
Output Rise Time

NAND, NOR
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
NAND, NOR
Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns
NORInverter
Output Fall Time

tTHL = (0.67 ns/pF) CL + 26.5 ns
tTHL = (0.45 ns/pF) CL + 17.5 ns
tTHL = (0.37 ns/pF) CL + 11.5 ns
NORInverter
Figure
Symbol
2, 3
tTLH
2, 3
VDD
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
60
40
30
120
80
60
50
10
15
130
70
50
260
140
100
Unit
ns
tTHL
ns
tTLH
ns
tTHL
ns

NAND

NOR
tPLH
tPHL
5.0
10
15
115
65
45
230
130
90
ns

NORInverter
tPLH,
tPHL
5.0
10
15
130
70
50
260
140
100
ns
tPLH,
tPHL
ns
be left open.
MC14501UB
6225
0.01 F
VDD
CERAMIC
16
PIN ASSIGNMENT
CL
Vin
CL
CL
CL
500 F
IDD
50% DUTY CYCLE
20 ns
90%
Vin
10%
VDD
90%
10%
20 ns
IN 1A
16
VDD
IN 2A
15
OUTB
IN 3A
14
OUTB
IN 4A
13
OUTA
IN 1C
12
IN 2B
IN 2C
11
IN 1B
IN 3C
10
OUTC
VSS
IN 4C
VSS

and Waveform
VDD
20 ns
16
PULSE
GENERATOR
INPUT (A)
OUTPUT
(B)
INPUT
(A) 8
VDD
90%
50%
10%
tPHL
CL
VSS
20 ns
90%
50%
10%
tPLH
90%
50%
10%
OUTPUT (B)
VSS
VOH
90%
50%
10%
tTHL
VOL
tTLH
Figure 2. Input NAND Gate Switching Time Test Circuit and Waveforms
20 ns
INPUT (A)
OUTPUT (B)
PULSE
GENERATOR
INPUT (A)
OUTPUT (C)
CL
Output (B) = NOR

Output (C) = NORInverter
CL
All unused inputs

VDD
90%
50%
10%
tPHL
tPLH
90%
50%
10%
OUTPUT (B)
tTHL
tPLH
OUTPUT (C)
tTLH
tTLH
90%
50%
10%
tTHL
VSS
VOH
VOL
tPHL
VOH
VOL
Figure 3. NOR Gate and NORInverter Switching Time Test Circuit and Waveforms
MC14501UB
6226
MOTOROLA

MC14502B
Strobed Hex Inverter/Buffer
L SUFFIX
CERAMIC
CASE 620
The MC14502B is a strobed hex buffer/inverter with 3state outputs, an

inhibit control, and guaranteed TTL drive over the temperature range. The
3state output simplifies design by allowing a common bus.
Separate Output Disable Control

3State Output
Capable of Driving 4LSTTL Loads Over the Rated Temperature Range
P SUFFIX
PLASTIC
CASE 648

Symbol
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
10
mA
Iout
+ 30
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
VDD
DC Supply Voltage
Vin, Vout
Iin
TL
Parameter
CIRCUIT DIAGRAM
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
3STATE
OUTPUT
4
DISABLE
INHIBIT 12
D1 3
5 Q1
DISABLE
VDD
INHIBIT
7 Q2
D2 6
2 Q3
D3 1
9 Q4
D4 10
D1
Q1
Other five buffers are identical
11 Q5
D5 13
14 Q6
D6 15
VSS
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Dn
Inhibit
Disable
Qn
High
Impedance
X = Dont Care
MC14502B
6227

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
3.5
7.8
29
2.8
6.3
24
6.6
17
66
2.0
4.4
16
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
Adc
0.1
3.0
Adc

MC14502B
6228
PIN ASSIGNMENT
D3
16
VDD
Q3
15
D6
D1
14
Q6
DISABLE
13
D5
Q1
12
INH
D2
11
Q5
Q2
10
D4
VSS
Q4
All Types
Characteristic
Symbol
VDD
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
40
20
15
80
40
30
ns
Propagation Delay Time Data to Q
tPHL
5.0
10
15
135
55
40
270
110
80
ns
Propagation Delay Time, Inhibit to Q
tPHL
5.0
10
15
335
145
95
670
290
190
ns
Propagation Delay Time Data to Q, Inhibit to Q
tPLH
5.0
10
15
295
130
95
590
260
190
ns
3State Propagation Delay, Output 1 to High Impedance
tPHZ
5.0
10
15
65
30
25
130
60
50
ns
3State Propagation Delay, High Impedance to 1 Level
tPZH
5.0
10
15
260
105
80
520
210
160
ns
3State Propagation Delay, Output 0 to High Impedance
tPLZ
5.0
10
15
150
70
55
300
140
110
ns
3State Propagation Delay, High Impedance to 0 Level
tPZL
5.0
10
15
160
65
50
320
130
100
ns
16
16
DIS
INH
D1
D2
D3
D4
D5
D6
+ VDD
+ VDD
Q1
Q2
Q3
Q4
Q5
Q6
VOH
IOH
Vout
VGS = VDD
VDS = VOH VDD
DIS
INH
D1
D2
D3
D4
D5
D6
Q1
Q2
Q3
Q4
Q5
Q6
VOL
IOL
Vout
VDS = VOL
VGS = VDD
VSS
VSS

Current Test Circuit (IOH)

Current Test Circuit (IOL)
MC14502B
6229
VDD
ID
DIS
INH
D1
D2
D3
D4
D5
D6
PULSE
GENERATOR
20 ns
90%
Vin
Q1
Q2
Q3
Q4
Q5
Q6
CL
CL
CL
CL
CL
CL
20 ns
VDD
50%
10%
50%
DUTY
CYCLE
VSS
Switch Positions for 3State Test
16
VDD
DISABLE
INHIBIT Q1
Q2
D1
Q3
D2
Q4
D3
Q5
D4
Q6
D5
D6
PULSE
GENERATOR
Test
S1
S2
S3
S4
tPHZ
tPLZ
tPZL
tPZH
Open
Closed
Closed
Open
Closed
Open
Open
Closed
Closed
Open
Open
Closed
Open
Closed
Closed
Open
CL
16
PULSE
GENERATOR
DISABLE
INHIBIT Q1
Q2
D1
Q3
D2
Q4
D3
Q5
D4
Q6
D5
D6
VDD
VSS
VDD
S4
S3
VDD
CL
1k
S1
S2
VSS
For all tTLH, tTHL, tPHL, and tPLH measurements Vin

may be applied to any other Dn input or to inhibit.
20 ns
20 ns
20 ns
VDD
90%
INPUT
50%
tPHL
50%
DISABLE
10%
OUTPUT
(TESTS 1 AND 2)
10%
tTHL
10%
VSS
90%
10%
VOH
50%
VDD
tPZL
tPLZ
tPLH
90%
20 ns
90%
Q OUTPUTS
VOL
tTLH
tPHZ
tPZH
90%
10%
Figure 4. AC Test Circuit and Waveforms

(tTLH, tTHL, TPLH, and tPHL)
MC14502B
6230
VSS
VOH
0.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
Figure 5. 3State AC Test Circuit and Waveforms

(tPHZ, tPLZ, tPZH, tPZL)
MOTOROLA
MC14503B
Hex Non-Inverting 3-State
Buffer
L SUFFIX
CERAMIC
CASE 620
The MC14503B is a hex noninverting buffer with 3state outputs, and a

high current source and sink capability. The 3state outputs make it useful in
common bussing applications. Two disable controls are provided. A high
level on the Disable A input causes the outputs of buffers 1 through 4 to go
into a high impedance state and a high level on the Disable B input causes
the outputs of buffers 5 and 6 to go into a high impedance state.
3State Outputs
TTL Compatible Will Drive One TTL Load Over Full Temperature
Range
Two Disable Controls for Added Versatility
Pin for Pin Replacement for MM80C97 and 340097

Symbol
VDD
Parameter
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
10
mA
Iout
25
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Vin, Vout
Iin
DC Supply Voltage
Value
TL
260
_C
CIRCUIT DIAGRAM
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TRUTH TABLE
Inn
0
Appropriate
Disable
Input
0
Outn
0
High
Impedance
X = Dont Care
ONE OF TWO/FOUR BUFFERS

VDD
LOGIC DIAGRAM
* INn
OUTn
DISABLE B
IN 5
* DISABLE
* INPUT
IN 6
VSS
IN 1
TO OTHER BUFFERS
IN 2
* Diode protection on all inputs (not shown)
IN 3
IN 4
DISABLE A
15
12
11
14
13
10
OUT 5
OUT 6
OUT 1
OUT 2
OUT 3
OUT 4
1
VDD = PIN 16
VSS = PIN 8
MC14503B
6231

Characteristic
Output Voltage
Vin = 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
4.5
5.0
5.0
10
15
4.3
5.8
1.2
3.1
8.2
3.6
4.8
1.02
2.6
6.8
5.0
6.1
1.4
3.7
14.1
2.5
3.0
0.7
1.8
4.8
IOL
4.5
5.0
10
15
2.2
2.6
6.5
19.2
1.8
2.1
5.5
16.1
2.1
2.3
6.2
25
1.2
1.3
3.8
11.2
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IQ
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
(CL = 50 pF on all outputs)
(All outputs switching,
50% Duty Cycle)
IT
5.0
10
15
ThreeState Output Leakage

Current
ITL
15
Vin = VDD
Input Voltage
0 Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
VIL
1 Level
VIH
(VO = 1.4 or 3.6 Vdc)

(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)

(VOH = 2.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
MC14503B
6232

Characteristic
Symbol
All Types
VDD
VCC
Typ #
Max
5.0
10
15
45
23
18
90
45
35
5.0
10
15
45
23
18
90
45
35
5.0
10
15
75
35
25
150
70
50
5.0
10
15
75
35
25
150
70
50
Unit
Output Rise Time

tTLH = (0.3 ns/pF) CL + 8.0 ns
tTLH = (0.2 ns/pF) CL + 8.0 ns
tTLH
ns
Output Fall Time

tTHL = (0.3 ns/pF) CL + 8.0 ns
tTHL = (0.2 ns/pF) CL + 8.0 ns
tTHL
TurnOff Delay Time, all Outputs

tPLH
TurnOn Delay Time, all Outputs

tPHL
3State Propagation Delay Time

tPHZ
5.0
10
15
75
40
35
150
80
70
ns
tPLZ
5.0
10
15
80
40
35
160
80
70
ns
High Impedance to 1 Level
tPZH
5.0
10
15
65
25
20
130
50
40
ns
tPZL
5.0
10
15
100
35
25
200
70
50
ns
ns
ns
ns
PIN ASSIGNMENT
DIS A
16
VDD
IN 1
15
DIS B
OUT 1
14
IN 6
IN 2
13
OUT 6
OUT 2
12
IN 5
IN 3
11
OUT 5
OUT 3
10
IN 4
VSS
OUT 4
MC14503B
6233
DISABLE
INPUT
20 ns
20 ns
VDD
90%
VDD
16
50%
INPUT
INPUT
10%
tPLH
PULSE
GENERATOR
OUTPUT
VSS
90%
50%
OUTPUT
CL
VSS
tPHL
VOH
10%
VOL
tTHL
tTLH
tPLH
tPHL

(tTLH, tTHL, tPHL, and tPLH)
DISABLE INPUT
DISABLE INPUT
PULSE
GENERATOR
VDD
tPHZ, tPZH CIRCUIT
tPLZ, tPZL CIRCUIT
PULSE
GENERATOR
VDD
16
16
INPUT
OUTPUT
8
1k
VSS
INPUT
OUTPUT
CL
20 ns
10%
VSS
tPZL
VOH
90%
10%
VOL + 0.05 V
tPHZ
OUTPUT FOR tPHZ, tPLZ CIRCUIT
CL
VDD
tPLZ
OUTPUT FOR tPZH, tPZL CIRCUIT
VSS
20 ns
90%
50%
DISABLE INPUT
1k
tPZH
VOH 0.15 V
90%
10%
VOL

(tPLZ, tPHZ, tPZH, tPZL)
MC14503B
6234
MOTOROLA
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
L SUFFIX
CERAMIC
CASE 620
The MC14504B is a hex noninverting level shifter using CMOS

technology. The level shifter will shift a TTL signal to CMOS logic levels for
any CMOS supply voltage between 5 and 15 volts. A control input also
allows interface from CMOS to CMOS at one logic level to another logic
level: Either up or down level translating is accomplished by selection of
power supply levels VDD and VCC. The VCC level sets the input signal levels
while VDD selects the output voltage levels.
UP Translates from a Low to a High Voltage or DOWN Translates from
a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up or
Power Down
3 to 18 Vdc Operation for VDD and VCC
Diode Protected Inputs to VSS
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
PIN ASSIGNMENT
VCC
VDD
LEVEL
SHIFTER
INPUT
OUTPUT
TTL/CMOS
MODE SELECT
MODE
Mode Select
Input Logic
Levels
Output Logic
Levels
1 (VCC)
TTL
CMOS
0 (VSS)
CMOS
CMOS
1/6 of package shown.
16
VDD
Aout
15
Fout
Ain
14
Fin
Bout
13
MODE
Bin
12
Eout
Cout
11
Ein
Cin
10
Dout
VSS
Din
This device contains circuitry to protect

the inputs against damage due to high static
voltages or electric fields referenced to the
VSS pin, only. Extra precautions must be
taken to avoid applications of any voltage
higher than maximum rated voltages to this
highimpedance circuit. For proper operation, the ranges VSS Vin 18 V and VSS
Vout
VDD are recommended.
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.
VCC
v v
MC14504B
6235

Symbol
Value
Unit
VCC
DC Supply Voltage
0.5 to 18.0
VDD
DC Supply Voltage
0.5 to + 18.0
Vin
0.5 to + 18.0
Vout
0.5 to VDD + 0.5
Input or output Current (DC or Transient),

per Pin
10
mA
PD
Power Dissipation, per Package*
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
Iin, Iout
TL
Parameter
55_C
25_C
125_C
VCC
Vdc
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
5.0
5.0
10
10
15
10
15
15
0.8
0.8
1.5
1.5
3.0
1.3
1.3
2.25
2.25
4.5
0.8
0.8
1.5
1.5
3.0
0.8
0.8
1.4
1.5
2.9
5.0
5.0
5.0
5.0
10
10
15
10
15
15
2.0
2.0
3.6
3.6
7.1
2.0
2.0
3.5
3.5
7.0
1.5
1.5
2.75
2.75
5.5
2.0
2.0
3.5
3.5
7.0
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Cin
5.0
7.5
pF
IDD or
ICC
5.0
10
15
0.05
0.10
0.20
0.0005
0.0010
0.0015
0.05
0.10
0.20
1.5
3.0
6.0
Adc
Quiescent Current
(Per Package)
TTLCMOS Mode
IDD
5.0
5.0
5.0
5.0
10
15
0.5
1.0
2.0
0.0005
0.0010
0.0015
0.5
1.0
2.0
3.8
7.5
15
Adc
Quiescent Current
(Per Package)
TTLCMOS Mode
ICC
5.0
5.0
5.0
5.0
10
15
5.0
5.0
5.0
2.5
2.5
2.5
5.0
5.0
5.0
6.0
6.0
6.0
mAdc
Characteristic
Output Voltage
Vin = 0 V
Symbol
0 Level
1 Level
Vin = VCC
Input Voltage
0 Level
(VOL = 1.0 Vdc) TTLCMOS
(VOL = 1.5 Vdc) TTLCMOS
(VOL = 1.0 Vdc) CMOSCMOS
VIL
Input Voltage
1 Level
(VOH = 9.0 Vdc) TTLCMOS
(VOH = 13.5 Vdc) TTLCMOS
(VOH = 9.0 Vdc) CMOSCMOS
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Quiescent Current
(Per Package)
CMOSCMOS Mode
Source
Sink
Vdc
Vdc
mAdc
MC14504B
6236

Characteristic
Propagation Delay, High to Low
Propagation Delay, Low to High
VDD
Vdc
Min
Typ #
Max
Unit
TTL CMOS
VDD > VCC
CMOS CMOS
VDD > VCC
5.0
5.0
10
15
140
140
280
280
ns
5.0
5.0
10
10
15
15
120
120
70
240
240
140
CMOS CMOS
VCC > VDD
10
15
15
5.0
5.0
10
185
185
175
370
370
350
TTL CMOS
VDD > VCC
CMOS CMOS
VDD > VCC
5.0
5.0
10
15
170
160
340
320
5.0
5.0
10
10
15
15
170
170
100
340
340
200
CMOS CMOS
VCC > VDD
10
15
15
5.0
5.0
10
275
275
145
550
550
290
ALL
5.0
10
15
100
50
40
200
100
80
Shifting Mode
tPHL
tPLH
Limits
VCC
Vdc
Symbol
tTLH, tTHL
ns
ns
7
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
VSp , INPUT SWITCHPOINT VOLTAGE (Vdc)
7
6
VCC = 10 V
5
4
3
VCC = 5 V
2
1
0
5
4
3
2
VCC = 5 V
1
0
5
10
15
VDD, SUPPLY VOLTAGE (Vdc)
20
Figure 1. Input Switchpoint CMOS to CMOS Mode
15
10
20
20
5
10
15
Figure 2. Input Switchpoint TTL to CMOS Mode
20
15
10
0
0
5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 3. Operating Boundary CMOS to CMOS Mode

5
10
15
VCC, SUPPLY VOLTAGE (Vdc)
20
Figure 4. Operating Boundary TTL to CMOS Mode

MC14504B
6237
MOTOROLA

MC14506UB
Dual 2-Wide, 2-Input
Expandable AND-OR-INVERT
L SUFFIX
CERAMIC
CASE 620
Gate
The MC14506UB is an expandable ANDORINVERT gate with inhibit
and 3state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4wide,
2input AOI gate. This device is useful in data control and digital multiplexing
applications.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
3State Output
Separate Inhibit Line
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL

to the range VSS
(Vin or Vout)
VDD.
TRUTH TABLE
A B C D E
LOGIC DIAGRAM
AA
BA
CA
DA
EA
1
2
3
4
5
15 ZA
VDD = PIN 16
VSS = PIN 8
INH 6
DIS 14
3STATE
OUTPUT DISABLE
Inhibit Disable
0
0
0
X
0
X
X
0
0
0
X
0
0
X
0
X
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
X
1
X
X
0
1
X
X
X
X
1
X
0
X
1
X
1
X
X
0
0
X
X
X
0
0
0
0
1
0
0
0
X X X X X
X X X X X
1
X
0
1
0
High
Impedance
X = Dont Care
EB 13
DB 12
CB 11
BB 10
AB 9
MC14506UB
6238
7 ZB
Z = (AB + CD + E + I)

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
PIN ASSIGNMENT
AA
16
VDD
BA
15
ZA
CA
14
DISABLE
DA
13
EB
EA
12
DB
INH
11
CB
ZB
10
BB
VSS
AB
MC14506UB
6239

Characteristic
Symbol

VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
295
110
75
580
225
180
5.0
10
15
270
95
65
480
175
140
5.0
10
15
180
75
50
430
160
125
5.0
10
15
200
80
55
330
110
90
5.0
10
15
220
100
65
500
225
160
5.0
10
15
230
95
60
400
175
150
5.0
10
15
60
45
35
150
110
90
Unit
tTLH, tTHL
Data Propagation Delay Time

tPLH

tPHL
Expand Propagation Delay Time

tPLH

tPHL
Inhibit Propagation Delay Time

tPLH

tPHL

1 to High Impedance
ns
ns
ns
ns
ns
ns
ns
tPHZ
ns
0 to High Impedance
tPLZ
5.0
10
15
90
55
40
225
140
100
ns
High Impedance to 1
tPZH
5.0
10
15
110
50
40
300
125
100
ns
High Impedance to 0
tPZL
5.0
10
15
170
70
50
425
175
125
ns
#Data labelled Typ Is not to be used for design purposes but is intended as an indication of the ICs potential performance.
16
16
VDD = 15 Vdc
a
b
c
12
10
10 Vdc
a
b
c
8.0
6.0
UNUSED INPUTS
CONNECTED TO
VSS
5.0 Vdc
a
4.0 b
a
b
c
2.0
0
0
2.0
14
14
4.0
6.0
8.0
10
TA = + 125C
TA = + 25C
TA = 55C
12
14
VDD = 15 Vdc
12
a TA = + 125C
b TA = + 25C
c TA = 55C
b
c
10 Vdc
a
b
10
8.0
A AND B CONNECTED TO Vin

ENABLE INPUT CONNECTED TO
VDD. OTHER INPUTS CONNECTED
TO VSS.
6.0
5.0 Vdc
4.0 a
b
c
2.0
0
16
2.0
4.0
6.0
8.0
10
(a) Expand Inputs
(b) Data Inputs
12
14
16
Figure 1. Typical Voltage Transfer Characteristics

MC14506UB
6240
VDD
16
VDD
16
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
ZA
VOH
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
IOH
EXTERNAL
POWER
SUPPLY
ZB
VSS

ZA
VOL
IOL
EXTERNAL
POWER
SUPPLY
ZB
VSS

VDD
16
VDD
16
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
8
0.01 F
CERAMIC
VDD
ZA
ITL
PULSE
GENERATOR
50% DUTY CYCLE
ZB
VSS
Figure 4. 3State Leakage Current

Test Circuit
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
ZA
ZB
VSS
CL
500 F
CL
IDD
Figure 5. Typical Power Dissipation

Test Circuit
MC14506UB
6241
VDD
16
PULSE
GENERATOR
ZA
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
ZB
VSS
20 ns
20 ns
VSS
tPLH
VOH
tPHL
90%
50%
10%
OUTPUT
CL
VDD
90%
50%
10%
INPUT
VOL
tTHL
CL
tTLH

(Data Inputs)
VDD
Vout
VDD
16
B
A
PULSE
GENERATOR
S1
INH
AA
BA
CA
DA
EA
AB
BB
CB
DB
EB
DIS
ZA
VSS
20 ns
CL
S2
20 ns
90%
50%
10%
DISABLE
INPUT
1k
A
tPZL
90%
tPLZ
10%
tPHZ
OUTPUT
ZB
90%
tPZH
10%
VOH
2.5 V @ VDD = 5 V,
10 V AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
* To test other side of circuit connect to this output and

change switch (S1) to other expand input (E).
SWITCH POSITIONS
TEST
S1
S2
tPLZ
tPHZ
tPZL
tPZH

(For 3State Output)
MC14506UB
6242
MOTOROLA
MC14508B
Dual 4-Bit Latch
The MC14508B dual 4bit latch is constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic structure. The
part consists of two identical, independent 4bit latches with separate Strobe
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications.
These complementary MOS latches find primary use in buffer storage,
holding register, or general digital logic functions where low power
dissipation and/or high noise immunity is desired.
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
3State Output
Capableof Driving Two Lowpower TTL Loads or One Lowpower

Symbol
VDD
Vin, Vout
Iin, Iout
PD
Tstg
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA
500
mW
65 to + 150
_C

Storage Temperature
Disable
0
D3
0
D2
0
D1
0
D0
0
Q3
0
Q2
0
Q1
0
Q0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
X
X
X
0
1
X
X
X
X
X
X
X
X
Latched
0
0
0
0
High Impedance
CIRCUIT DIAGRAM
Plastic
Ceramic
SOIC
1
2
3
4
6
8
10
MR
ST
DIS
D0
D1
D2
D3
Q0
Q1
Q2
Q3
11
13
14
15
16
18
20
22
MR
ST
DIS
D0
D1
D2
D3
Q0
17
Q1
19
Q2
21
Q3
23
VDD = PIN 24
VSS = PIN 12
X = Dont Care
DIS
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
BLOCK DIAGRAM
TRUTH TABLE
ST
1
TL
260
_C
MR
0
DW SUFFIX
SOIC
CASE 751E
VDD
MR
ST
Qn
Dn
(TO OTHER THREE LATCHES)

VSS
MC14508B
6243

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
be left open.
MC14508B
6244
All Types
Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
90
60
440
180
120
tWH(R)
5.0
10
15
200
100
70
100
50
35
ns
trem
5.0
10
15
30
25
20
15
0
0
ns
tWH(S)
5.0
10
15
140
70
40
70
35
20
ns
Setup Time
Data to Strobe
tsu
5.0
10
15
50
20
10
25
10
5.0
ns
Hold Time
Strobe to Data
th
5.0
10
15
50
35
35
20
10
10
ns
5.0
10
15
55
35
30
170
100
70

tTLH, tTHL
Propagation Delay Time, Dn or MR to Q

tPLH, tPHL
Master Reset Pulse Width
Master Reset Removal Time
Strobe Pulse Width
Unit
ns
ns
ns

tPHZ
tPLZ
5.0
10
15
75
40
35
170
100
70
tPZH
5.0
10
15
80
35
30
170
100
70
tPZL
5.0
10
15
105
50
35
210
100
70
PIN ASSIGNMENT
MRA
24
VDD
STA
23
Q3B
DISA
22
D3B
D0A
21
Q2B
Q0A
20
D2B
D1A
19
Q1B
Q1A
18
D1B
D2A
17
Q0B
Q2A
16
D0B
D3A
10
15
DISB
Q3A
11
14
STB
VSS
12
13
MRB
MC14508B
6245
tWH(S)
STROBE
INPUT
50%
50%
tsu
tWH(R)
th
Dn INPUT
MASTER RESET
INPUT
50%
tPLH
Qn OUTPUT
tPHL
10%
VSS
VOH
Qn OUTPUT
90%
50%
tTLH
VDD
50%
VOL
tTHL
Figure 1. AC Waveforms
VDD
MR
ST
DISABLE
D0
D1
D2
D3
PULSE
GENERATOR
VDD
ST3
VDD
Q0
ST1
Q1
Q2
1.0 k
Test
ST1
ST2
ST3
ST4
tPHZ
tPLZ
tPZL
tPZH
Open
Close
Close
Open
Close
Open
Open
Close
Close
Open
Open
Close
Open
Close
Close
Open
Q3
1.0 k
ST4
VSS
CL
ST2
20 ns
20 ns
DISABLE
VDD
90%
50%
10%
tPLZ
tPZL
90%
10%
Q3 OUTPUT
tPHZ
VSS
VOH
2.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
tPZH
90%
10%
MC14508B
6246
IOD
3STATE MODE OF OPERATION

The MC14508B can be used in bussed systems as shown.
The output terminals of N 4bit latches can be directly wired
to a bus line, and to one of the 4bit latches selected. The
selected latch controls the logic state of the bus line and the
remaining (N1) 4bit latches are disabled into a high impedance off state. The number of latches, N, which may be
connected to a bus line is determined from the output drive
current, IOD, the 3state or disabled output leakage current,
ITL, and the load current, IL, required to drive the bus line (including fanout to other device inputs) and can be calculated
by the following:
IOD IL
N=
+1
ITL
SELECTED AS
1/2
DRIVING DEVICE MC14508B
IOD
ITL
1/2
DISABLED
MC14508B
ITL
N must be calculated for both high and low logic states of the
bus line.
ITL
1/2
DISABLED
MC14508B
ITL
IL
IL
BUS LINES
TYPICAL 3STATE APPLICATIONS

EXAMPLE 1
RESET
CLOCK
MC14015B
SERIAL
DATA
4BIT SHIFT
REGISTER
4BIT SHIFT
REGISTER
MC
QUAD LATCH 14508B
(3STATE)
QUAD LATCH
(3STATE)
STROBE
DISABLE
DISABLE
4LINE DATA BUS
EXAMPLE 2
DATA BUS
3STATE
4BIT LATCH
3STATE
4BIT LATCH
MC
14508B
MC
14508B
4LINE DATA BUS
4LINE DATA BUS
MC14519B
A
B
3STATE
4BIT LATCH
3STATE
4BIT LATCH
MC14508B
6247
MOTOROLA

MC14510B
BCD Up/Down Counter
The MC14510B synchronous up/down BCD counter is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a monolithic
structure. The counter consists of type D flipflop stages with a gating
structure to provide type T flipflop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the
Reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analogto
digital and digitaltoanalog conversions, and (3) Magnitude and sign
generation.

of Clock

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the may occur.
TRUTH TABLE
Carry In
Up/Down
Preset
Enable
Reset
Clock
Action
No Count
Count Up
Count Down
Preset
Reset
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
1
5
9
10
15
4
12
13
3
Q1
PE
CARRY IN
R
Q2
UP/DOWN
CLOCK
Q3
P1
P2
Q4
P3
CARRY
P4
OUT
6
11
14
2
7
VDD = PIN 16
VSS = PIN 8

to the range VSS
(Vin or Vout)
VDD.
X = Dont Care
NOTE: When counting up, the Carry Out signal is normally high, and is low only
when Q1 and Q4 are high and Carry In is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.
MC14510B
6248

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
PE
16
VDD
Q4
15
P4
14
Q3
P1
13
P3
CARRY IN
12
P2
Q1
11
Q2
CARRY OUT
10
U/D
VSS
MC14510B
6249
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, See Figure 2)
All Types
Characteristic

Clock to Q
Symbol
tTLH,
tTHL
tPLH,
tPHL
Clock to Carry Out

tPLH,
tPHL

tPLH,
tPHL
Preset or Reset to Q
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
315
130
100
630
260
200
5.0
10
15
315
130
100
630
260
200
5.0
10
15
180
80
60
360
160
120
5.0
10
15
315
130
100
630
260
200
5.0
10
15
550
225
150
1100
450
300
ns
ns
ns
Preset or Reset to Carry Out

Reset Pulse Width
tPLH,
tPHL
tw(H)
5.0
10
15
360
210
160
180
105
80
ns
Clock Pulse Width
tw(H)
5.0
10
15
350
170
140
200
100
75
ns
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time

The Preset or Reset Signal must be low prior to a
positivegoing transition of the clock.
trem
5.0
10
15
650
230
180
325
115
90
ns
tTLH,
tTHL
5.0
10
15
15
5
4
Setup Time
Carry In to Clock
tsu
5.0
10
15
260
120
100
130
60
50
ns
Hold Time
Clock to Carry In
th
5.0
10
15
0
10
10
50
15
5
ns
Setup Time
Up/Down to Clock
tsu
5.0
10
15
500
200
175
250
100
75
ns
Hold Time
Clock to Up/Down
th
5.0
10
15
70
30
20
140
80
50
ns
Setup Time
Pn to PE
tsu
5.0
10
15
50
30
25
100
65
55
ns
Hold Time
PE to Pn
th
5.0
10
15
480
410
410
240
205
205
ns
tWH
5.0
10
15
200
100
80
100
50
40
ns
ns
MC14510B
6250
VDD
0.01 F
CERAMIC
ID
500 pF
Q1
PE
CARRY IN
Q2
R
UP/DOWN
CLOCK Q3
PULSE
GENERATOR
CL
P1
P2
P3
Q4
P4
CARRY
OUT
CL
CL
CL
CL
20 ns
CLOCK
20 ns
50%
VDD
90%
10%
VSS
VARIABLE
WIDTH
VDD
PE
Q1
CARRY IN
Q2
R
UP/DOWN
CLOCK Q3
PROGRAMMABLE
PULSE
GENERATOR
CL
P1
P2
P3
Q4
P4
CARRY
OUT
CL
CL
CL
CL
VSS
tsu
CARRY IN OR
UP/DOWN
trem
1
fcl
VDD
50%
VSS
VDD
50%
CLOCK
tw(H)
VSS
VDD
tw(H)
PRESET ENABLE
VSS
20 ns
tTLH
CARRY OUT ONLY
VOH
90%
10%
90%
10%
Q1 OR CARRY OUT
VOL
tPHL
tTHL
tPLH
trem
tPLH
RESET
VDD
VSS
tw(H)
MC14510B
6251
LOGIC DIAGRAM
P1
4
Q1
6
P2
12
Q2
11
P3
13
Q3
14
P4
3
Q4
2
RESET
PRESET ENABLE
CLOCK
PE
CARRY OUT
C
D
PE
PE
C
Q
PE
CARRY IN
UP/DOWN
STATE DIAGRAM FOR UP COUNTING
15
15
14
14
13
13
12
12
MC14510B
6252
11
10
STATE DIAGRAM FOR DOWN COUNTING
11
10
PIN DESCRIPTIONS
INPUTS
synchronous output is active low and may also be used to

indicate terminal count.
P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) Activelow input used when cascading
stages. Usually connected to Carry Out of the previous
stage. While high, clock is inhibited.
Clock, (Pin 15) BCD data is incremented or decremented, depending on the direction of count, on the positive transition of this signal.
OUTPUTS
CONTROLS
PE, Preset Enable (Pin 1) Asynchronously loads data
on the Preset Inputs. This pin is active high and will inhibit the
clock when high.
R, Reset, (Pin 9) Asynchronously resets the Q outputs
to a low state. This pin is active high and will inhibit the clock
when high.
Up/Down, (Pin 10) Controls the direction of count: high
for up count, low for down count.
SUPPLY PINS
Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) BCD
data is present on these outputs with Q1 corresponding to
the least significant bit.
Carry Out, (Pin 7) Used when cascading stages, this
pin is usually connected to Carry In of the next stage. This
PRESET
ENABLE
0 = COUNT
1 = PRESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q1
PE
Q2
Q3
Q4
Q1
PE
Q2
Q3
Q4
Cout
Cin
CLOCK
Cin
CLOCK
1 = UP
0 = DOWN
L.S.D.
MC14510B
U/D
R
P2
P2
P3
P3
P4
P4
+ VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
+ VDD
P1
P5
Cout
M.S.D.
MC14510B
U/D
R
P1
P1
CLOCK
VSS, Negative Supply Voltage, (Pin 8) This pin is

usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) This pin is connected to a positive supply voltage ranging from 3.0 Vdc to
18.0 Vdc.
P2
P6
P3
P7
TERMINAL
COUNT
INDICATOR
P4
P8
+ VDD
RESISTORS = 10 k
RESET
OPEN = COUNT
Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) does not change while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9
(count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one
count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8Bit Up/Down Counter
MC14510B
6253
TIMING DIAGRAM FOR THE PRESETTABLE

CASCADED 8BIT UP/DOWN COUNTER
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P8
P7
P6
P5
P4
P3
P2
P1
CARRY OUT
(MSD)
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CARRY OUT
(LSD)
RESET
COUNT MSD
COUNT LSD
PRESET
ENABLE
PRESET ENABLE
UP COUNT
MC14510B
6254
DOWN COUNT
UP COUNT
DOWN
COUNT
RESET
UP COUNT
fout
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q1
PE
Q2
Q3
Q4
Q1
PE
Q2
Q3
Q4
Cout
Cin
CLOCK
Cin
CLOCK
L.S.D.
MC14510B
U/D
R
+ VDD
P2
P1
P0
CLOCK (fin)
U/D
R
P1
P3
P2
P4
P3
+ VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
RESET
M.S.D.
MC14510B
P1
P4
P2
P5
P3
P6
BUFFER
Cout
P4
P7
+ VDD
RESISTORS = 10 k
f
fout = in
n
OPEN = COUNT
Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For
example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide
operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and
should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
MC14510B
6255
MOTOROLA
MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
L SUFFIX
CERAMIC
CASE 620
The MC14511B BCDtoseven segment latch/decoder/driver is

constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4bit storage latch, an 8421 BCDtoseven
segment decoder, and an output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turnoff or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. It can be used with sevensegment lightemitting diodes
(LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts
either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
DW SUFFIX
SOIC
CASE 751G
Low Logic Circuit Power Dissipation

HighCurrent Sourcing Outputs (Up to 25 mA)
Latch Storage of Code
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Facility
Capable of Driving Two Lowpower TTL Loads, One Lowpower
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
Chip Complexity: 216 FETs or 54 Equivalent Gates
Triple Diode Protection on all Inputs
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBDW
SOIC
MC14XXXBD
SOIC
PIN ASSIGNMENT

Rating
Symbol
Value
Unit
VDD
0.5 to + 18
Vin
0.5 to VDD + 0.5
DC Current Drain per Input Pin
10
mA
TA
55 to + 125
_C
Power Dissipation per Package
PD
500
mW
Tstg
65 to + 150
_C
Maximum Output Drive Current

(Source) per Output
IOHmax
25
mA
Maximum Continuous Output Power

(Source) per Output
POHmax
DC Supply Voltage
50
mW
POHmax = IOH (VDD VOH)

16
VDD
15
LT
14
BI
13
LE
12
11
10
VSS
a
f
c
d
DISPLAY
TRUTH TABLE
Inputs
LE BI LT
Outputs
Blank
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
2
3
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
Blank
Blank
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
1 1 1
X
X
X
X
*
X = Dont Care
* Depends upon the BCD code previously applied when LE = 0
MC14511B
6256
Display

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.1
9.1
14.1
4.1
9.1
14.1
4.57
9.58
14.59
4.1
9.1
14.1
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
4.1
3.9
3.4
4.1
3.9
3.4
4.57
4.24
4.12
3.94
3.70
3.54
4.1
3.5
3.0
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10
9.1
9.0
8.6
9.1
9.0
8.6
9.58
9.26
9.17
9.04
8.90
8.70
9.1
8.6
8.2
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15
14.1
14
13.6
14.1
14
13.6
14.59
14.27
14.18
14.07
13.95
13.70
14.1
13.6
13.2
Vdc
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Vin = 0 or VDD
Input Voltage #
0 Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 3.8 Vdc)

(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
Output Drive Voltage
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Vdc
Vdc
VOH
Source
Vdc
IOL
Sink
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package) Vin = 0 or VDD,
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15

Adc

Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
IT(CL) = IT(50 pF) + 3.5 x 103 (CL 50) VDDf
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
MC14511B
6257

Characteristic
Symbol
VDD
Vdc
Min
Typ
Max
5.0
10
15
40
30
25
80
60
50
5.0
10
15
125
75
65
250
150
130
5.0
10
15
640
250
175
1280
500
350
5.0
10
15
720
290
200
1440
580
400
5.0
I0
15
600
200
150
750
300
220
5.0
10
15
485
200
160
970
400
320
5.0
10
15
313
125
90
625
250
180
Unit
Output Rise Time

tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tTHL

tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH

tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
Blank Propagation Delay Time

tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPLH
tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
Lamp Test Propagation Delay Time

tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH

tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
313
125
90
625
250
180
Setup Time
tsu
5.0
10
15
100
40
30
ns
Hold Time
th
5.0
10
15
60
40
30
ns
tWL
5.0
10
15
520
220
130
260
110
65
ns
Latch Enable Pulse Width
ns
ns
ns
ns
ns
* The formulas given are for the typical characteristics only.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS (Vin or
Vout) VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
MC14511B
6258
Input LE low, and Inputs D, BI and LT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns
20 ns
VDD
90%
50%
1
2f
A, B, AND C
10%
VSS
50% DUTY CYCLE
VOH
50%
ANY OUTPUT
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
20 ns
VDD
90%
50%
10%
INPUT C
tPLH
VSS
tPHL
VOH
90%
50%
OUTPUT g
10%
tTLH
VOL
tTHL
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
LE
10%
VDD
90%
50%
th
VSS
tsu
VDD
INPUT C
50%
VSS
VOH
OUTPUT g
VOL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
20 ns
LE
VDD
90%
50%
10%
VSS
tWL
(c) Data DCBA strobed into latches.

MC14511B
6259
CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
1.7 V
1.7 V
VSS
VSS
INCANDESCENT READOUT
VDD
VDD
FLUORESCENT READOUT
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
VSS
VSS
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)
GAS DISCHARGE READOUT
VDD
APPROPRIATE
VOLTAGE
LIQUID CRYSTAL (LCD) READOUT

EXCITATION
(SQUARE WAVE,
VSS TO VDD)
VDD
1/4 OF MC14070B
VSS
** A filament prewarm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
MC14511B
6260
VSS
Direct dc drive of LCDs not recommended for life of
LCD readouts.
LOGIC DIAGRAM
BI 4
13 a
A 7
12 b
11 c
B 1
10 d
9 e
15 f
C 2
14 g
LT 3
D 6
LE 5
VDD = PIN 16
VSS = PIN 8
MC14511B
6261
MOTOROLA
MC14512B
8-Channel Data Selector
L SUFFIX
CERAMIC
CASE 620
The MC14512B is an 8channel data selector constructed with MOS

monolithic structure. This data selector finds primary application in signal
multiplexing functions. It may also be used for data routing, digital signal
switching, signal gating, and number sequence generation.
P SUFFIX
PLASTIC
CASE 648

Single Supply Operation
3State Output (Logic 1, Logic 0, High Impedance)

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
TRUTH TABLE
C
Inhibit
Disable
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X0
X1
X2
X3
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X4
X5
X6
X7
X
X
X
X
X
X
1
X
0
1
0
High
Impedance
X = Dont Care
MC14512B
6262
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
X0
16
VDD
X1
15
DIS
X2
14
X3
13
X4
12
X5
11
X6
10
INH
VSS
X7

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
MC14512B
6263
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C, See Figure 1)

All Types
Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z
tPLH
Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z
tPHL
3State Output Delay Times (Figure 3)

1 or 0 to High Z, and
High Z to 1 or 0
VDD
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
330
125
85
650
250
170
5.0
10
15
330
125
85
650
250
170
5.0
10
15
60
35
30
150
100
75
Unit
ns
ns
ns
tPHZ, tPLZ,
tPZH, tPZL
ns
ID
Vin
PULSE
GENERATOR
50%
50%
DUTY
CYCLE
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VDD
Z
CL
VSS

VDD
20 ns
20 ns
PULSE
GENERATOR
DATA
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
tPLH
CL
VDD
90%
50%
10%
VSS
tPHL
90%
50%
10%
VOH
VOL
tTLH
tTHL
TEST CONDITIONS:
INHIBIT = VSS
A, B, C = VSS
20 ns
INHIBIT,
A, B, OR C
VSS
Parameter
Test Conditions
Inhibit to Z
A, B, C = VSS, XO = VDD
A, B, C to Z
Inh = VSS, XO = VDD
20 ns
VDD
90%
50%
10%
tPHL
90%
50%
10%
Z
tTHL
VSS
tPLH
VOH
VOL
tTLH

MC14512B
6264
VDD
PULSE
GENERATOR
VDD
S3
S4
VSS
20 ns
VDD
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
20 ns
90%
50%
10%
DISABLE
INPUT
CL
S1
1k
VSS
tPZL
VOH
90%
tPLZ
S2
2.5 V @ VDD = 5 V,
10 V, AND 15 V
tPZH
2 V @ VDD = 5 V
VOH 6 V @ VDD = 10 V
10%
10 V @ VDD = 15 V
VOL
10%
OUTPUT
VOL
tPHZ
VSS
VDD
OUTPUT
90%
Switch Positions for 3State Test
VSS
Test
S1
S2
S3
S4
tPHZ
tPLZ
tPZL
tPZH
Open
Closed
Closed
Open
Closed
Open
Open
Closed
Closed
Open
Open
Closed
Open
Closed
Closed
Open
Figure 3. 3State AC Test Circuit and Waveform

LOGIC DIAGRAM
C
B
A
X0
X1
X2
13
12
15
11
1
DISABLE
10
INHIBIT
VDD
X4
IOD
MC14512B
IL
14
X3
DATA
BUS
SELECTED
DEVICE
LOAD
ITL
Z
MC14512B
5
ITL
X5
X6
X7
MC14512B
VSS
7
9
1
OUT
IN
2
TRANSMISSION
GATE
IN
OUT
2
3STATE MODE OF OPERATION

Output terminals of several MC14512B 8Bit Data Selectors can be connected to a single date bus as shown. One
MC14512B is selected by the 3state control, and the remaining devices are disabled into a highimpedance off
state. The number of 8bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, IOD, 3state or disable output leakage current, ITL,
and the load current, IL, required to drive the bus line (including fanout to other device inputs), and can be calculated by:
N=
IOD IL
+1
ITL
N must be calculated for both high and low logic state of the
bus line.
MC14512B
6265
MOTOROLA
MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver
L SUFFIX
CERAMIC
CASE 726
CMOS MSI (LowPower Complementary MOS)

The MC14513B BCDtoseven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4bit storage latch, an 8421 BCDtoseven
segment decoder, and has output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turnoff or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output
(RBO) can be used to suppress either leading or trailing zeroes. It can be
used with sevensegment light emitting diodes (LED), incandescent,
fluorescent, gas discharge, or liquid crystal readouts either directly or
indirectly.
P SUFFIX
PLASTIC
CASE 707
MC14XXXBCP
MC14XXXBCL
PIN ASSIGNMENT

Highcurrent Sourcing Outputs (Up to 25 mA)
Latch Storage of Binary Input
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Time Share (Multiplexing) Capability
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
Capable of Driving Two LowPower TTL Loads, One Lowpower
Schottky TTL Load to Two HTL Loads Over the Rated Temperature
Range.
18
VDD
17
LT
16
BI
15
LE
14
13
12
RBI
VSS
11
10
RBO

DC Supply Voltage
Symbol
Value
a
g
f
e
b
c
DISPLAY
Rating
Plastic
Ceramic
TRUTH TABLE
Unit
Inputs
RBI LE BI LT
Outputs
D C B A RBO a b c d e f g Display
VDD
0.5 to + 18
X X X X
1 1 1 1 1 1 1
Vin
0.5 to VDD + 0.5
X X X X
0 0 0 0 0 0 0
Blank
DC Current Drain per Input Pin
10
mA
1
0
0
0
1
1
1
1
0 0 0 0
0 0 0 0
1
0
0 0 0 0 0 0 0
1 1 1 1 1 1 0
Blank
0
TA
55 to + 125
PD
500
mW
Tstg
65 to + 150
_C
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
2
3
4
5
Maximum Continuous Output Drive Current

(Source) per Output
IOHmax
25
mA
Maximum Continuous Output Power

(Source) per Output
POHmax
50
mW
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
6
7
8
9
Blank
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
Blank
X X X X
POHmax = IOH (VDD VOH)

MC14513B
6266
X = Dont Care
RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
5.0
10
15
4.1
9.1
14.1
4.1
9.1
14.1
5.0
10
15
4.1
9.1
14.1
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
4.1
3.9
3.4
4.1
3.9
3.4
4.57
4.24
4.12
3.94
3.70
3.54
4.1
3.5
3.0
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10
9.1
9.0
8.6
9.1
9.0
8.6
9.58
9.26
9.17
9.04
8.90
8.75
9.1
8.6
8.2
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15
14.1
14
13.6
14.1
14
13.6
14.59
14.27
14.18
14.07
13.95
13.80
14.1
13.6
13.2
Vdc
Characteristic
Symbol
Output Voltage Segment Outputs

0 Level
Vin = VDD or 0
VOL
1 Level
VOH
Output Voltage RBO Output

0 Level
Vin = VDD or 0
VOL
1 Level
VOH
Vin = 0 or VDD
Vin = 0 or VDD
Input Voltage #
0 Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL

(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
VIH
Output Drive Voltage Segments

(IOH = 0 mA)
Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
VOH
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
(continued)
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS (Vin or
Vout) VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
MC14513B
6267
ELECTRICAL CHARACTERISTICS continued (Voltages Referenced to VSS)

Characteristic
Symbol
Output Drive Current RBO Output

(VOH = 2.5 V)
Source
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
5.0
10
15
0.40
0.21
0.81
0.32
0.17
0.66
0.64
0.34
1.30
0.22
0.12
0.46
5.0
10
15
0.18
0.47
1.80
0.15
0.38
1.50
0.29
0.75
2.90
0.10
0.26
1.0
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Unit
mAdc
Sink
IOL
Output Drive Current Segments

(VOL = 0.4 V)
Sink
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
mAdc
mAdc

Adc

Noise Margin for both 1 and 0 level =
1.0 Vdc min @ VDD = 5.0 Vdc
where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
Input LE and RBI low, and Inputs D, BI and LT high.

20 ns
20 ns
A, B, AND C
90%
50%
1
2f
VDD
10%
50% DUTY CYCLE

ANY OUTPUT
VSS
VOH
50%
VOL
MC14513B
6268

Characteristic
Output Rise Time Segment Outputs
Output Rise Time RBO Output
Symbol
Typ
Max
5.0
10
15
40
30
25
80
60
50
5.0
10
15
480
240
190
960
480
380
5.0
10
15
125
75
65
250
150
130
Output Fall Time RBO Outputs

tTHL = (3.25 ns/pF) CL + 107.5 ns
tTHL = (1.35 ns/pF) CL + 67.5 ns
tTHL = (0.95 ns/pF) CL + 62.5 ns
tTHL
5.0
10
15
270
135
110
540
270
220
Propagation Delay Time A, B, C, D Inputs*

tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH
5.0
10
15
640
250
175
1280
500
350
tPHL
5.0
10
15
720
290
200
1440
580
400
tPLH
5.0
10
15
600
200
150
750
300
220
5.0
10
15
485
200
160
970
400
320
5.0
10
15
313
125
90
625
250
180
Unit
ns
tTLH
tTHL
Propagation Delay Time RBI and BI Inputs*

tPLH = (1.05 ns/pF) CL + 547.5 ns
tPLH = (0.45 ns/pF) CL + 177.5 ns
tPLH = (0.30 ns/pF) CL + 135 ns
Min
tTLH
Output Fall Time Segment Outputs*

tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns

tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
All Types
VDD
Vdc
ns
ns
ns
ns
ns
ns
tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
Propagation Delay Time LT Input*

tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH

tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
313
125
90
625
250
180
ns
Setup Time
tsu
5.0
10
15
100
40
30
ns
Hold Time
th
5.0
10
15
60
40
30
ns
tWL(LE)
5.0
10
15
520
220
130
260
110
65
ns
Latch Enable Pulse Width
ns
ns
MC14513B
6269
20 ns
VDD
20 ns
90%
50%
10%
INPUT C
VSS
tPHL
tPLH
VOH
OUTPUT g
VOL
tTHL
tTLH
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
50%
10%
INPUT C
tPLH
VSS
tPHL
VOH
90%
OUTPUT RBO
50%
10%
tTLH
VOL
tTHL
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns
VDD
90%
50%
LE
10%
VSS
th
tsu
INPUT C
VDD
50%
VSS
VOH
OUTPUT g
VOL
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns
20 ns
90%
50%
LE
VDD
10%
VSS
tWL(LE)
d. Pulse Width: Data DCBA strobed into latches.

MC14513B
6270

VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
1.7 V
1.7 V
VSS
VSS
VDD
VDD
FLUORESCENT READOUT
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
(SUPPLY)
VSS
VSS
VDD
APPROPRIATE
VOLTAGE
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
LIQUID CRYSTAL (LC) READOUT

EXCITATION
(SQUARE WAVE,
VSS TO VDD)
VDD
1/4 OF MC14070B
VSS
** A filament prewarm resistor is recommended to reduce
filament thermal shock and increase the effective cold
resistance of the filament.
VSS
Direct dc drive of LCs not recommended for life of LC readouts.
MC14513B
6271
LOGIC DIAGRAM
BI 4
15 a
A 7
14 b
13 c
B 1
12 d
11 e
17 f
C 2
16 g
LT 30
10 RBO
RBI 8
D 6
LE 5
TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION
DISPLAYS
CONNECT TO
a g
RBI
VDD (1) D C
RBO
1
B A
a g
RBI
D C
MC14513B
6272
0
(0)
RBI
D C
MC14513B
MC14513B
INPUT
CODE
a g
RBO
0
(0)
a g
RBO
B
D C
MC14513B
0
0
(5)
a g
RBO
RBI
B
D C
MC14513B
1
0
(0)
a g
RBO
RBI
B
D C
MC14513B
0
0
(1)
RBO
RBI
B
MC14513B
0
(3)
TYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)

TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
a g
RBO
RBI
B A
D C
a g
0
RBO
D C
0
(5)
RBO
D C
MC14513B
MC14513B
0
a g
RBI
(0)
a g
RBI
B
RBO
D C
MC14513B
0
0
(1)
a g
RBI
B
D C
MC14513B
1
1
(3)
a g
RBI
RBO
B
D C
MC14513B
1
0
(0)
CONNECT TO
RBI
RBO
B
VDD (1)
MC14513B
0
0
(0)
0
INPUT CODE
MC14513B
6273
MOTOROLA
MC14514B
MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical 1 at the selected output, whereas the MC14515B (output
active low option) presents a logical 0 at the selected output. The latches
are RS type flipflops which hold the last input data presented prior to the
strobe transition from 1 to 0. These high and low options of a 4bit latch/4
to 16 line decoder are constructed with Nchannel and Pchannel
enhancement mode devices in a single monolithic structure. The latches are
RS type flipflops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E

MC14XXXBCP
MC14XXXBCL
MC14XXXBDW

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
500
mW
65 to + 150
_C
PD
Tstg
Storage Temperature
TL
260
_C
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
DATA 1
DATA 2
DATA 3
DATA 4
STROBE
INHIBIT
21
TRANSPARENT
C
LATCH
22
4 TO 16
DECODER
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
Plastic
Ceramic
SOIC
DECODE TRUTH TABLE (Strobe = 1)*

Selected Output
Data Inputs
Inhibit
MC14514 = Logic 1
MC14515 = Logic 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
All Outputs = 0, MC14514

All Outputs = 1, MC14515
X = Dont Care
*Strobe = 0, Data is latched
23
MC14514B MC14515B
6274

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
ITL
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

Adc
be left open.
MC14514B MC14515B
6275
All Types
Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
Propagation Delay Time; Data, Strobe to S

tPLH,
tPHL
Inhibit Propagation Delay Times

tPLH,
tPHL
Setup Time
Data to Strobe
tsu
Hold Time
Strobe to Data
th
Strobe Pulse Width
VDD
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
550
225
150
1100
450
300
5.0
10
15
400
150
100
800
300
200
5.0
10
15
250
100
75
125
50
38
5.0
10
15
20
0
10
100
40
30
5.0
10
15
350
100
75
175
50
38
Unit
ns
ns
ns
ns
ns
tWH
ns
ns
VDD
VDS
STROBE
INHIBIT
For MC14514B
1. For Pchannel: Inhibit = VSS
1. and D1D4 constitute
1. binary code for output
1. under test.
2. For Nchannel: Inhibit = VDD
D1
D2
D3
D4
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
For MC14515B
1. For Pchannel: Inhibit = VDD
2. For Nchannel: Inhibit = VSS
2. and D1D4 constitute binary
2. code for output under test.
ID
EXTERNAL
POWER SUPPLY
VSS
Figure 1. Drain Characteristics Test Circuit
MC14514B MC14515B
6276
VDD
ID
VDD
24
PULSE
GENERATOR
0.01 F
CERAMIC
500
F
D1
S0
D2
D3
D4
STROBE
INHIBIT S15
12
20 ns
20 ns
Vin
CL
VDD
90%
10%
VSS
CL
VSS
VDD
STROBE
OUTPUT S0
OUTPUT S1
S0
S1
INHIBIT
CL
20 ns
CL
INPUT
D1
PROGRAMMABLE
PULSE
GENERATOR
tTLH
10%
VDD
90%
50%
VSS
tPHL
VDD
tPLH
D2
90%
50%
10%
OUTPUT
D3
D4
tTHL
OUTPUT S15
S15
VSS
tTLH
VSS
tTHL
CL
PIN ASSIGNMENT
ST
24
VDD
D1
23
INH
D2
22
D4
S7
21
D3
S6
20
S10
S5
19
S11
S4
18
S8
S3
17
S9
S1
16
S14
S2
10
15
S15
S0
11
14
S12
VSS
12
13
S13
MC14514B MC14515B
6277
MC14514B MC14515B
6278
LOGIC DIAGRAM
AB CD
AB CD
AB CD
9 S1
10 S2
AB CD
DATA 1 2
S
8 S3
A
AB CD
DATA 2 3
S
AB CD
B
AB CD
AB CD
AB CD
DATA 3 21
S
C
AB CD
DATA 4 22
11 S0
AB CD
D
6 S5
5 S6
4 S7
18 S8
17 S9
20 S10
AB CD
19 S11
AB CD
R
7 S4
STROBE 1
14 S12
AB CD
13 S13
AB CD
16 S14
INHIBIT 23
AB CD
IN MC14515B ONLY
15 S15
COMPLEX DATA ROUTING

Two MC14512 eightchannel data selectors are used here
with the MC14514B fourbit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3state data bus to a
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be rerouted or
intermixed according to patterns determined by data select
and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
times faster then the shift frequency of the input registers, the
most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most
significant bits from all of the registers can be transferred to
the data bus before the next most significant bit is presented
for transfer by the input registers.
Information from the 3state bus is redistributed by the
MC14514B fourbit latch/decoder. Using the fourbit address, D1 thru D4, the information on the inhibit line can be
transferred to the addressed output line to the desired output
registers, A thru P. This distribution of data bits to the output
registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can
be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or
other methods of data slicing can be implemented.
DATA ROUTING SYSTEM
REGISTER 1
D0
D1
D2
D3
D4
D5
D6
DIS
3STATE
DATA BUS
DATA
DISTRIBUTION
OUTPUT
REGISTERS
D7
A0 A1 A2
D1 D2 D3 D4
S0
STROBE
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
INHIBIT
S14
S15
REGISTER A
MC14514B
REGISTER 8
DATA
TRANSFER
MC14512
INPUT
REGISTERS
DATA
SELECT
A0 A1 A2
D0
Q
D1
D2
D3
D4
D5
D6
D7
DIS
MC14512
REGISTER 9
REGISTER 16
REGISTER P
MC14514B MC14515B
6279
MOTOROLA

MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is constructed with
MOS Pchannel and Nchannel enhancement mode devices in a monolithic
structure.
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the
reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analogto
digital and digitaltoanalog conversions, and (3) Magnitude and sign
generation.

of Clock
Single Pin Reset
Schottky Load Over the Rated Temperature Range

Symbol
VDD
Parameter
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
BLOCK DIAGRAM
1
PE
CARRY IN
RESET
10
UP/DOWN
0.5 to + 18.0
15
CLOCK
Vin, Vout
0.5 to VDD + 0.5
P0
Iin, Iout

per Pin
10
mA
12
P1
13
P2
PD
500
mW
P3
Tstg
Storage Temperature
65 to + 150
_C
TL
260
_C
TRUTH TABLE
Carry In
Up/Down
Preset
Enable
Reset
Clock
Action
No Count
Count Up
Count Down
Preset
Reset
Plastic
Ceramic
SOIC
Unit
Value
DC Supply Voltage
L SUFFIX
CERAMIC
CASE 620
Q0
Q1
11
Q2
14
Q3
CARRY
OUT
VDD = PIN 16
VSS = PIN 8

to the range VSS
(Vin or Vout)
VDD.
X = Dont Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
MC14516B
6280

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
PE
16
VDD
Q3
15
P3
14
Q2
P0
13
P2
CARRY IN
12
P1
Q0
11
Q1
CARRY OUT
10
U/D
VSS
MC14516B
6281
All Types
Characteristic
Symbol

tTLH,
tTHL

Clock to Q
tPLH,
tPHL
Clock to Carry Out

tPLH,
tPHL

tPLH,
tPHL
Preset or Reset to Q
tPLH,
tPHL
Preset or Reset to Carry Out

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
315
130
100
630
260
200
5.0
10
15
315
130
100
630
260
200
5.0
10
15
180
80
60
360
160
120
5.0
10
15
315
130
100
630
360
200
5.0
10
15
550
225
150
1100
450
300
ns
ns
ns
ns
Reset Pulse Width
tw
5.0
10
15
380
200
160
190
100
80
ns
Clock Pulse Width
tWH
5.0
10
15
350
170
140
200
100
75
ns
fcl
5.0
10
15
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time

The Preset or Reset signal must be low prior to a
positivegoing transition of the clock.
trem
5.0
10
15
650
230
180
325
115
90
ns
tTLH,
tTHL
5.0
10
15
15
5
4
Setup Time
Carry In to Clock
tsu
5.0
10
15
260
120
100
130
60
50
ns
Hold Time
Clock to Carry In
th
5.0
10
15
0
20
20
60
20
0
ns
Setup Time
Up/Down to Clock
tsu
5.0
10
15
500
200
150
250
100
75
ns
Hold Time
Clock to Up/Down
th
5.0
10
15
70
10
0
160
60
40
ns
Setup Time
Pn to PE
tsu
5.0
10
15
40
30
25
120
70
50
ns
Hold Time
PE to Pn
th
5.0
10
15
480
420
420
240
210
210
ns
tWH
5.0
10
15
200
100
80
100
50
40
ns
#Data labelled Typ is not to be used for design purposes but is intended as an Indication of the ICs potential performance.
MC14516B
6282
VDD
500 pF
0.01 F
CERAMIC
ID
Q0
PE
CARRY IN
Q1
R
UP/DOWN
PULSE
GENERATOR
20 ns
20 ns
CL
50%
CLOCK
Q2
CLOCK
Q3
P3
CARRY
OUT
10%
VARIABLE
WIDTH
CL
P0
P1
P2
VDD
90%
VSS
CL
CL
CL

LOGIC DIAGRAM
P0
4
RESET
PRESET
ENABLE
CLOCK 15
PE
C
CARRY OUT
CARRY IN
Q0
6
P1 Q1
12 11
PE
P2
13
PE
C
Q
Q2
14
C
Q
P3
3
PE
Q3
2
C
Q
UP/DOWN 10
TOGGLE FLIPFLOP
PARALLEL IN
PE
C
T
FLIPFLOP FUNCTIONAL TRUTH TABLE

Preset
Enable
Clock
Qn+1
Parallel In
Qn
Qn
Qn
X = Dont Care
MC14516B
6283
tsu
trem
th
CARRY IN OR
UP/DOWN
1
fcl
VDD
50%
VSS
VDD
50%
CLOCK
VSS
VDD
tw(H)
tw(H)
PRESET ENABLE
VSS
tTLH
CARRY OUT ONLY
Q0 OR CARRY OUT
VOH
90%
10%
90%
10%
VOL
tPHL
tTHL
tPLH
tPLH
trem
VDD
50%
RESET
VSS
tw
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) This activelow input is used when
Cascading stages. Carry In is usually connected to Carry
Out of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) Binary data is incremented or decremented, depending on the direction of count, on the positive
transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2)
Binary data is present on these outputs with Q0 corresponding to the least significant bit.
Carry Out, (Pin 7) Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
MC14516B
6284
synchronous output is active low and may also be used to

indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) Asynchronously resets the Q out
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) Controls the direction of count, high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) This pin is
connected to a positive supply voltage ranging from 3.0 volts
to 18.0 volts.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
CLOCK
PRESET
ENABLE
0 = COUNT
1 = PRESET
Cin
CLOCK
1 = UP
0 = DOWN
CLOCK
+VDD
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
Cout
M.S.D.
MC14516B
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
TERMINAL COUNT
INDICATOR
+VDD
RESISTORS = 10 kW
RESET
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8Bit Up/Down Counter
MC14516B
6285
MC14516B
6286
CLOCK
UP/DOWN
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8BIT UP/DOWN COUNTER
CARRY IN
(MSD)
PE
P7
P6
P5
P4
P3
P2
P1
P0
CARRY OUT
(MSD)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CARRY OUT
(LSD)
RESET
COUNT
13
14
15
16
17
18
19
18
17
16
15
13
251
252
253 254 255
PRESET
ENABLE
PRESET ENABLE
UP COUNT
14
DOWN COUNT
RESET
UP COUNT
DOWN
COUNT
UP COUNT
fout
BUFFER
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
PE
Q1
Q2
Q3
Q0
PE
Q1
Q2
Q3
Cout
Cin
CLOCK
Cin
CLOCK
CLOCK (fin)
+VDD
L.S.D.
MC14516B
U/D
R
P0
P1
P2
P0
P1
P2
+VDD
THUMBWHEEL SWITCHES
(OPEN FOR 0)
Cout
M.S.D.
MC14516B
P3
U/D
R
P0
P1
P2
P3
P3
P4
P5
P6
P7
+VDD
RESISTORS = 10 kW
f
fout = in
n
RESET
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
MC14516B
6287
MOTOROLA
MC14517B
Dual 64-Bit Static Shift Register
The MC14517B dual 64bit static shift register consists of two identical,
independent, 64bit registers. Each register has separate clock and write
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16bit,
32bit, and 48bit taps may be entered into the device by application of a
clock pulse. This feature permits the register to be loaded with 64 bits in 16
clock periods, and also permits bus logic to be used. This device is useful in
time delay circuits, temporary memory storage circuits, and other serial shift
register applications.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648

Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the Clock
Input
3State Output at 64thBit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MAXIMUM RATINGS (Voltages referenced to VSS)

Symbol
VDD
Parameter
DC Supply Voltage
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Value
Unit
0.5 to + 18.0
Q16A
16
VDD
Vin, Vout
0.5 to VDD + 0.5
Q48A
15
Q16B
Iin, Iout

per Pin
10
mA
WEA
14
Q48B
CA
13
WEB
PD
500
mW
12
CB
Storage Temperature
65 to + 150
_C
Q64A
Tstg
11
_C
Q32A
Q64B
260
DA
10
Q32B
VSS
TL
DB
FUNCTIONAL TRUTH TABLE (X = Dont Care)

Clock
Write
Enable
Data
16Bit Tap
32Bit Tap
48Bit Tap
64Bit Tap
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
Data entered
into 1st Bit
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
Data entered
into 1st Bit
Data at tap
entered into 17Bit
Data at tap
entered into 33Bit
Data at tap
entered into 49Bit
High Impedance
Content of 16Bit
Displayed
Content of 32Bit
Displayed
Content of 48Bit
Displayed
Content of 64Bit
Displayed
High Impedance
High Impedance
High Impedance
High Impedance
MC14517B
6288

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
be left open.
MC14517B
6289

Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
475
210
140
770
300
215
tWH
5.0
10
15
330
125
100
170
75
60
ns
fcl
5.0
10
15
3.0
6.7
8.3
1.5
4.0
5.3
MHz
tTLH, tTHL
5.0
10
15

tTLH, tTHL

tPLH, tPHL
Clock Pulse Width
Unit
ns
ns
**See Note
Data to Clock Setup Time
tsu
5.0
10
15
0
10
15
40
15
0
ns
Data to Clock Hold Time
th
5.0
10
15
150
75
35
75
25
10
ns
Write Enable to Clock Setup Time
tsu
5.0
10
15
400
200
110
170
65
50
ns
Write Enable to Clock Release Time
trel
5.0
10
15
380
180
100
160
55
40
ns
** When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
VDD
REPETITIVE WAVEFORM
CL
WE
CL
VSS
D
C
VDD
D
(f = 1/2 fo)
CL
Q16 Q32 Q48 Q64
D
C
VDD
fo
CL
VSS
WE
Q16 Q32 Q48 Q64
VSS
50 F
ID
CL
CL
CL
CL
MC14517B
6290
Vout = VOH
Vout = VOL
VDD = VGS
D
C
VDD = VGS
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64
D
C
WE
WE
D
C
D
C
IOH
WE
IOL
WE
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64

EXTERNAL
POWER
SUPPLY
VSS
EXTERNAL
POWER
SUPPLY
VSS
(Output being tested should be in the lowlogic state)
(Output being tested should be in the highlogic state)
Figure 2. Typical Output Source Current

Figure 3. Typical Output Sink Current

tWH
PIN NOS
tWL
16
17
18
90%
19
10%
CLOCK 4 (12)
tsu
trel
WRITE 3 (13)
th1
th1
16BIT OUTPUT 1 (15)

17BIT INPUT
tsu1
32BIT OUTPUT 6 (10)
33BIT INPUT
tsu1
48BIT OUTPUT 2 (14)
49BIT INPUT
VSS
20 ns
th1
10%
tPHL
tsu0
th0
th1
VDD
90%
50%
tsu1
tPLH
90%
VDD
tsu0
th0
20 ns
tsu0
th0
20 ns
VDD
50%
VSS
VDD
th0
tsu0
tsu1
DATA IN 7 (9)
33
tPHL
VDD
tTLH
tPLH
tPHL
VDD
90%
tTLH
tPLH
VSS
VOH
VDD
10%
V
tTHL OL
VOH
50%
10%
VOL
tTHL
VOH
VSS
tTLH
tPLH
tPHL
20 ns
50%
VDD
VSS
VDD
VSS
VDD
V
tTHL OL
64BIT OUTPUT 5 (11)

tTLH
VSS
tTHL
Figure 4. AC Test Waveforms

EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)
CLOCK
DATA
WRITE
ENABLE
D
C
D
C
D
Q
C 16
3STATE
WRITE ENABLE = 0, 16BIT OUTPUT

WRITE ENABLE = 1, 17BIT INPUT
D
Q
C 17
WE
D
Q
C 32
3STATE
32BIT OUTPUT
33BIT INPUT
D
Q
C 33
WE
D
Q
C 48
3STATE
48BIT OUTPUT
49BIT INPUT
D
Q
C 49
WE
D
C 64 Q
3STATE
64BIT OUTPUT
HIGH IMPEDANCE
MC14517B
6291
MOTOROLA
MC14518B
MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary counter
are constructed with MOS Pchannel and Nchannel enhancement mode
devices in a single monolithic structure. Each consists of two identical,
independent, internally synchronous 4stage counters. The counter stages
are type D flipflops, with interchangeable Clock and Enable lines for
incrementing on either the positivegoing or negativegoing transition as
required when cascading multiple stages. Each counter can be cleared by
applying a high level on the Reset line. In addition, the MC14518B will count
out of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multistage synchronous or ripple
counting applications requiring low power dissipation and/or high noise
immunity.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G

Internally Synchronous for High Internal and External Speeds
Logic EdgeClocked Design Incremented on Positive Transition of
Clock or Negative Transition on Enable

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
TRUTH TABLE
Clock
Enable
Reset
Action
Increment Counter
Increment Counter
No Change
No Change
No Change
No Change
Q0 thru Q3 = 0
0
X
X
0
1
X
X = Dont Care
MC14518B MC14520B
6292
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
CLOCK
1
Q0
Q1
Q2
2
ENABLE
3
4
Q3
5
6
Q0
11
Q1
Q2
Q3
12
7
CLOCK
9
C
10
ENABLE
13
14
15
VDD = PIN 16
VSS = PIN 8

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
CA
16
VDD
EA
15
RB
Q0A
14
Q3B
Q1A
13
Q2B
Q2A
12
Q1B
Q3A
11
Q0B
RA
10
EB
VSS
CB
MC14518B MC14520B
6293
All Types
Characteristic
Symbol

tTLH,
tTHL

Clock to Q/Enable to Q
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
280
115
80
560
230
160
5.0
10
15
330
130
90
650
230
170
tw(H)
tw(L)
5.0
10
15
200
100
70
100
50
35
ns
fcl
5.0
10
15
2.5
6.0
8.0
1.5
3.0
4.0
MHz
tTHL, tTLH
5.0
10
15
15
5
4
Enable Pulse Width
tWH(E)
5.0
10
15
440
200
140
220
100
70
ns
Reset Pulse Width
tWH(R)
5.0
10
15
280
120
90
125
55
40
ns
trem
5.0
10
15
5
15
20
45
15
5
ns
Reset to Q
tPHL = (0.66 ns/pF) CL + 117 ns
tPHL
Clock Pulse Width
Clock or Enable Rise and Fall Time
Reset Removal Time
ns
VDD
500 F
PULSE
GENERATOR
ID
0.01 F
CERAMIC
C Q0
Q1
Q2
E Q3
R
CL
CL
CL
CL
VSS
20 ns
20 ns
50%
90%
VARIABLE
WIDTH
10%
VSS
MC14518B MC14520B
6294
20 ns
VDD
PULSE
GENERATOR
20 ns
90%
50%
10%
CLOCK
INPUT
Q0
tWH
Q1
E
R
Q2
Q3
CL
VSS
CL
CL
VSS
tWL
tPHL
tPLH
CL
VDD
90%
50%
10%
Q
tr
tf
2 3
4 5
7 8
9 10 11 12 13 14 15 16 17 18
2 3
4 5
7 8
9 0 1
7 8
9 0
2 3
4 5
7 8
9 10 11 12 13 14 15 0
1 2
CLOCK
ENABLE
RESET
2 3
4 5
Q0
MC14518B
Q1
Q2
Q3
4
Q0
MC14520B
Q1
Q2
Q3
MC14518B MC14520B
6295
Q0
D
C
Q1
Q2
Q3
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram

Q0
D
C
Q1
Q2
Q3
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram

MC14518B MC14520B
6296
MOTOROLA
MC14519B
4-Bit AND/OR Selector or
Quad 2-Channel Data Selector
or Quad Exclusive NOR" Gate
L SUFFIX
CERAMIC
CASE 620
The MC14519B is constructed with MOS Pchannel and Nchannel

enhancement mode devices in a monolithic structure. These complementary
MOS logic gates find primary use where low power dissipation and/or high
noise immunity is desired.
This device provides three functions in one package; a 4Bit AND/OR
Selector, a Quad 2Channel Data Selector, or a Quad Exclusive NOR Gate.
Plugin Replacement for CD4019 in Most Applications
LOGIC DIAGRAM
CONTROL
INPUTS
DATA
INPUTS
14
X0
Y0
X1
Y1
X2
Y2
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TRUTH TABLE
10 Z0
11 Z1
12 Z2
X3 15
Y3
P SUFFIX
PLASTIC
CASE 648
Control Inputs
A
0
0
1
1
0
1
0
1
Output
Zn
0
Yn
Xn
xn
Yn
NOTE: Xn
Yn means Xn
(ExclusiveNOR) Yn
13 Z3
1
VDD = PIN 16
VSS = PIN 8
MC14519B
6297

Symbol
VDD
Parameter
DC Supply Voltage
PIN ASSIGNMENT
Value
Unit
0.5 to + 18.0
Y3
16
VDD
Vin, Vout
0.5 to VDD + 0.5
X2
15
X3
Iin, Iout

per Pin
10
mA
Y2
14
X1
13
Z3
PD
500
mW
Y1
12
Z2
Tstg
Storage Temperature
65 to + 150
_C
X0
11
Z1
260
_C
Y0
10
Z0
VSS
TL

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14519B
6298

Characteristic
Symbol

tTLH,
tTHL

tPLH, tPHL = (0.66 ns/pF) CL + 82
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
250
115
90
500
225
165
Unit
ns
ns
+VDD
VDD
PULSE
GENERATOR
Vin
Z0
CL
20 ns
X0
20 ns
Z1
Y0
CL
X1
Vin
Y1
X2
VDD
90%
10%
Z2
VSS
50% DUTY CYCLE

CL
Y2
X3
Y3
VSS
Z3
CL
ISS
500 F
VDD
20 ns
PULSE
GENERATOR
V
A DD Z0
B
X0
Z1
Y0
X1
Y1
Z2
X2
Y2
X3
Y3 V Z3
SS
INPUT
CL
20 ns
VDD
90%
50%
10%
VSS
tPHL
CL
OUTPUTS
OUTPUT
CL
tPLH
tTHL
tPLH
CL
VOH
90%
50%
10%
OUTPUT
VOL
tTLH
tPHL
VOH
50%
VOL
MC14519B
6299
TYPICAL CIRCUIT APPLICATIONS

DATA REGISTER SELECTION COMPARISON
DATA A
CLOCK A
RESET A
MC14015B
DUAL 4BIT REGISTER
4BIT REGISTER A
Q1
Q2 Q3 Q4
CONTROL A
CONTROL B
Q1
X0
X1
Z0
X2
X3
Y0 Y1 Y2
MC14519B
AND/OR SELECT/EXCL NOR
Z1
Z2
DATA B
CLOCK B
RESET B
4BIT REGISTER B
Q2 Q3 Q4
Y3
Z3
INVERT
MC14070B
QUAD
EXCLUSIVE OR
Q0
Q1
Q2
Q3
CONVERSION TABLE
Operation Code
Output
Function
INV
Q0
Q1
Q2
Q3
0
0
1
1
0
0
0
0
0
1
0
1
0
1
X0
X0
0
1
X1
X1
0
1
X2
X2
0
1
X3
X3
Inhibit, all zeros

Inhibit, all ones
Control A
Control A and Invert
0
0
1
1
1
1
1
1
0
1
0
1
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Control B
Control B and Invert
Exclusive NOR
Exclusive OR
X0
X0
Y0
Y0
X1
X1
Y1
Y1
X2
X2
Y2
Y2
X3
X3
Y3
Y3
be left open.
MC14519B
6300
MOTOROLA
MC14521B
24-Stage Frequency Divider
L SUFFIX
CERAMIC
CASE 620
The MC14521B consists of a chain of 24 flipflops with an input circuit that

allows three modes of operation. The input will function as a crystal
oscillator, an RC oscillator, or as an input buffer for an external oscillator.
Each flipflop divides the frequency of the previous flipflop by two,
consequently this part will count up to 224 = 16,777,216. The count advances
on the negative going edge of the clock. The outputs of the last
sevenstages are available for added flexibility.
P SUFFIX
PLASTIC
CASE 648
All Stages are Resettable

Reset Disables the RC Oscillator for Low Standby Power Drain
RC and Crystal Oscillator Outputs Are Capable of Driving External
Loads
Test Mode to Reduce Test Time
VDD and VSS Pins Brought Out on Crystal Oscillator Inverter to Allow
the Connection of External Resistors for LowPower Operation
Schottky TTL Load over the Rated Temperature Range.
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Vin, Vout
Iin, Iout
PD
Tstg
Parameter
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA
500
mW
65 to + 150
_C
DC Supply Voltage
Storage Temperature
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
TL
260
_C
Q24
16
VDD
RESET
15
Q23
VSS
14
Q22
OUT 2
13
Q21
VDD
12
Q20
IN 2
11
Q19
OUT 1
10
Q18
VSS
IN 1
BLOCK DIAGRAM
RESET
2
Output
9
IN 1
STAGES
1 THRU 17
6
IN 2
7
OUT 1
5
VDD
4
3 OUT2
VSS
STAGES
18 THRU 24
Q18 Q19 Q20 Q21 Q22 Q23 Q24
VDD = PIN 16
VSS = PIN 8
10
11
12
13
14
15
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Count Capacity
218 = 262,144
219 = 524,288
220 = 1,048,576
221 = 2,097,152
222 = 4,194,304
223 = 8,388,608
224 = 16,777,216
MC14521B
6301

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Source
Pins 4 & 7
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
(VOH = 2.5 Vdc)

Source
(VOH = 4.6 Vdc)
Pins 1, 10,
(VOH = 9.5 Vdc) 11, 12, 13, 14
(VOH = 13.5 Vdc)
and 15
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14521B
6302
Symbol
Characteristic
Output Rise and Fall Time (Counter Outputs)

tTLH, tTHL

Clock to Q18
tPHL, tPLH
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
Clock to Q24
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns
tPHL = (0.66 ns/pF) CL + 467 ns
VDD
Vdc
5.0
10
15
4.5
1.7
1.3
9.0
3.5
2.7
5.0
10
15
6.0
2.2
1.7
12
4.5
3.5
tPHL
Clock Pulse Width
5.0
10
15
1300
500
375
2600
1000
750
tWH(cl)
5.0
10
15
385
150
120
140
55
40
ns
fcl
5.0
10
15
3.5
9.0
12
2.0
5.0
6.5
MHz
tTLH, tTHL
5.0
10
15
15
5.0
4.0
tWH(R)
5.0
10
15
1400
600
450
700
300
225
ns
trem
5.0
10
15
30
0
40
200
160
110
ns
Reset Pulse Width
Reset Removal Time
ns
VDD
500 F
0.01 F
CERAMIC
ID
VDD
PULSE
GENERATOR
IN 2
VDD
Q18
Q19
Q20
Q21
Q22
Q23
Q24
VSS
VSS
CL
CL
Vin
CL
CL
20 ns
90%
50%
10%
20 ns
VDD
0V
50% DUTY CYCLE
CL
CL
CL
MC14521B
6303
VDD
VDD
VDD
PULSE
GENERATOR
IN 2
R
VSS
20 ns
IN 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
20 ns
CL
CL
tWL
CL
CL
CL
VSS
Qn
90%
50%
10%
CL
20 ns
tWH
90%
50%
10%
tPLH
tTLH
CL
tPHL
tTHL
500 kHz
Circuit
50 kHz
Circuit
Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
50
6.2
kHz
k
External Resistor/Capacitor Values

Ro
CT
CS
47
82
20
750
82
20
k
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
4.0
+ 100
2.0
+ 120
ppm
ppm
2.0
160
2.0
560
ppm
ppm
Characteristic
VDD
Ro
18 M
CS
CT
VDD
R*
VDD
IN 1 OUT 1
OUT 2
Q18
Q19
IN 2
Q20
Q21
Q22
Q23
R
Q24
VSS
VSS
R*
* Optional for low power operation,

10 k R 70 k.
Figure 3. Crystal Oscillator Circuit
MC14521B
6304
Frequency Stability
of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
of Temperature (VDD = 10 V)
TA Change from 55_C to + 25_C
MC14521 only
Complete Oscillator*
TA Change from + 25_C to + 125_C
MC14521 only
Complete Oscillator*
*Complete oscillator includes crystal, capacitors, and resistors.
Figure 4. Typical Data for Crystal Oscillator Circuit
100
8.0
VDD = 15 V
4.0
TEST CIRCUIT
FIGURE 7
0
10 V
4.0
8.0
5.0 V
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
10
5.0
2.0
1.0
TEST CIRCUIT
FIGURE 7
VDD = 10 V
50
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.5
0.2
12
RTC = 56 k,
C = 1000 pF
16
55
0.1
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
1.0 k
25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (C), DEVICE ONLY
125
0.0001
RS
RTC
10 k
100 k
0.001
0.01
C, CAPACITANCE (F)
1.0 m
0.1

VDD
VDD
C
VDD
VDD
VDD
IN 1
IN 1
IN 2
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
VSS
Q18
Q19
Q20
Q21
IN 2
Q22
Q23
Q24
OUT 1
R
OUT 2
PULSE
GENERATOR
VSS
VSS
VSS
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
FUNCTIONAL TEST SEQUENCE

Inputs
A test function (see Figure 8) has been

included for the reduction of test time required to
exercise all 24 counter stages. This test function
divides the counter into three 8stage sections,
and 255 counts are loaded in each of the
8stage sections in parallel. All flipflops are
now at a logic
g 1. The counter is now returned
to the normal 24stages in series configuration.
One more pulse is entered into Input 2 (In 2)
which will cause the counter to ripple from an all
1 state to an all 0 state.
Outputs
Comments
Reset
In 2
Out 2
VSS
VDD
Q18 thru Q24
VDD
Gnd
First 0 to 1 transition
on In 2, Out 2 node.
0
1
0
1
255 0 to 1 transitions
are clocked into this In 2,
Out 2 node.
0
0
0
0
1
0
Counter is in three 8stage

sections in parallel mode
Counter is reset.
reset In 2 and
Out 2 are connected
together
The 255th 0 to 1
transition.
1
1
Gnd
Counter converted back to

24stages in series mode.
Out 2 converts back to an

output.
VDD
Counter ripples from an all

1 state to an all 0 stage.
MC14521B
6305
LOGIC DIAGRAM
VDD
5
RESET
2
IN 1
3
VSS
9
17
18
19
10
Q18
MC14521B
6306
4
OUT 2
6
IN 2
7
OUT 1
STAGES
3 THRU 7
20
11
Q19
21
12
Q20
22
13
Q21
10
23
14
Q22
STAGES
11 THRU 15
16
24
15
Q23
1
Q24
VDD = PIN 16
VSS = PIN 8
MOTOROLA
Presettable 4-Bit Down Counters
MC14522B
MC14526B
The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters
with a decoded 0 state output for dividebyN applications. In single stage
applications the 0 output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade dividebyN operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
These complementary MOS counters can be used in frequency synthesizers, phaselocked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity.
Logic EdgeClocked Design Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Q3
16
VDD
Tstg
Storage Temperature
65 to + 150
_C
P3
15
Q2
260
_C
TL
FUNCTION TABLE
Inputs
Output
Clock
Reset
Inhibit
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous
reset*
y
Asynchronous reset
A
Asynchronous
h
reset
Asynchronous preset
L
L
L
L
X
X
L
L
Decrement inhibited
Decrement inhibited
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change**
g
(inactive
(
edge)
g )
No change** (inactive edge)
D
Decrement**
**
Decrement**
PE
14
P2
INHIBIT
13
CF
P0
12
CLOCK
11
P1
Q0
10
RESET
VSS
Q1
Resulting
Function
Preset
Enable
Cascade
Feedback
PIN ASSIGNMENT

to the range VSS
(Vin or Vout)
VDD.
X = Dont Care
NOTES:
* Output 0 is low when reset goes high only it PE and CF are low.
** Output 0 is high when reset is low, only if CF is high and count is 0000.
MC14522B MC14526B
6307

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14522B MC14526B
6308

Characteristic

Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
Symbol
tTLH,
tTHL
(Figures 4, 5)
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
ns
tPLH,
tPHL
(Figures 4, 5, 6)
Clock or Inhibit to 0
Unit
ns
5.0
10
15
550
225
160
1100
450
320
5.0
10
15
240
130
100
480
260
200

Pn to Q
tPLH,
tPHL
(Figures 4, 7)
5.0
10
15
260
120
100
520
240
200
ns

Reset to Q
tPHL
250
110
80
500
220
160
ns
(Figure 8)
5.0
10
15
tPHL,
tPLH
(Figures 4, 9)
5.0
10
15
220
100
80
440
200
160
ns
tw
5.0
10
15
250
100
80
125
50
40
ns
2.0
5.0
6.6
1.5
3.0
4.0
MHz
(Figures 4, 5, 6)
5.0
10
15
tr,
tf
(Figures 5, 6)
5.0
10
15
15
5
4
tsu
5.0
10
15
90
50
40
40
15
10
ns
5.0
10
15
30
30
30
15
5
0
ns
5.0
10
15
250
100
80
125
50
40
ns
5.0
10
15
350
250
200
175
125
100
ns
5.0
10
15
10
20
30
110
30
20
ns

Preset Enable to 0
Clock or Inhibit Pulse Width
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
Clock or Inhibit Rise and Fall Time
Setup Time
Pn to Preset Enable
fmax
(Figure 10)
Hold Time
Preset Enable to Pn
th
(Figure 10)
tw
(Figure 10)
Reset Pulse Width
tw
(Figure 8)
Reset Removal Time
trem
(Figure 8)
MC14522B MC14526B
6309
VOL
VOH
VDD = VGS
VDD = VGS
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
IOH
Q3
0
EXTERNAL
POWER
SUPPLY
VSS

CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
IOL
Q3
0
EXTERNAL
POWER
SUPPLY
VSS

VDD
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
CL
Q3
CL
CL
VSS CL
PULSE
GENERATOR
20 ns
CLOCK
20 ns
VDD
90%
50%
10%
VSS
VARIABLE
50%
DUTY
CYCLE
WIDTH
Figure 3. Power Dissipation
MC14522B MC14526B
6310
TEST POINT
CL
Q or 0
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance.
Figure 4. Test Circuit
SWITCHING WAVEFORMS
tr
CLOCK
tf
tf
VDD
90%
50%
10%
tr
VDD
90%
50%
10%
INHIBIT
VSS
VSS
tw
tw
1/fmax
tPLH
ANY Q
OR 0
1/fmax
tPHL
tPLH
90%
50%
10%
ANY Q
OR 0
tTLH
tPHL
90%
50%
10%
tTHL
tTLH
Figure 5.
tTHL
Figure 6.
tw
VDD
RESET
50%
VSS
tr
ANY P
tf
tPHL
VDD
90%
50%
10%
VSS
tPLH
ANY Q
50%
tPHL
trem
ANY Q
50%
VDD
CLOCK
50%
VSS
Figure 7.
Figure 8.
VALID
tr
PRESET
ENABLE
tf
VDD
VDD
90%
50%
10%
ANY P
50%
VSS
GND
tPHL
VDD
PRESET
ENABLE
0
th
tsu
tPLH
50%
50%
VSS
tw
Figure 9.
Figure 10.
MC14522B MC14526B
6311
PIN DESCRIPTIONS
Preset Enable (Pin 3) If Reset is low, a high level on
the Preset Enable input asynchronously loads the counter
with the programmed values on P0, P1, P2, and P3.
other than all zeroes, the 0 output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high).
See the Function Table.
Inhibit (Pin 4) A high level on the Inhibit input pre

vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge
clock input.
Cascade Feedback (Pin 13) If the Cascade Feedback

input is high, a high level is generated at the 0 output when
the count is all zeroes. If Cascade Feedback is low, the 0
output depends on the Preset Enable input level. See the
Function Table.
Clock (Pin 6) The counter decrements by one for each

rising edge of Clock. See the Function Table for level requirements on the other inputs.
Reset (Pin 10) A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the 0 output to go high.
0 (Pin 12) The 0 (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
P0, P1, P2, P3 (Pins 5, 11, 14, 2) These are the preset
data inputs. P0 is the LSB.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) These are the synchronous counter outputs. Q0 is the LSB.
VSS (Pin 8) The most negative power supply potential.
This pin is usually ground.
VDD (Pin 16) The most positive power supply potential.
VDD may range from 3 to 18 V with respect to VSS.
STATE DIAGRAMS
MC14522B
0
15
15
14
14
13
13
12
12
11
MC14526B
10
MC14522B MC14526B
6312
11
10
MC14522B LOGIC DIAGRAM (BCD Down Counter)

P0
Q0
P1
7
Q1
11
P2
9
Q2
14
P3
15
Q3
2
D R
D RQ
D RQ
D RQ
T PE Q
T PE Q
T PE Q
T PE Q
VSS
CF
PE
INHIBIT
13
3
4
12
CLOCK
RESET
10
MC14526B LOGIC DIAGRAM (Binary Down Counter)

P0
Q0
P1
7
D R
C
T PE
P2
9
Q2
14
P3
15
Q3
2
D RQ
D RQ
D RQ
T PE Q
T PE Q
T PE Q
VDD
CF
Q1
11
VDD
13
PE
INHIBIT
4
12
CLOCK
RESET
10
MC14522B MC14526B
6313
DivideByN, Single Stage
The Inhibit pin may be used to stop pulse counting. When

this pin is taken high, decrementing is inhibited.
Figure 11 shows a single stage dividebyN application.

The MC14522B (BCD version) can accept a number greater
than 9 and count down in binary fashion. Hence, the BCD
and binary single stage dividebyN counters (as shown in
Figure 11) function the same.
To initialize counting a number, N is set on the parallel inputs (P0, P1, P2, and P3) and reset is taken high asynchronously. A zero is forced into the master and slave of each bit
and, at the same time, the 0 output goes high. Because
Preset Enable is tied to the 0 output, preset is enabled. Reset must be released while the Clock is high so the slaves of
each bit may receive N before the Clock goes low. When the
Clock goes low and Reset is low, the 0 output goes low (if
P0 through P3 are unequal to zero).
The counter downcounts with each rising edge of the
Clock. When the counter reaches the zero state, an output
pulse occurs on 0 which presets N. The propagation delays
from the Clocks rising and falling edges to the 0 outputs
rising and falling edges are about equal, making the 0 output pulse approximately equal to that of the Clock pulse.
Cascaded, Presettable DivideByN
N
VDD
fin
VSS
P0
P1
P2
P3
CF
RESET
INHIBIT
Figure 12 shows a three stage cascade application. Taking

Reset high loads N. Only the first stages Reset pin (least significant counter) must be taken high to cause the preset for
all stages, but all pins could be tied together, as shown.
When the first stages Reset pin goes high, the 0 output is
latched in a high state. Reset must be released while Clock is
high and time allowed for Preset Enable to load N into all
stages before Clock goes low.
When Preset Enable is high and Clock is low, time must be
allowed for the zero digits to propagate a Cascade Feedback
to the first nonzero stage. Worst case is from the most significant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to
one (i.e. N = 1).
After N is loaded, each stage counts down to zero with
each rising edge of Clock. When any stage reaches zero and
the leading stages (more significant bits) are zero, the 0
output goes high and feeds back to the preceding stage.
When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.
Q0
Q1
Q2
Q3
BUFFER
fin
CLOCK
PE
Figure 11. N Counter
LSB
N0 N1 N2 N3
P0 P1 P2 P3
fin
VSS
VDD
P0 P1 P2 P3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
P0 P1 P2 P3
CLOCK
CLOCK
CLOCK
INHIBIT
RESET
LOAD
N
MSB
N8 N9 N10 N11
N4 N5 N6 N7
CF
0
PE
VSS
INHIBIT
RESET
CF
0
PE
VSS
INHIBIT
RESET
Q0 Q1 Q2 Q3
VDD
CF
0
PE
BUFFER
10 K
fin
VSS
Figure 12. 3 Stages Cascaded
MC14522B MC14526B
6314
MOTOROLA
MC14527B
BCD Rate Multiplier

The MC14527B BCD rate multiplier (DRM) provides an output pulse rate
based upon the BCD input number. For example, if 6 is the BCD input
number, there will be six output pulses for every ten input pulses. This part
may be used for arithmetic operations including multiplication and division.
Typical applications include digital filters, motor speed control and frequency
synthesizers.
Output Clocked on the Negative Going Edge of Clock
Strobe for Inhibiting or Enabling Outputs
Enable and Cascade Inputs for Cascade Operation of Two or More
DRMs
9 Output for the Parallel Enable Configuration and DRMs in Cascade
Complementary Outputs
Clear and Set to Nine Inputs

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
500
mW
65 to + 150
_C
PD
Tstg
Storage Temperature
TL
260
_C
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
BLOCK DIAGRAM
4
12
RATE INPUT
Output
MULTIPLIER
Number of Pulses
Inputs
D*
No. of
Clock
Pulses
Ein
Strobe
Cascade
Clear
Set
Out
Out
Eout
0
0
0
0
0
0
0
1
10
10
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
4
5
6
2
3
4
5
6
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
8
9
7
8
9
8
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
10
10
10
10
10
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
8
9
8
9
8
9
1
1
1
1
1
1
1
1
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10
10
10
10
10
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
10
0
0
1
0
10
1
1
1
1
1
1
0
1
1
0
0
1
11
9
10
14
TRUTH TABLE (X = Dont Care, *D = Most Significant Bit)

Logic Level
Plastic
Ceramic
SOIC
15
2
3
S
Eout
CASC
Ein
CLOCK OUT
ST
A
OUT
B
C
9
D
CLEAR
7
6
5
1
13
VDD = PIN 16
VSS = PIN 8
MC14527B
6315

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

MC14527B
6316
PIN ASSIGNMENT
9
16
VDD
15
14
13
CLEAR
OUT
12
CASC
OUT
11
Ein
Eout
10
ST
VSS
CLOCK

Characteristic
Symbol

tTLH,
tTHL

Clock to Out
tPHL,
tPHL
Clock to Out
tPLH,
tPHL
Clock to Eout
tPLH.
tPHL
Clock to 9
tPLH,
tPHL
Set or Clear to Out

tPHL = (0.66 ns/pF) CL + 132 ns
tPHL
Cascade to Out
tPLH
Strobe to Out
tPLH
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
200
100
70
400
200
140
5.0
10
15
125
65
45
250
130
90
5.0
10
15
295
130
85
590
260
170
5.0
10
15
400
155
110
800
310
220
5.0
10
15
380
165
110
760
330
220
5.0
10
15
125
65
45
250
130
90
5.0
10
15
230
105
70
260
210
140
tWH
5.0
10
15
500
200
150
250
110
80
ns
fcl
5.0
10
15
2.0
4.5
6.0
1.2
2.5
3.5
MHz
tTLH,
tTHL
5.0
10
15
15
5
4
Set or Clear Pulse Width
tWH
5.0
10
15
240
100
75
80
35
30
ns
Set Removal Time
trem
5.0
10
15
0
0
0
20
10
7.5
ns
tsu
5.0
10
15
400
150
120
175
60
45
ns
Clock Pulse Width
Enable In Setup Time
ns
ns
ns
ns
ns
ns
MC14527B
6317
0 1234 5678 90 123 4

CLOCK
VDD
Qa
Qb
Qc
S
CASC Eout
Ein
CLOCK
OUT
ST
A
OUT
B
C
9
D
CLEAR
PULSE
GENERATOR
MULTIPLIER
PRESET NO.
Qd
R1
R2
R3
R4
OUTPUT (PIN 6)
A ENABLED
VSS
B ENABLED
C ENABLED
D ENABLED
Figure 1. Test Circuit and Timing Diagram

Eout
OUTPUT (PIN 6)
(PRESET NO. OF 1)
(PRESET NO. OF 2)
(PRESET NO. OF 3)
(PRESET NO. OF 4)
VDD
S
CASC
Ein
CLOCK
ST
A
B
C
D
CLEAR
PROGRAMMABLE
PULSE
GENERATOR
(PRESET NO. OF 5)
Eout
(PRESET NO. OF 6)
(PRESET NO. OF 7)
OUT
(PRESET NO. OF 8)
OUT
CL
CL
CL
VSS
20 ns
20 ns
tTLH
CLOCK
(PRESET NO. OF 9)
CL
1
fcl
tTHL
90%
10%
50%
SET
trem
ENABLE IN
50%
tsu
SET
tWH
50%
tPHL
90%
10%
50%
OUT
tPLH
tTLH
tPHL
tTHL
MC14527B
6318
VDD
0.01 F
CERAMIC
500
pF
ID
VDD
PULSE
GENERATOR
S
CASC Eout
Ein
CLOCK
OUT
ST
A
OUT
B
C
D
9
CLEAR
VSS
20 ns
CLOCK
CL
CL
20 ns
VDD
90%
50%
10%
VARIABLE WIDTH
VSS
50% DUTY CYCLE
CL
CL
LOGIC DIAGRAM
ENABLE IN
11
D C B A
2 15 14
STROBE CASCADE
10
12
T
C a
R
Q
R1
CLOCK
R2
6 OUT
5 OUT
C b
R
R3
R4
VDD = PIN 16
VSS = PIN 8
C c
R
T S Q
1 9
C d
R
Q
7 ENABLE OUT
CLEAR
13
SET TO NINE
MC14527B
6319
MOST SIGNIFICANT
DIGIT
1
0
0
1
A
OUT
B
C
1
D
Eout
CLOCK
CASC
Ein
9
ST
CLEAR S
LEAST SIGNIFICANT
DIGIT
0
0
1
0
A
OUT
B
C
2
D
Eout
CLOCK
CASC
Ein
9
ST
CLEAR S
NOTE: More than two MC14527Bs

may be cascaded using this
configuration.
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
CLOCK
CLOCK
OUT
DRM 2
One of four output pulses contributed by DRM 2 to

output for every 100 clock pulses in for preset No. of 94.
Figure 4. Two MC14527Bs in Cascade with Preset No. of 94
MC14527B
6320
MOTOROLA
MC14528B
Dual Monostable Multivibrator
L SUFFIX
CERAMIC
CASE 620
The MC14528B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an
output pulse over a wide range of widths, the duration of which is determined
by the external timing components, CX and RX.
Separate Reset Available
Triggerable from Leading or Trailing Edge Pulse
PinforPin Replacement with the MC14538B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
CX1
1
RX1
VDD
2
6
4
A1
5
B1
Q1
Q1
ONESHOT SELECTION GUIDE

100 ns
1 ms
10 ms
100 ms
1 ms
10 ms
100 ms
MC14528B
MC14536B
MC14538B
MC14541B
1s
RESET 1
10 s
CX2
23 HR
RX2
VDD
5 MIN.
15
MC4538A*
*LIMITED OPERATING VOLTAGE (26 V)

TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
12
A2
11
B2
RESET 2
14
10
9
Q2
Q2
13
VDD = PIN 16
VSS = PIN 1, PIN 8, PIN 15
RX AND CX ARE EXTERNAL COMPONENTS
MC14528B
6321

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.64
1.6
4.2
1.0
0.51
1.3
3.4
1.7
0.88
2.25
8.8
0.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
IOL
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
mAdc
Source
IOH
Sink

external load Capacitance (CL)
and at external timing
capacitance (CX), use the
formula
Adc
IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x108

RXCX(VDD2)2f] x 103
where: IT in A (per circuit), CL and CX in pF, RX in megohms,
VDD in Vdc, f in kHz is input frequency.

MC14528B
6322
PIN ASSIGNMENT
VSS
16
VDD
CX1/RX1
15
VSS
RESET 1
14
CX2/RX2
A1
13
RESET 2
B1
12
A2
Q1
11
B2
Q1
10
Q2
VSS
Q2
SWITCHING CHARACTERISTICS** (CL = 50 pF, TA = 25_C)

Symbol
Characteristic
CX
pF
RX
k
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
325
120
90
650
240
180
5.0
10
15
705
290
210
Unit

tTLH,
tTHL
TurnOff, TurnOn Delay Time A or B to Q or Q

tPLH,
tPHL
15
TurnOff, TurnOn Delay Time A or B to Q or Q

tPLH,
tPHL
1000
Input Pulse Width A or B
tWH
15
5.0
5.0
10
15
150
75
55
70
30
30
ns
tWL
1000
10
5.0
10
15
70
30
30
ns
Output Pulse Width Q or Q

(For CX < 0.01 F use graph for
appropriate VDD level.)
tW
15
5.0
5.0
10
15
550
350
300
ns

(For CX > 0.01 F use formula:
tW = 0.2 RX CX Ln [VDD VSS])
tW
10,000
10
5.0
10
15
15
10
15
30
50
55
45
90
95
Pulse Width Match between Circuits in the same

package
t1 t2
10,000
10
5.0
10
15
6.0
8.0
8.0
25
35
35
Reset Propagation Delay Reset to Q or Q
tPLH,
tPHL
15
5.0
5.0
10
15
325
90
60
600
225
170
ns
1000
10
5.0
10
15
1000
300
250
ns
15
5.0
5.0
10
15
0
0
0
ns
1000
10
5.0
10
15
0
0
0
ns
5.0
1000
Retrigger Time
trr
External Timing Resistance
RX
ns
5.0
ns
10
ns
External Timing Capacitance

CX
No Limits*
RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.
* If CX > 15 F, Use Discharge Protection Diode DX, per Fig. 9.
FUNCTION TABLE
Inputs
Reset
H
H
H
H
H
H
L
Outputs
B
H
L
Not Triggered
Not Triggered
L, H,
L
H
L, H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
MC14528B
6323
VDD
16
VDD
16
IOL
A
OPEN
B
Q
RESET
IOH
VSS
VOL
VOH
RESET
Figure 1. Output Source Current Test Circuit
OPEN
Q
VSS
Figure 2. Output Sink Current Test Circuit
VDD
500 pF
0.1 mF
CERAMIC
ID
RX
CX
RX
CX
20 ns
Vin
20 ns
VDD
90%
A
CL
RESET
10%
Vin
DUTY CYCLE = 50%
0V
CL
CL
CL
RESET
VSS
VDD
RX
RX
CX
CX
PULSE
GENERATOR
*CX = 15 pF
*CL = 15 pF
RX = 5.0 kW
INPUT CONNECTIONS
A
Q
Characteristics
Reset
tPLH, tPHL, tTLH, tTHL

tW
VDD
PG1
VDD
tPLH, tPHL, tTLH, tTHL

tW
VDD
VSS
PG2
tPLH(R), tPHL(R), tW
PG3
PG1
PG2
CL
PULSE
GENERATOR
RESET
CL
CL
PULSE
GENERATOR
Q
CL
RESET
VSS
* Includes capacitance of probes,

wiring, and fixture parasitic.
PG1 =
NOTE: AC test waveforms for

PG1, PG2, and PG3 on
next page.
PG2 =
PG3 =
Figure 4. AC Test Circuit
MC14528B
6324
90%
10%
tTHL
50%
A
tTLH
tWH
tTHL
VDD
50%
VSS
tTLH
VDD
90%
10%
50%
VSS
tWL
tTHL
RESET
90%
10%
tTHL
tPLH
tW
50%
50%
50%
Q
tPHL
tTLH
VDD
50%
VSS
tWL
tTLH
90%
10%
tTLH
trr
tPHL
50%
VOL
tTHL
tPHL
VOH
tPHL
Q
50%
50%
VOH
90%
10%
50%
50%
VOL
Figure 5. AC Test Waveforms
t W, PULSE WIDTH ( m s)
1000
VDD = 15 V
15 V
10 V
5.0 V
10 V
5.0 V
100
RX = 100 kW
15 V
10 V
5.0 V
10
RX = 10 kW
RX = 5.0 kW
1.0
0.1
15 V
10 V
5.0 V
10
100
1000
10,000
100,000
CX, EXTERNAL CAPACITANCE (pF)
Figure 6. Pulse Width versus CX
MC14528B
6325
Cx
Cx
Rx
Rx
VDD
VDD
RISING EDGE
TRIGGER
Q
RESET
VDD
RISING EDGE
TRIGGER
Q
RESET
VDD
VDD
Cx
Cx
Rx
Rx
VDD
VDD
FALLING EDGE
TRIGGER
Q
RESET
FALLING EDGE
TRIGGER
Q
RESET
VDD
VDD
Figure 7. Retriggerable
Monostables Circuitry
Figure 8. NonRetriggerable
DX
Cx
VDD
NC
1, 15
Rx
2, 14
VDD
NC
Q
RESET
NC
A
Q
B
VDD
Q
RESET
VDD
Figure 9. Use of a Diode to Limit

Power Down Current Surge
MC14528B
6326
VDD
VDD
Figure 10. Connection of Unused Sections
MOTOROLA
MC14529B
Dual 4-Channel Analog
Data Selector
L SUFFIX
CERAMIC
CASE 620
The MC14529B analog data selector is a dual 4channel or single

8channel device depending on the input coding. The device is suitable for
digital as well as analog application, including various oneoffour and
oneofeight data selector functions. Since the device has bidirectional
analog characteristics it can also be used as a dual binary to 1of4 or a
binary to 1of8 decoder.
Data Paths Are Bidirectional
3State Outputs
Linear On Resistance
Schottky TTL Load over the Rated Temperature Range.

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
TRUTH TABLE (X = Dont Care)

STX
1
1
1
1
STY
1
1
1
1
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Y0
Y1
Y2
Y3
High
Impedance
Dual 4Channel Mode

2 Outputs
Single 8Channel Mode

1 Output
(Z and W tied together)
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
3STATE OUTPUT ENABLE
STROBE X 1
6
7
2
3
4
5
A
B
X0
X1
X2
X3
14
13
12
11
Y0
Y1
Y2
Y3
10
STROBE Y 15
VDD = PIN 16
VSS = PIN 8

MC14529B
6327
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit

Range
VDD
VDD 3.0 VSS

VEE
3.0
18
3.0
18
3.0
18

Package
IDD
5.0
10
15

VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
Vswitch
500 mV**
1.0
1.0
2.0
0.005
0.010
0.015
1.0
1.0
2.0
60
60
120

(Dynamic Plus
Quiescent, Per Package
ID(AV)
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout) / Ron, is
not included.)
Typical

CONTROL INPUTS INHIBIT, A, B (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN W, Z (Voltages Referenced to VEE)

Recommended Peakto
Peak Voltage Into or
Out of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Dynamic Voltage
Across the Switch**
(Figure 5)
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
10
15
Vswitch
500 mV**,
Vin = VIL or VIH
0 to VDD (Switch)
400
240
120
80
480
270
560
350
Ron
10
15
15
10
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Inhibit = VDD
8.0
pF
CO/I
Inhibit = VDD
20
pF
(Channel Off)
CI/O
Pins Not Adjacent

Pins Adjacent
0.15
0.47
pF
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 10)
#Data labelled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential performance.
MC14529B
6328
SWTCHING CHARACTERISTICS (TA = 25_C)

Figure
Symbol
VSS
VDD
Min
Typ #
Max
Unit
Vin to Vout Propagation Delay Time

(CL = 50 pF, RL = 1.0 k)
tPLH, tPHL
0.0
5.0
10
15
20
10
8.0
40
20
15
ns
Propagation Delay Time, Control to

Output, Vin = VDD or VSS
(CL = 50 pF, RL = 1.0 k)
tPLZ, tPZL,
tPHZ, tPZH
0.0
5.0
10
15
140
70
50
400
160
120
ns
Crosstalk, Control to Output

(CL = 50 pF, RL = 1.0 k
Rout = 10 k)
0.0
5.0
10
15
5.0
5.0
5.0
mV
Control Input Pulse Frequency

(CL = 50 pF, RL = 1.0 k)
10
fin
0.0
5.0
10
15
5.0
10
12
2.5
6.2
8.3
MHz
11, 12
0.0
5.0
10
15
24
25
30
nV/
cycle
5.0
10
15
12
12
15
5.0
5.0
0.36
5.0
5.0
7.5
7.5
5.0
5.0
7.5
7.5
0.001
0.001
0.0015
0.0015
125
125
250
250
5.0
5.0
Characteristic
Noise Voltage
(f = 100 Hz)
Sine Wave Distortion

(Vin = 1.77 Vdc RMS
Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)
OffChannel Leakage Current

(Vin = + 5.0 Vdc, Vout = 5.0 Vdc)
(Vin = 5.0 Vdc, Vout = + 5.0 Vdc)
(Vin = + 7.5 Vdc, Vout = 7.5 Vdc)
(Vin = 7.5 Vdc, Vout = + 7.5 Vdc)
Ioff
Insertion Loss
(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc,
f = 1.0 MHz)
Iloss = 20 Log10 (Vout / Vin)
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
13
Bandwidth ( 3 dB)
(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc)
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
Feedthrough and Crosstalk

20 Log10 (Vout / Vin) = 50 dB
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)
dB
5.0
5.0
2.0
0.8
0.25
0.01
5.0
MHz
nA
BW
35
28
27
26
5.0
MHz
850
100
12
1.5
MC14529B
6329
VDD
STX
STY
A
B
VN
X3
Y3
IS
1k
Z
W
VSS
Pins 2, 3, 4, 12, 13 and 14 are left open.

OUT
VSS
VDD
VSS = 0.0 V
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD
VIL: Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON
VIH: specifications are met.
Vin
Figure 1. Output Voltage

Test Circuit
Figure 2. Noise Immunity

Test Circuit
VDD
STX = STY = VDD
ID
VDD
PULSE
GENERATOR
OUT
OUT
10 k
fc
RL
VSS
VDD
A0, A1
VSS
PD = VDD x ID
Vin
Vin
Figure 3. Quiescent Power Dissipation

Test Circuit
Figure 4. RON Characteristics

Test Circuit
TYPICAL RON versus INPUT VOLTAGE

250
VDD = 5 V
VSS = 5 V
200
150
VDD = 7.5 V
VSS = 7.5 V
100
50
10
Figure 5.
MC14529B
6330
10
R ON ON RESISTANCE (OHMS)
R ON ON RESISTANCE (OHMS)
250
VDD = 10 V
VSS = 0 V
200
VDD = 15 V
VSS = 0 V
150
100
50
10
15
20
25
Figure 6.
Vout
OUT
VSS
VDD
RL
STX, STY
CL
Vin
Vin
20 ns
20 ns
90%
50%
Vin
STX, STY
20 ns
tPLH
VDD
10%
tPHL
50%
Vout

and Waveforms
10%
Vout
tPZL
90%
A OR B
V
tPHZ SS
Vin
90%
Vx
tPLZ
VDD
VSS
Vin
Vx
VSS
VDD
10%

and Waveforms
VFeedthrough
10 k
VDD
90%
10%
50%
Vout
OUT
CONTROL
LOGIC
VX
tPZH
VSS
CL
RL
50 pF
VSS
X, Y
INPUT
RL
VDD
OUT
RL
VSS
VDD
Vin
+2.5 Vdc
1k
Vin
Figure 9. Crosstalk Test Circuit
0.0 Vdc
2.5 Vdc
X, Y INPUT
Figure 10. Frequency Response Test Circuit
30
VDD = 15 Vdc
25
NOISE VOLTAGE (nV/ CYCLE)
35
OUT
VSS
VDD
IN
QUANTECH
MODEL
2283
OR EQUIV
10 Vdc
20
5.0 Vdc
15
10
5.0
0
10
Figure 11. Noise Voltage Test Circuit
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 12. Typical Noise Characteristics
MC14529B
6331
PIN ASSIGNMENT
2.0
RL = 1 MW AND 100 kW
TYPICAL INSERTION LOSS (dB)
STX
16
VDD
10 kW
X0
15
STY
1.0 kW
X1
14
Y0
X2
13
Y1
X3
12
Y2
11
Y3
10
VSS
2.0
4.0
3.0 dB (RL = 1.0 MW)

3.0 dB (RL = 10 kW)
6.0
3.0 dB (RL = 1.0 kW)
8.0
10
12
10 k
100 k
1.0 M
10 M
fin, INPUT FREQUENCY (Hz)
100 M
Figure 13. Typical Insertion Loss/Bandwidth

Characteristics
LOGIC DIAGRAM
B
7
A
6
STY STX
15
1
2
X0
3
X1
9
Z
4
X2
5
X3
14
Y0
13
Y1
10
W
12
Y2
11
Y3
VDD = PIN 16
VSS = PIN 8
MC14529B
6332
MOTOROLA
MC14530B
Dual 5-Input Majority
Logic Gate
L SUFFIX
CERAMIC
CASE 620
The MC14530B dual fiveinput majority logic gate is constructed with

monolithic structure. Combinational and sequential logic expressions are
easily implemented with the majority logic gate, often resulting in fewer
components than obtainable with the more basic gates. This device can also
provide numerous logic functions by using the W and some of the logic (A
thru E) inputs as control inputs.
P SUFFIX
PLASTIC
CASE 648

D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
LOGIC TABLE
INPUTS A B C D E
For all combinations of inputs where three or

more inputs
i
t are llogical
i l 0
0.
For all combinations of inputs where three or

more inputs
i
t are llogical
i l 1
1.
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
W
6
1
2
3
4
5
A
B
C
D
E
* Z = M5
Z = M5
Z = M5
9
10
11
12
13
7
Z
M5
W = (ABC+ABD+ABE+ACD+
W = (ACE+ADE+BCD+BCE+
W = (BDE+CDE) W
A
B
C
D
E
15
Z
M5
14
W
* M5 is a logical 1 if any three or more
inputs are logical 1.
Exclusive NOR Exclusive OR

TRUTH TABLE
M5
0
0
1
1
0
1
0
1
1
0
0
1
VDD = PIN 16
VSS = PIN 8
MC14530B
6333

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.2
2.5
3.0
2.25
4.50
6.75
1.25
2.5
3.0
1.15
2.4
2.9
5.0
10
15
3.85
7.6
12.1
3.75
7.5
12
2.75
5.50
8.25
3.75
7.5
12
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
* To calculate total supply current at loads other than 50 pF:
PIN ASSIGNMENT
MC14530B
6334
AA
16
VDD
BA
15
ZB
CA
14
WB
DA
13
EB
12
DB
EA
WA
11
CB
ZA
10
BB
VSS
AB

Characteristic
Symbol

tTLH,
tTHL

A, C, W = VDD; B, E = Gnd; D = Pulse Generator
tPLH = (0.66 ns/pF) CL + 127 ns
tPLH

tPHL = (0.66 ns/pF) CL + 162 ns
tPHL
A, B, C, D, E = Pulse Generator; W = VDD

VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
ns
ns
5.0
10
15
375
160
110
960
400
300
5.0
10
15
430
195
120
1200
540
410
5.0
10
15
255
120
86
640
300
210
5.0
10
15
280
125
100
750
330
250
5.0
10
15
230
105
75
575
265
190
tPLH

tPHL
A, B, C, D, E = Gnd; W = Pulse Generator

tPLH,
tPHL
Unit
ns
ns
ns
ns
VDD
16
A
B
C
D
PULSE
GENERATOR
CL
W
A
B
C
D
E
W
20 ns
Vin
20 ns
50%
DUTY
CYCLE
CL
VSS
VDD
VSS
Figure 1. Power Dissipation Test

Circuit and Waveform
MC14530B
6335
SEQUENTIAL LOGIC APPLICATIONS
1
0
1
x
y
COINCIDENT FLIPFLOP
W
A
B
C
D
E
Qn+1
0
0
0
1
0
1
0
1
0
Q
Q
1
A flipflop that will change only when both inputs agree.
ASTABLE MULTIVIBRATOR
0
0
1
x
y
W
A
B
C
D
E
Qn+1
0
0
1
1
0
1
0
1
1
2
2
1
A flipflop with three output conditions, where the third state is

in oscillation between 1 and 0. The period of oscillation is
twice the delay of the gate and the feedback element.
COINCIDENT FLIPFLOP
1
x
y
z
W
A
B
C
D
E
MC14530B
6336
tx
Qn+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Qn
Qn
Qn
Qn
Qn
Qn
1
The flipflop changes state only when all 1s or all 0s are

entered. This configuration may be extended by cascading M5
gates to cover ninputs where all inputs must be 1s or 0s
before the output will change. As an example, this configuration is useful for controlling an nstage up/down counter that is
to cycle from a minimum to maximum count and back again
without flipping over (from all 1s to all 0s.)
BASIC COMBINATIONAL FUNCTIONS

1
A
B
C
D
E
5INPUT MAJORITY LOGIC GATE APPLICATIONS

Each package labeled M5 is a single majority logic gate
using five inputs, A thru E, and one output Z.
W
A
B
C
D
E
Z
M5
1. Majority Logic Gate Array

yielding the symmetric function
of 1 thru 7 variables true, out
of 7 input variables (X1... X7)
M5
5INPUT MAJORITY GATES

1
1
0
0
1
0
Z
A
B
C
(e.g., if any twoinput variables

are true (logical 1), Z1 and
Z2 are true (logical 1)
Z
A
B
C
M3
0
0
A
B
C M5
D
E
Z7
A
B
C M5
D
E
Z6
M5
A
B
C M5
D
E
Z5
M5
A
B
C M5
D
E
Z4
M5
A
B
C M5
D
E
Z3
A
B
C M5
D
E
Z2
A
B
C M5
D
E
Z1
M3
3INPUT MAJORITY GATES

1
1
1
0
1
1
Z
A
B
C
OR3
3INPUT OR GATE
1
0
0
Z
A
B
C
NOR3
3INPUT NOR GATE
0
0
0
Z
A
B
C
AND3
3INPUT AND GATE
W
Z
A
B
C
0
0
NAND3
3INPUT NAND GATE
DOUBLING THE WEIGHT OF INPUT VARIABLE A

BY TYING IT TO ANY TWO INPUTS
W
W
A
A
B
C
D
To
S0
S1
S2
S3
S4
To
To
S0
S1
S2
S3
W
A
B
C
D
E
W
0
0
CORRELATION OF MULTIPLE SAMPLES

WITH A TEST BIT
Z
M5
CORRELATION OF 60%, 80%, 100%

The gate will have a 1 output if
the test bit To matches or correlates with 3, 4 or 5 of the sample
bits S0S4.
W
A
B
C
D
E
(AB + AC + AD + BCD)
0
1
1
M5
CORRELATION OF 75%, 100%

1
1
1
1
M5
To
To
To
S0
S1
S2
1
M5
1
1
M5
W
A
B
C
D
E
CORRELATION OF 100%
X1
X3
X4
X5
X6
X7
X2
MC14530B
6337
MOTOROLA
MC14531B
12-Bit Parity Tree
L SUFFIX
CERAMIC
CASE 620
The MC14531B 12bit parity tree is constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic structure. The
circuit consists of 12 databit inputs (D0 thru D11), and even or odd parity
selection input (W) and an output (Q). The parity selection input can be
considered as an additional bit. Words of less than 13 bits can generate an
even or odd parity output if the remaining inputs are selected to contain an
even or odd number of ones, respectively. Words of greater than 12bits can
be accommodated by cascading other MC14531B devices by using the W
input. Applications include checking or including a redundant (parity) bit to a
word for error detection/correction systems, controller for remote digital
sensors or switches (digital event detection/correction), or as a multiple input
summer without carries.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Variable Word Length
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
VDD
Vin, Vout
Iin, Iout
PD
Tstg
TL
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5

per Pin
10
mA

Storage Temperature
500
mW
65 to + 150
_C
260
_C
LOGIC DIAGRAM
TRUTH TABLE
Inputs
Output
Decimal
(Octal)
Equivalent
D11
D10
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
(0)
(1)
(2)
(3)
0
1
1
0
4
5
6
7
(4)
(5)
(6)
(7)
1
0
0
1
Q*
D0
D1
D2
6
5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
D3
D4
4
3
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D5
D6
2
1
D7
D8
15
14
1
1
1
1
1
1
1
1
1.
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
8184 (17770)
8185 (17771)
8186 (17772)
8187 (17773)
0
1
1
0
D9
D10
13
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188 (17774)
8189 (17775)
8190 (17776)
8191 (17777)
1
0
0
1
D11
ODD/EVEN W
11
10
Q = D0
MC14531B
6338
9 Q
VDD = PIN 16
VSS = PIN 8
D1 D2 @@@@ D11 W
*0 = Even Parity
1 = Odd Parity
NOTE: May redefine to suit application by manipulating W and/or other
available Ds.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

PIN ASSIGNMENT
D6
16
VDD
D5
15
D7
D4
14
D8
D3
13
D9
D2
12
D10
D1
11
D11
D0
10
VSS
MC14531B
6339

Characteristic
Symbol

tTLH,
tTHL

Data to Q
Odd/Even to Q
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
440
175
120
1320
525
360
5.0
10
15
250
100
70
750
300
210
20 ns
20 ns
90%
SIGNAL
INPUT
10%
20 ns
VDD
50%
VSS
INPUT
(D OR W)
1
DATA RATE (f)
f IN RESPECT TO SYSTEM CLOCK
Figure 1. Dynamic Power Dissipation

Signal Waveform
MC14531B
6340
20 ns
90%
50%
tPLH
90%
OUTPUT
10%
tTLH
VDD
10%
VSS
tPHL
VOH
50%
VOL
tTHL
MOTOROLA
MC14532B
8-Bit Priority Encoder
L SUFFIX
CERAMIC
CASE 620
The MC14532B is constructed with complementary MOS (CMOS)

enhancement mode devices. The primary function of a priority encoder is to
provide a binary address for the active input with the highest priority. Eight
data inputs (D0 thru D7) and an enable input (Ein) are provided. Five outputs
are available, three are address outputs (Q0 thru Q2), one group select (GS)
and one enable output (Eout).
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

500
mW
65 to + 150
_C
260
_C
PIN ASSIGNMENT
D4
16
VDD
D5
15
Eout
D6
14
GS
TRUTH TABLE
D7
13
D3
Ein
12
D2
Input
Ein
D7
D6
D5
D4
Output
D3
D2
D1
D0
GS
Q2
Q1
Q0
Eout
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
Q2
11
D1
Q1
10
D0
VSS
Q0
X = Dont Care

MC14532B
6341

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14532B
6342

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time Ein to Eout

tPLH,
tPHL
Propagation Delay Time Ein to GS

tPLH, tPHL = (0.66 ns/pF) CL 57 ns
tPLH,
tPHL
Propagation Delay Time Ein to Qn

tPHL,
tPLH
Propagation Delay Time Dn to Qn

tPLH,
tPHL
Propagation Delay Time Dn to GS

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
205
110
80
410
220
160
5.0
10
15
175
90
65
350
180
130
5.0
10
15
280
140
100
560
280
200
5.0
10
15
300
170
110
600
340
220
5.0
10
15
280
140
100
560
280
200
Unit
ns
ns
ns
ns
ns
ns
Vout
Ein
D0
D1
Eout
Q0
Q1
D2
D3
SWITCH
MATRIX
D4
D5
VDD
Q2
ID
GS
500 F
D6
EXTERNAL
POWER
SUPPLY
VGS = VDD
VDS = Vout
Sink Current
Ein
D0
D1
VGS = VDD
VDS = Vout VDD
Source Current
Output
Under
Test
D0 thru D7
Ein
D0 thru D6
D7
Ein
Eout
Q0
Q1
Q2
GS
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Figure 1. Typical Sink and Source

Current Characteristics
D2
D3
D4
D5
PULSE
GENERATOR
(fo)
0.01 F
ID
D7
Eout
CL
Q0
CL
Q1
CL
Q2
CL
D6
D7
GS
VSS
CL
MC14532B
6343
VDD
Eout
Ein
D0
D1
PROGRAMMABLE
PULSE
GENERATOR
CL
Q0
D2
D3
Q1
D4
D5
Q2
CL
CL
D6
CL
GS
D7
VSS
CL
NOTE: Input rise and fall times are 20 ns

PIN
NO.
D0
10
D1
11
D2
12
D3
13
D4
D5
D6
D7
Ein
50%
50%
50%
50%
50%
50%
Eout
15
50%
50%
50%
tPLH
tPHL
90%
50%
10%
tTHL
tPLH
tTLH
GS
Q0
14
tTLH
tPLH
tPLH
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPLH
tPHL
Q1
7
tPLH
Q2
tTLH
tTLH
tTLH
tPHL
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
tPHL
90%
50%
10%
tTHL
MC14532B
6344
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7
Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
10
D0
Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7)

Q2 = Ein (D4 + D5 + D6 + D7)
GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
11
D1
9
Q0
12
D2
13
D3
1
D4
7
Q1
2
D5
3
D6
4
D7
6
Q2
5
Ein
14
GS
15
Eout
MC14532B
6345
D15 D14 D13 D12 D11 D10
D7
VDD
D6
D5
D4
D3
D2
Ein
GS
Q2 Q1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Eout
Ein
Eout = 1
WITH Din = 0
Eout
Q0
Q2 Q1
Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532Bs Cascaded for 4Bit Output
VDD
VSS
CLOCK
INPUT
C
DIGITAL TO ANALOG CONVERSION

The digital eightbit word to be converted is applied to
the inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between I bias for the MC1710 and R
between N and Pchannel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms,
C
0.03 F). The analog 3.0 dB bandwidth would then be
dc to 1.0 kHz.
Q1
ANALOG TO DIGITAL CONVERSION

An analog signal is applied to the analog input of the
MC1710. A digital eightbit word known to represent a digitized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
1/2 MC14520B
Q2
Q3
1/2 MC14520B
Q4
Q1
Q2
Q3
Q4
DIGITAL INPUT/OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7
VDD
8BIT WORD
TO BE CONVERTED
Ein
Q2 Q1 Q0
A
B
C
X7 X6 X5 X4 X3 X2 X1 X0
MC1710
MC14512
Z
R
ANALOG
OUTPUT
STOP
WORD
INCREMENTATION
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
MC14532B
6346
MOTOROLA
MC14534B
5 Cascaded BCD Counters
L SUFFIX
CERAMIC
CASE 623
The MC14534B is composed of five BCD ripple counters that have their
respective outputs multiplexed using an internal scanner. Outputs of each
counter are selected by the scanner and appear on four (BCD) pins.
Selection is indicated by a logic high on the appropriate digit select pin. Both
BCD and digit select outputs have threestate controls providing an
opencircuit when these controls are high and allowing multiplexing.
Cascading may be accomplished by using the carryout pin. The counters
and scanner can be independently reset by applying a high to the counter
master reset (MR) and the scanner reset (SR). The MC14534B was
specifically designed for application in real time or event counters where
continual updating and multiplexed displays are used.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
Four Operating Modes (See truth table)

Input Error Detection Circuit
Clock Conditioning Circuits for Slow Transition Inputs
Counter Sequences on Positive Transition of Clock A
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
TO CAPACITORS
22
1
VDD = PIN 24
VSS = PIN 12
23
CLOCK B
PULSE
SHAPER
CLOCK A
4
MASTER 2
RESET
TENS
Cn+4
Q0
ERROR OUT
TEST
CONTROL
UNITS
C 10
PULSE ERROR
DETECTOR
CARRY
CONTROL
C 10
Q3
HUNDREDS
C 10
Cn+4
Q0
Q3
THOUSANDS
Cn+4
Q0
Q3
C 10
Cn+4
Q0
Q3
TEN
THOUSANDS
C 10
Cn+4
Q0
13
CARRY OUT
Q3
5
MODE A
OUTPUT
CONTROL
MODE B
MUX
MUX
MUX
17
MUX
Q3
6
MUX
18
Q2
BCD
OUT
19
SCANNER
RESET 9
Q1
R
20
SCANNER 10
CLOCK
Q0
SCANNER
21
8
DS1
NOTE:
= 3STATE
OUTPUT BUFFER
14
DS2
16
DS3
DIGIT SELECT
DS4
11
DS5
15 3STATE DIGIT
CONTROL
3STATE BCD
CONTROL
3State Control
Out
0
1
Q or DS
High Impedance
MC14534B
6347
MAXIMUM RATINGS (Voltages referenced to VSS)

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
3.0
1.5
3.0
4.5
1.0
2.0
3.0
1.0
2.0
3.0
5.0
10
15
4.0
8.0
12
4.0
8.0
12
3.5
7.0
11
4.0
8.0
12
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
5.0
10
15
0.31
0.31
0.9
0.25
0.25
0.75
0.8
0.4
1.6
0.17
0.17
0.51
IOL
5.0
10
15
0.024
0.06
1.3
0.02
0.05
0.25
0.03
0.09
1.63
0.014
0.035
0.175
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
IOL
Output Drive Current Pins 1 and 22

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
Source
(VOH = 13.5 Vdc)
IOH
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Sink
mAdc
mAdc
MC14534B
6348
mAdc
(continued)
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued)

55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
Characteristic
Symbol
Quiescent Current
(Per Package)
15

0.1
0.0001
Adc
Scan Oscillator
Frequency = 1.0 kHz
0.1
3.0
Adc
MC14534B
6349
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, see Figure 1)

Characteristic
Symbol
tTLH,
tTHL
Propagation Delay Time,

Clock to Q
tPLH, tPHL = (1.8 ns/pF) CL + 4.0 s
tPLH,
tPHL
3.3
1.1
0.8
6.6
2.2
1.7
5.0
10
15
1.8
0.6
0.5
3.6
1.2
0.9
5.0
10
15
0.6
0.2
0.12
1.5
.5
0.38
5.0
10
15
1.8
0.6
0.5
3.6
1.2
0.9
5.0
10
15
1.5
0.5
0.4
3.0
1.0
0.75
tPHZ
5.0
10
15
75
45
40
150
90
80
ns
tPZH
5.0
10
15
120
55
40
240
110
80
ns
tPLZ
5.0
10
15
120
55
45
240
110
90
ns
tPZL
5.0
10
15
160
70
45
320
140
90
ns
fcl
5.0
10
15
1.0
3.0
5.0
0.5
1.0
1.2
MHz
tWH
5.0
10
15
1000
500
375
500
190
125
ns
tw
5.0
10
15
320
130
80
160
65
40
ns
trem
5.0
10
15
900
150
100
270
80
50
ns
tWH(R)
5.0
10
15
2000
600
450
900
300
250
ns
trem
5.0
10
15
1060
350
250
550
205
140
ns
Scanner Clock to Q
tPLH,
tPHL
Scanner Clock to Digit Select

tPHL, tPLH = (1.8 ns/pF) CL + 1.5 s
tPLH,
tPLH
tPHL
Master Reset Pulse Width
ns
5.0
10
15
Master Reset to Error Out

tPHL = (1.8 ns/pF) CL + 0.57 s
tPHL = (0.8 ns/pF) CL + 0.19 s
tPHL = (0.6 ns/pF) CL + 0.11 s
Scanner Reset Removal Time
Unit
200
100
80
8.0
3.0
2.25
tPHL
Scanner Reset Pulse Width
Max
100
50
40
4.0
1.5
1.0
Master Reset to Q
tPHL = (1.8 ns/pF) CL + 1.8 s
tPHL = (0.8 ns/pF) CL + 0.6 s
tPHL = (0.6 ns/pF) CL + 0.5 s
Clock or Scanner Clock Pulse Width
Typ #
tPLH
Min
5.0
10
15
5.0
10
15
Clock to Carry Out

tPLH = (1.8 ns/pF) CL + 3.3 s
tPLH = (0.8 ns/pF) CL + 1.1 s
tPLH = (0.6 ns/pF) CL + 0.8 s

3State Control to Q
VDD
Vdc
MC14534B
6350
COUNTER TIMING DIAGRAM

1 2
3 4
5 6
7 8
9 10
102
103
104
105
106
CLOCK A
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
UNITS Cn + 4
TENS Q0
TENS Q3
TENS Cn + 4
HUNDREDS Q0
HUNDREDS Q3
HUNDREDS Cn + 4
THOUSANDS Q0
THOUSANDS Q3
THOUSANDS Cn + 4
TEN THOUSANDS Q0
TEN THOUSANDS Q3
CARRY OUT
MASTER RESET
MODE CONTROL TRUTH TABLE

Mode A
Mode B
First Stage Output
Carry to Second Stage
Application
Normal Count and Display
At 9 to 0 transition of first stage
5digit Counter
Inhibited
Input Clock
Test Mode: Clock directly into stages 1, 2, and 4.
Inhibited
4digit counter with 10 and roundoff at front end.
Counts 3, 4, 5, 6, 7 = 5
Counts 8, 9, 0, 1, 2 = 0
4digit counter with 1/2 pence capability.
MC14534B
6351
SCANNER TIMING DIAGRAM

SCANNER
CLOCK
SCANNER
RESET
DS1
UNITS
DS2
TENS
DS3
HUNDREDS
DS4
THOUSANDS
DS5
TEN
THOUSANDS
NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be
shortened to four stages.
DS5 is selected automatically when Scanner Reset goes high.
ERROR DETECTION TIMING DIAGRAM

RESET
CLOCK A
CLOCK B
ERROR
OUT
GOOD PULSE
ERROR
1
ERROR
2
GOOD PULSE
ERROR
3
ERROR
4
NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at
Clock A is not accompanied by a negative pulse at Clock B (or viceversa) within
a time period of the oneshots an error is counted. Three errors result in Error Out
to go to a 1. If error detection is not needed, tie Clock B high or low and leave
Pins 1 and 22 unconnected.
CLOCK SKEW RANGE
ALLOWABLE CLOCK SKEW (ns/pF)
1000
500
300
100
SKEW IN THIS RANGE

RESULTS IN COUNTED
ERROR.
50
30
MAX
SKEW IN THIS RANGE
MAY OR MAY NOT
RESULT IN COUNTED
ERROR.
10
5.0
3.0
1.0
3.0
TYP
SKEW IN THIS RANGE

RESULTS IN NO ERROR
COUNTED.
MC14534B
6352
5.0
7.0
MIN
9.0
11
VDD (Vdc)
13
15
NOTES:
1. The skew is the time difference between the
lowtohigh transition of CA to the highto
low transition of CB or viceversa. Capacitors
C1 = C22 tied from pins 1 and 22 to VSS.
2. This graph is accurate for C1 = C22 100 pF.
3. When the error detection circuitry in not used,
pins 1 and 22 are left open.
17
VDD
En
CLOCK
MC14534B
1/2
MC14518B
Q4
CLOCK A
MC14534B
Cout*
CLOCK A
* Carry Out is high for a single clock period when all five BCD stages go to zero.
(Carry Out also goes high when MR is applied.)
Figure 1. Cascade Operation
CLOCK
Q0
CLOCK A
Q1
MC14534B
Q2
SC
BCD FOR
SELECTED
STAGE
Q3
DS1
DS2
DS3
DS4
DS5
When the Q outputs of a given stage are required, this configuration will
lock up the selected stage within four clock cycles. The select line feedback
may be hardwired or switched.
Figure 2. Forcing a BCD Stage to the Q Outputs
PIN ASSIGNMENT
Cext
24
VDD
MR
23
CLOCK B
Eout
22
Cext
CLOCK A
21
3ST BCD
MODE A
20
Q0
MODE B
19
Q1
DS1
18
Q2
DS2
17
Q3
SR
16
DS4
SC
10
15
3ST DIG
DS5
11
14
DS3
VSS
12
13
Cout
MC14534B
6353
MOTOROLA
MC14536B
Programmable Timer
L SUFFIX
CERAMIC
CASE 620
The MC14536B programmable timer is a 24stage binary ripple counter

with 16 stages selectable by a binary code. Provisions for an onchip RC
oscillator or an external clock are provided. An onchip monostable circuit
incorporating a pulsetype output has been included. By selecting the
appropriate counter stage in conjunction with the appropriate input clock
frequency, a variety of timing can be achieved.
24 FlipFlop Stages Will Count From 20 to 224
Last 16 Stages Selectable By FourBit Select Code

8Bypass Input Allows Bypassing of First Eight Stages
Set and Reset Inputs
Clock Inhibit and Oscillator Inhibit Inputs
OnChip RC Oscillator Provisions
OnChip Monostable Output Provisions
Clock Conditioning Circuit Permits Operation With Very Long Rise and
Fall Times
Test Mode Allows Fast Test Sequence
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
500
mW
65 to + 150
_C
PD
Tstg
Storage Temperature
TL
260
_C
BLOCK DIAGRAM
CLOCK INH.
7
RESET SET 8 BYPASS

2
1 6
OSC. INHIBIT 14
IN1
STAGES 9 THRU 24
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
STAGES
1 THRU 8
3
4
OUT1
5
OUT2
VDD = PIN 16
VSS = PIN 8
A 9
B 10
C 11
D 12
DECODER
MONOIN 15
MC14536B
6354
MONOSTABLE
MULTIVIBRATOR
13
DECODE
OUT

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Source
Pins 4 & 5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.25
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
Source
Pin 13
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14536B
6355

Characteristic
Symbol
Output Rise and Fall Time (Pin 13)

tTLH,
tTHL

Clock to Q1, 8Bypass (Pin 6) High
tPLH,
tPHL
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
3600
1300
1000
5.0
10
15
3.8
1.5
1.1
7.6
3.0
2.3
5.0
10
15
7.0
3.0
2.2
14
6.0
4.5
5.0
10
15
1500
600
450
3000
1200
900
tWH
5.0
10
15
600
200
170
300
100
85
ns
fcl
5.0
10
15
1.2
3.0
5.0
0.4
1.5
2.0
MHz
tTLH,
tTHL
5.0
10
15
tWH
5.0
10
15
tPLH,
tPHL
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL
Reset Pulse Width
Max
1800
650
450
Clock to Q16
Typ #
tPLH,
tPHL

(50% Duty Cycle)
Min
5.0
10
15
Clock to Q1, 8Bypass (Pin 6) Low

Clock Pulse Width
VDD
ns
No Limit
1000
400
300
500
200
150
ns

MC14536B
6356
PIN ASSIGNMENT
SET
16
VDD
RESET
15
MONO IN
IN 1
14
OSC INH
OUT 1
13
DECODE
OUT 2
12
8BYPASS
11
CLOCK INH
10
VSS
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flipflop stages. After Set goes low
(inactive), the occurrence of the first negative clock transition
on IN1 causes Decode Out to go low. The counters flipflop
stages begin counting on the second negative clock transition of IN1. When Set is high, the onchip RC oscillator is
disabled. This allows for very lowpower standby operation.
RESET (Pin 2) A high on Reset asynchronously forces
Decode Out to a low level; all 24 flipflop stages are also
reset to a low level. Like the Set input, Reset disables the
onchip RC oscillator for standby operation.
IN1 (Pin 3) The devices internal counters advance on
the negativegoing edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT 1 and
OUT 2 to form an RC oscillator. When an external clock is
used, both OUT 1 and OUT 2 may be left unconnected or
used to drive 1 LSTTL or several CMOS loads.
8BYPASS (Pin 6) A high on this input causes the first
8 flipflop stages to be bypassed. This device essentially becomes a 16stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) A high on this input disconnects the first counter stage from the clocking source. This
holds the present count and inhibits further counting. However, the clocking source may continue to run. Therefore,
when Clock Inhibit is brought low, no oscillator startup time
is required. When Clock Inhibit is low, the counter will start
counting on the occurrence of the first negative edge of the
clocking source at IN1.
OSC INHIBIT (Pin 14) A high level on this pin stops the
RC oscillator which allows for very lowpower standby operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONOIN (Pin 15) Used as the timing pin for the on
chip monostable multivibrator. If the MonoIn input is connected to V SS , the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between MonoIn and V DD. This resistor and the devices internal capacitance will determine the minimum output pulse
widths. With the addition of an external capacitor to V SS, the
pulse width range may be extended. For reliable operation
the resistor value should be limited to the range of 5 k to
100 k and the capacitor value should be limited to a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) These inputs select the
flipflop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) Outputs used in conjunction with
IN1 to form an RC oscillator. These outputs are buffered and
may be used for 20 frequency division of an external clock.
DECODE OUT (Pin 13) Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flipflop stages
into three 8stage sections to facilitate a fast test sequence.
The test mode is enabled when 8Bypass, Set and Reset
are at a high level. (See Figure 8.)
MC14536B
6357
TRUTH TABLES
Input
Input
8Bypass
Stage Selected
for Decode Out
8Bypass
Stage Selected
for Decode Out
10
11
12
13
14
15
16
17
18
10
19
11
20
12
21
13
22
14
23
15
24
16
FUNCTION TABLE
Set
Reset
Clock
Inh
OSC
Inh
No
Change
Advance to
next state
No
Change
No
Change
No
Change
In1
Out 1
Out 2
Decode
Out
Advance to
next state
X = Dont Care
MC14536B
6358
IN1
SET
1
4
OUT 1
OSC INHIBIT
14
OUT 2
7
CLOCK
INHIBIT
En R
S
Q
T 1
RESET
2
STAGES
2 THRU 7
8
15
MONOIN
A
B
C
D
9
10
11
12
T 9
8BYPASS
STAGES
10 THRU
15
16
DECODER
OUT
13
DECODER
STAGES
18 THRU
23
VSS = PIN 8
VDD = PIN 16
17
24
LOGIC DIAGRAM
MC14536B
6359

(For Circuit Diagram See Figure 11 In Application)
8.0
100
4.0
0
10 V
4.0
8.0
5.0 V
12
RTC = 56 k,
C = 1000 pF
16
55
25
* Device Only.
VDD = 10 V
50
VDD = 15 V
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
TA, AMBIENT TEMPERATURE (C)*
100
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
10
5.0
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
2.0
1.0
0.5
0.2
0.1
1.0 k
125
10 k
100 k
0.001
0.01
C, CAPACITANCE (F)
0.0001
1.0 M
0.1

MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 RX CX 0.85
WHERE R IS IN k, CX IN pF.
10
t W, PULSE WIDTH ( s)
100
RX = 100 k
50 k
1.0
10 k
5 k
10

tW = 0.00247 RX CX 0.85
RX = 100 k
50 k
1.0
10 k
5 k
TA = 25C
VDD = 5 V
TA = 25C
VDD = 10 V
0.1
0.1
1.0
10
100
1000
Figure 3. Typical CX versus Pulse Width

@ VDD = 5.0 V
1.0
10
100
1000

@ VDD = 10 V
100
10

tW = 0.00247 RX CX 0.85
RX = 100 k
50 k
1.0
10 k
5 k
TA = 25C
VDD = 15 V
0.1
1.0
10
100
1000

@ VDD = 15 V
MC14536B
6360
VDD
500 F
0.01 F
CERAMIC
ID
SET
RESET OUT 1
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
PULSE
GENERATOR
A
B
C
D
CL
VDD
CL
DECODE
OUT
PULSE
GENERATOR
CL
VSS
20 ns
20 ns
20 ns
20 ns
50%
IN1
tWL
SET
OUT 1
RESET
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
A
B
C
DECODE
OUT
D
OUT
tWH
90%
10%
tPLH
50%
tTLH
tTHL
tPHL
CL
VSS
90%
50%
10%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test

Circuit and Waveform
VDD
Test function (Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages.
This test function divides the counter into three 8stage
sections and 255 counts are loaded in each of the 8stage
sections in parallel. All flipflops are now at a 1. The counter is now returned to the normal 24stages in series configuration. One more pulse is entered into In1 which will cause
the counter to ripple from an all 1 state to an all 0 state.
PULSE
GENERATOR
SET
RESET OUT 1
8BYPASS
IN1
C INH
MONO IN OUT
2
OSC INH
A
B
C
D
DECODE
OUT
VSS
Figure 8. Functional Test Circuit

Inputs
Outputs
Comments
g are in Reset mode.
All 24 stages
In1
Set
Reset
8Bypass
Decade Out
Q1 thru Q24
Counter is in three 8 stage sections in parallel mode.
First 1 to 0 transition of clock.
1
0
The 255 1 to 0 transition.
Counter converted back to 24 stages in series mode.

Set and Reset must be connected together and simultaneously
go from 1 to 0.
In1 Switches to a 1.
Counter Ripples from an all 1 state to an all 0 state.
255 1 to 0 transitions are clocked in the counter.
MC14536B
6361
+V
16
6
8BYPASS
VDD
OUT 1
A
10 B
11 C
12
2
14
15
1
PULSE
GEN.
7
3
PULSE
GEN.
CLOCK
D
RESET
OUT 2
DECODE OUT
13
OSC INH
MONOIN
SET
CLOCK INH
IN1
VSS
8
IN1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20divided
output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions
(Divideby2 Configured)
MC14536B
6362
+V
6
RX
2
1
7
15
14
3
CLOCK
CX
OUT 1
A
10 B
11 C
12
PULSE
GEN.
8BYPASS
16
VDD
4
D
RESET
OUT 2
DECODE OUT
13
SET
CLOCK INH
MONOIN
CLOCK INH
IN1
VSS
8
IN1
RESET
*tw .00247 RX CX0.85
DECODE OUT
*tw
tw in sec
RX in k
CX in pF
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chips internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the MonoIn input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,

and Output Monostable to Achieve a Pulse Output
MC14536B
6363
+V
RS
16
6
8BYPASS
VDD
9
A
10 B
11 C
12
PULSE
GEN.
2
14
15
1
7
3
OUT 1
4
C
RTC
D
OUT 2
RESET
SET
CLOCK INH
MONOIN
CLOCK INH
IN1
VSS
8
DECODE OUT 13
RESET
OUT 1
OUT 2
fosc
DECODE OUT
POWER UP
tw
^ 2.3 R1tc C
Rs Rtc
F = Hz
R = Ohms
C = FARADS
NOTE: This circuit is designed to use the onchip oscillation function. The oscillator frequency is determined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the OscInh input, the oscillator is
disabled. This puts the device in a lowcurrent standby condition. The rising edge of the Reset pulse
will cause the output to go low. This in turn causes OscInh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
for 2n/2 of the oscillators period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using OnChip RC Oscillator and

Reset Input to Initiate Time Interval
MC14536B
6364
MOTOROLA
MC14538B
Dual Precision
Retriggerable/Resettable
L SUFFIX
CERAMIC
CASE 620
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an
accurate output pulse over a wide range of widths, the duration and accuracy
of which are determined by the external timing components, CX and RX.
Unlimited Rise and Fall Time Allowed on the A Trigger Input
Pulse Width Range = 10 s to 10 s
Latched Trigger Inputs
Separate Latched Reset Inputs
3.0 Vdc to 18 Vdc Operational Limits
Triggerable from Positive (A Input) or NegativeGoing Edge (BInput)
Pinforpin Compatible with MC14528B and CD4528B (CD4098)
Use the MC54/74HC4538A for Pulse Widths Less Than 10 s with
Supplies Up to 6 V.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
*MC14XXXBDW

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
CX
1
4
5
Q1
Q1
RESET
3
CX
15
100 ns
MC14528B
MC14536B
MC14538B
1 s
10 s
100 s
1 ms
10 ms
100 ms
12
1s
11
10 s
23 HR
5 MIN.
MC14541B
MC4538A*
*LIMITED OPERATING VOLTAGE (2 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
VDD
ONESHOT SELECTION GUIDE
RX
RX
VDD
14
A
Q2
B
Q2
RESET
10
9
13
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
* Consult factory for possible D suffix SOIC
Case 751B.
MC14538B
6365

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current, Pin 2 or 14
Iin
15
0.05
0.00001
0.05
0.5
Adc
Input Current, Other Inputs
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance, Pin 2 or 14
Cin
25
pF
Input Capacitance, Other Inputs

(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
Q = Low, Q = High
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Quiescent Current, Active State

(Both) (Per Package)
Q = High, Q = Low
IDD
5.0
10
15
2.0
2.0
2.0
0.04
0.08
0.13
0.20
0.45
0.70
2.0
2.0
2.0
mAdc
IT
5.0
10
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink

external load capacitance (CL) and
at external timing network (RX, CX)
mAdc
IT = (3.5 x 102) RXCXf + 4CXf + 1 x 105 CLf

where: IT in A (one monostable switching only),
where: CX in F, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
Adc
be left open.
MC14538B
6366

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL

A or B to Q or Q
tPLH,
tPHL
All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
300
150
100
600
300
220
5.0
10
15
250
125
95
500
250
190
5
10
15
15
5
4
B Input
5
10
15
300
1.2
0.4
1.0
0.1
0.05
ms
A Input
5
10
15
Reset to Q or Q
Input Rise and Fall Times
Reset
Input Pulse Width

A, B, or Reset
ns
tr, tf
No Limit
tWH,
tWL
5.0
10
15
170
90
80
85
45
40
ns
Retrigger Time
trr
5.0
10
15
0
0
0
ns

Refer to Figures 8 and 9
CX = 0.002 F, RX = 100 k
s
5.0
10
15
198
200
202
210
212
214
230
232
234
CX = 0.1 F, RX = 100 k
5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
CX = 10 F, RX = 100 k
5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
5.0
10
15
1.0
1.0
1.0
5.0
5.0
5.0
Pulse Width Match between circuits in

the same package.
CX = 0.1 F, RX = 100 k
100
[(T1 T2)/T1]
OPERATING CONDITIONS
External Timing Resistance
RX
5.0
External Timing Capacitance
CX
No
Limit
* The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout
and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 M..
If CX > 15 F, use discharge protection diode per Fig. 11.
MC14538B
6367
VDD
VDD
P1
RX
2 (14)
CX
+
C1
Vref1
1 (15)
Vref2
ENABLE
ENABLE
+
C2
N1
VSS
4 (12)
6 (10)
R
Q
OUTPUT
LATCH
S
Q
7 (9)
CONTROL
5 (11)
B
RESET
QR
S
3 (13)
RESET LATCH
NOTE: Pins 1, 8 and 15 must

be externally grounded
QR
R
Figure 1. Logic Diagram

(1/2 of DevIce Shown)
VDD
500 pF
0.1 F
CERAMIC
ID
RX
CX
RX
VSS
Vin
CX
VSS
CX/RX
A
B
RESET
20 ns
CL
VDD
90%
CL
CL
20 ns
10%
Vin
0V
CL
RESET
VSS
VDD
INPUT CONNECTIONS
RX
CX
RX
VSS
CX
A
B
PULSE
GENERATOR
RESET
PULSE
GENERATOR
VSS
CX/RX
PULSE
GENERATOR
CL
CL
CL
Q
CL
RESET
VSS
Characteristics
Reset
tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL
VDD
PG1
VDD
tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL
VDD
VSS
PG2
tPLH(R), tPHL(R),
tWH, tWL
PG3
PG1
PG2
* CL = 50 pF
* Includes capacitance of probes,

wiring, and fixture parasitic.
PG1 =
NOTE: Switching test waveforms

for PG1, PG2, PG3 are shown
In Figure 4.
PG2 =
PG3 =
Figure 3. Switching Test Circuit
MC14538B
6368
90%
10%
tTHL
50%
A
tTLH
tWH
50%
tTHL
90%
10%
B
50%
VDD
tTLH
VDD
tWL
tTHL
90%
10%
RESET
tPLH
tPLH
50%
50%
tTLH
90%
10%
50%
Q
tPHL
tTHL
50%
90%
10%
50%
VDD
50%
tWL
trr
tPHL
50%
tTHL
tTLH
tPHL
tPHL
tPLH
50%
50%
TA = 25C
RX = 100 k
CX = 0.1 F
NORMALIZED PULSE WIDTH CHANGE

WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
Figure 4. Switching Test Waveforms
0% POINT PULSE WIDTH

VDD = 5.0 V, T = 9.8 ms
VDD = 10 V, T = 10 ms
VDD = 15 V, T = 10.2 ms
1.0
0.8
0.6
0.4
0.2
0
4 2
0
2
4
T, OUTPUT PULSE WIDTH (%)
RX = 100 k
CX = 0.1 F
2
1
0
1
2
Figure 5. Typical Normalized Distribution

of Units for Output Pulse Width
8
9
10
11
12
VDD, SUPPLY VOLTAGE (VOLTS)
TOTAL SUPPLY CURRENT ( A)
15
FUNCTION TABLE
Inputs
RX = 100 k, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY
Reset
VDD = 15 V
5.0 V
10
10 V
1.0
0.1
0.001
14
Figure 6. Typical Pulse Width Variation as

a Function of Supply Voltage VDD
1000
100
13
0.1
1.0
10
H
H
H
H
H
H
L
Outputs
B
H
L
Not Triggered
Not Triggered
L, H,
L
H
L, H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
100
OUTPUT DUTY CYCLE (%)
Figure 7. Typical Total Supply Current

versus Output Duty Cycle
MC14538B
6369
VDD = 15 V
VDD = 10 V
0
VDD = 5 V
TYPICAL NORMALIZED ERROR

WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
TYPICAL NORMALIZED ERROR

WITH RESPECT TO 25C VALUE AT VDD = 10 V (%)
RX = 100 k
CX = 0.1 F
3.0
2.0
1.0
0
1.0
RX = 100 k
CX = .002 F
VDD = 15 V
VDD = 10 V
2.0
VDD = 5.0 V
3.0
60 40
20
0
20
40
60
80 100
120
140
60 40
Figure 8. Typical Error of Pulse Width

Equation versus Temperature
20
0
20
40
60
80 100
120
140
Figure 9. Typical Error of Pulse Width

Equation versus Temperature
THEORY OF OPERATION
1
A
2
B
5
RESET
Vref 2
Vref 2
CX/RX
Vref 1
Vref 2
Vref 2
Vref 1
Vref 1
Vref 1
Q
T
Positive edge trigger
Positive edge retrigger (pulse lengthening)
Negative edge trigger
Positive edge retrigger (pulse lengthening)
Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION
The block diagram of the MC14538B is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to V DD. When the trigger input A goes from V SS to V DD
(while inputs B and Reset are held to V DD) a valid trigger is
recognized, which turns on comparator C1 and Nchannel
transistor N1 . At the same time the output latch is set. With
transistor N1 on, the capacitor CX rapidly discharges toward
V SS until V ref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
MC14538B
6370
comparator C2 turns on. With transistor N1 off, the capacitor

CX begins to charge through the timing resistor, RX, toward
V DD. When the voltage across CX equals Vref 2, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 . This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, CX is fully charged to VDD causing
the current through resistor RX to be zero. Both comparators
are off with total device current due only to reverse junction
leakages. An added feature of the MC14538B is that the output latch is set via the input trigger without regard to the
capacitor voltage. Thus, propagation delay from trigger to Q
is independent of the value of CX, RX, or the duty cycle of the
input waveform.
RETRIGGER OPERATION
The MC14538B is retriggered if a valid trigger occurs followed by another valid trigger before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated ,
the voltage at C X /R X will again drop to V ref 1 before
progressing along the RC charging curve toward VDD. The Q
output will remain high until time T, after the last valid retrigger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 . When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level is

detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width specification.
POWERDOWN CONSIDERATIONS
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
discharge from V DD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
V DD supply must not be faster than (V DD). (C) / (10 mA). For
example, if V DD = 10 V and CX = 10 F, the V DD supply
should discharge no faster than (10 V) x (10 F) / (10 mA) =
10 ms. This is normally not a problem since power supplies
are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of V DD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11.
Dx
PIN ASSIGNMENT
Cx
Rx VDD
VSS
VDD
Q
Q
RESET
VSS
16
VDD
CX/RXA
15
VSS
RESET A
14
CX/RXB
AA
13
RESET B
BA
12
AB
QA
11
BB
QA
10
QB
VSS
QB
Figure 11. Use of a Diode to Limit

Power Down Current Surge
MC14538B
6371
CX
CX
RX
RX
VDD
VDD
RISINGEDGE
A
TRIGGER
B
RISINGEDGE
A
TRIGGER
B
Q
Q
B = VDD
RESET = VDD
CX
RESET = VDD
CX
VDD
RX
VDD
A = VSS
A
B
Q
B
RX
FALLINGEDGE
TRIGGER
FALLINGEDGE
TRIGGER
RESET = VDD
RESET = VDD
Figure 12. Retriggerable

Figure 13. NonRetriggerable

NC
A
B
NC
NC
CD
VDD
VDD
Figure 14. Connection of Unused Sections
MC14538B
6372
MOTOROLA
MC14539B
Dual 4-Channel Data
Selector/Multiplexer
L SUFFIX
CERAMIC
CASE 620
The MC14539B data selector/multiplexer is constructed with MOS

monolithic structure. The circuit consists of two sections of four inputs each.
One input from each section is selected by the address inputs A and B. A
high on the Strobe input will cause the output to remain low.
This device finds primary application in signal multiplexing functions. It
permits multiplexing from Nlines to Iline, and can also perform parallelto
serial conversion. The Strobe input allows cascading of nlines to nlines.
P SUFFIX
PLASTIC
CASE 648


Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
14
2
1
6
5
4
3
A
B
ST
X0
X1
X2
X3
15
10
11
12
13
A
B
ST
Y0
Y1
Y2
Y3
TRUTH TABLE
Address
Inputs
Data Inputs
X3
Y3
ST, ST
Outputs
Z, W
X
0
0
0
0
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
1
X
X
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
1
0
1
X2
Y2
X1
Y1
X0
Y0
VDD = PIN 16
VSS = PIN 8
X = Dont Care
MC14539B
6373

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14539B
6374

Characteristic
Symbol

tTLH,
tTHL

X, Y Input to Output
tPLH,
tPHL
A Input to Output
tPLH

tPHL
Strobe Input to Output

VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
210
90
70
420
180
140
5.0
10
15
225
110
85
450
220
170
5.0
10
15
245
115
90
490
230
180
5.0
10
15
145
75
60
290
150
120
ns
tPLH,
tPHL
ns
ns
VDD
PULSE
GENERATOR
20 ns
A
B
ST
X0
X1
X2
X3
ST
Y0
Y1
Y2
Y3
20 ns
Z
INPUT
CL
OUTPUT
(TEST 1)
tPLH
OUTPUT
(TESTS 2 AND 3)
VSS
tPHL
tTLH
tTHL
tTHL
tPHL
tTLH
tPLH
INPUT CONNECTIONS FOR tTLH, tTHL, tPHL, tPLH

Test
Strobe
X0
1
2
3
Gnd
P.G.
Gnd
Gnd
Gnd
P.G.
P.G.
VDD
VDD
MC14539B
6375
VDD
500 F
PULSE
GENERATOR
0.01 F
CERAMIC
ID
A
B
ST
X0
X1
X2
X3
ST
Y0
Y1
Y2
Y3
20 ns
20 ns
Vin
CL
VDD
90%
50%
10%
VSS
50% DUTY CYCLE

W
CL
VSS
LOGIC DIAGRAM
B
A
X0
X1
X2
X3
Y0
Y1
2
14
ST
PIN ASSIGNMENT
5
7
4
10
Y3
16
VDD
15
ST
X3
14
X2
13
Y3
X1
12
Y2
X0
11
Y1
10
Y0
VSS
11
9
Y2
ST
12
13
MC14539B
6376
15
ST
MOTOROLA
MC14541B
Programmable Timer
L SUFFIX
CERAMIC
CASE 620
The MC14541B programmable timer consists of a 16stage binary

counter, an integrated oscillator for use with an external capacitor and two
resistors, an automatic poweron reset circuit, and output control logic.
Timing is initialized by turning on power, whereupon the poweron reset is
enabled and initializes the counter, within the specified VDD range. With the
power already on, an external reset pulse can be applied. Upon release of
the initial reset command, the oscillator will oscillate with a frequency
determined by the external RC network. The 16stage counter divides the
oscillator frequency (fosc) with the nth stage frequency being fosc/2n.
Available Outputs 28, 210, 213 or 216
Increments on Positive Edge Clock Transitions
Builtin Low Power RC Oscillator ( 2% accuracy over temperature
range and 20% supply and 3% over processing at < 10 kHz)
Oscillator May Be Bypassed if External Clock Is Available (Apply
external clock to Pin 3)
External Master Reset Totally Independent of Automatic Reset
Operation
Operates as 2n Frequency Divider or Single Transition Timer
Q/Q Select Provides Output Logic Level Flexibility
Reset (auto or master) Disables Oscillator During Resetting to Provide
No Active Power Dissipation
Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise
and Fall Times
Automatic Reset Initializes All Counters On Power Up
Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Disabled (Pin 5 = VDD)
= 8.5 Vdc to 18 Vdc with Auto Reset
Enabled (Pin 5 = VSS)

Symbol
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
10
mA
Iout
45
mA
PD
Tstg
Storage Temperature
VDD
Vin, Vout
Iin
TL
Parameter
DC Supply Voltage
500
mW
65 to + 150
_C
260
_C
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Rtc
14
VDD
Ctc
13
RS
12
NC
11
NC
AR
10
MODE
MR
Q/Q SEL
VSS
NC = NO CONNECTION
MC14541B
6377

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
10
15
7.96
4.19
16.3
6.42
3.38
13.2
12.83
6.75
26.33
4.49
2.37
9.24
IOL
5.0
10
15
1.93
4.96
19.3
1.56
4.0
15.6
3.12
8.0
31.2
1.09
2.8
10.9
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Pin 5 is High)
Auto Reset Disabled
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
Auto Reset Quiescent Current

(Pin 5 is low)
IDDR
10
15
250
500
30
82
250
500
1500
2000
Adc
Supply Current**
(Dynamic plus Quiescent)
ID
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
ID = (0.4 A/kHz) f + IDD

Adc
When using the on chip oscillator the total supply current (in Adc) becomes: IT = ID + 2 Ctc VDD f x 103 where ID is in A, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during poweron with automatic reset enabled is typically 50 A @ VDD = 10 Vdc.
be left open.
MC14541B
6378

Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
3.5
1.25
0.9
10.5
3.8
2.9
5.0
10
15
6.0
3.5
2.5
18
10
7.5
tWH(cl)
5.0
10
15
900
300
225
300
100
85
ns
fcl
5.0
10
15
1.5
4.0
6.0
0.75
2.0
3.0
MHz
tWH(R)
5.0
10
15
900
300
225
300
100
85
ns
trem
5.0
10
15
420
200
200
210
100
100
ns

tTLH,
tTHL
Propagation Delay, Clock to Q (28 Output)

Propagation Delay, Clock to Q (216 Output)
tPLH
tPHL
tPHL
tPLH
Clock Pulse Width
Clock Pulse Frequency (50% Duty Cycle)
MR Pulse Width
Unit
ns
VDD
PULSE
GENERATOR
VDD
PULSE
GENERATOR
RS
AR
Q/Q SELECT
MODE
RS
AR
Q/Q SELECT
MODE
A
B
MR
A
B
MR
CL
VSS
20 ns
20 ns
RS
90% 50%
10%
50%
DUTY CYCLE

and Waveform
CL
VSS
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

20 ns
20 ns
90% 50%
10%
50%
tPHL
tPLH
50%
Q
tTLH
90%
10%
50%
tTHL

and Waveforms
MC14541B
6379
EXPANDED BLOCK DIAGRAM

A 12
B 13
1 OF 4
MUX
Rtc 1
Ctc 2
OSC
RS 3
RESET
AUTO RESET
5
8 Q
210 213 216

C 8STAGE
COUNTER
RESET
8STAGE 8
2
C
COUNTER
RESET
POWERON
RESET
6
MASTER RESET
10
MODE
9
Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE
TRUTH TABLE
State
Number of
Counter Stages
n
13
8192
10
1024
256
16
65536
Count
2n
Pin
Auto Reset Operating
Auto Reset Disabled
Master Reset, 6
Timer Operational
Master Reset On
Q / Q,
Output Initially Low

After Reset
Output Initially High

After Reset
Mode,
10
Single Cycle Mode
Recycle Mode
Auto Reset,
TO CLOCK
CIRCUIT
INTERNAL
RESET
2
1
Ctc
RS
RTC
Figure 3. Oscillator Circuit Using RC Configuration
MC14541B
6380

8.0
100
VDD = 15 V
0
10 V
4.0
8.0
5.0 V
12
RTC = 56 k,
C = 1000 pF
16
55
25
VDD = 10 V
50
4.0
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0
25
50
75
100
125
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)
20
10
5.0
2.0
1.0
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.5
0.2
0.1
1.0 k
0.0001
10 k
100 k
1.0 m
0.001
0.01
C, CAPACITANCE (F)
0.1

Function of Rtc and Ctc
With Auto Reset pin set to a 0 the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a
1. Both types of reset will result in synchronously resetting
all counter stages independent of counter state. Auto Reset
pin when set to a 1 provides a low power operation.
The RC oscillator as shown in Figure 3 will oscillate with a
frequency determined by the external RC network i.e.,
f=
1
2.3 RtcCtc
if (1 kHz
v f v 100 kHz)
and RS 2 Rtc
where RS 10 k
The time select inputs (A and B) provide a twobit address
to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is 1, 216 is selected for both states of B. However,
when B is 0, normal counting is interrupted and the 9th

counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a 0 the Q output is a 0, correspondingly when Q/Q select pin is set to a 1 the Q output is
a 1.
When the mode control pin is set to a 1, the selected
count is continually transmitted to the output. But, with mode
pin 0 and after a reset condition the RS flipflop (see Expanded Block Diagram) resets, counting commences, and
after 2n1 counts the RS flipflop sets which causes the output to change state. Hence, after another 2n1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
DIGITAL TIMER APPLICATION

Rtc
Ctc
NC
RS
AR
MR
INPUT
14
13
VDD
B
12
11
10
N.C.
MODE
Q/Q
VDD
OUTPUT
tMR
When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and remains low until another input pulse is received.
This one shot is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy is
needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up, during which time Q output will be high.
t + tMR
MC14541B
6381
MOTOROLA
MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
L SUFFIX
CERAMIC
CASE 620
The MC14543B BCDtoseven segment latch/decoder/driver is designed

for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode devices. The circuit provides the
functions of a 4bit storage latch and an 8421 BCDtoseven segment
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as
lightemitting diode (LED), incandescent, gas discharge, and fluorescent
readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display driver,

Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Range
PinforPin Replacement for CD4056A (with Pin 7 Tied to VSS).
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Outputs
LD BI Ph* D C
Symbol
Value
Unit
VDD
0.5 to + 18
Vin
0.5 to VDD + 0.5
X X
X X 0 0 0 0 0 0 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
2
3
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
Blank
Blank
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
Iin
10
mA
55 to + 125
_C
X X
PD
500
mW
Tstg
65 to + 150
_C
10
mA
Maximum Continuous Output Power*

(Source or Sink) per Output
POHmax
POLmax
70
mW
* POHmax = IOH (VOH VDD) and POLmax = IOL (VOL VSS)

MC14543B
6382
Blank
TA
IOHmax
IOLmax
Display
Maximum Continuous Output Drive

Current (Source or Sink) per Output
B A a b c d e f g
DC Input Current per Pin
Plastic
Ceramic
SOIC
TRUTH TABLE
MAXIMUM RATINGS* (Voltages referenced to VSS)

DC Supply Voltage
D SUFFIX
SOIC
CASE 751B
Inputs
Rating
P SUFFIX
PLASTIC
CASE 648
X X
**
Inverse of Output
Combinations
Above
**
Display
as above
X = Dont care
= Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when
LD = 1

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
10.1
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
10.1
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 0.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 9.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

Adc

Noise Margin for both 1 and 0 level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency.
MC14543B
6383

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 12.5 ns
tTHL
TurnOff Delay Time

tPLH = (0.66 ns/pF) CL + 217 ns
tPLH
TurnOn Delay Time

tPHL = (0.66 ns/pF) CL + 172 ns
tPHL
VDD
Min
Typ
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
605
250
185
1210
500
370
5.0
10
15
505
205
155
1650
660
495
Unit
ns
ns
ns
ns
Setup Time
tsu
5.0
10
15
350
450
500
ns
Hold Time
th
5.0
10
15
40
30
20
ns
tWH
5.0
10
15
250
100
80
ns
Latch Disable Pulse Width (Strobing Data)
125
50
40
LOGIC DIAGRAM
BI 7
VDD = PIN 16
VSS = PIN 8
9 a
A 5
10 b
11 c
B 3
12 d
13 e
C 2
15 f
14 g
D 4
LD 1
MC14543B
6384
PHASE 6
24
VDD = 15 Vdc
VDD = 5.0 Vdc
POHmax = 70 mWdc
IOL , SINK CURRENT (mAdc)
IOH, SOURCE CURRENT (mAdc)
6.0
VDD = 10 Vdc
12
18
18
VDD = 10 Vdc
12
6.0
VDD = 15 Vdc
24
16
POLmax = 70 mWdc
VDD = 5.0 Vdc

VSS = 0 Vdc
VSS = 0 Vdc
12
8.0
4.0
(VOH VDD), SOURCE DEVICE VOLTAGE (Vdc)
4.0
8.0
12
(VOL VSS), SINK DEVICE VOLTAGE (Vdc)

Characteristics
16

Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns
20 ns
90%
10%
VDD
50%
VSS
tPLH
tPHL
90%
50%
VOH
10%
VOL
tTLH
tTHL
(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
90%
10%
LD
Inputs BI and Ph low, and Inputs D and LD high.
VSS
tsu
C
VDD
50%
th
50%
50%
VDD
VSS

20 ns
A, B, AND C
10%
20 ns
90%
50%
1
2f
50% DUTY CYCLE
ANY OUTPUT
VOH
VDD
VSS
VOH
VOL

Signal Waveforms
VOL
(c) Data DCBA strobed into latches

LD
VDD
50%
VSS
tWH
MC14543B
6385

MC14543B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
ONE OF SEVEN SEGMENTS

COMMON
BACKPLANE
MC14543B
OUTPUT
Ph
SQUARE WAVE
(VSS TO VDD)
VSS
COMMON
CATHODE LED
COMMON
ANODE LED
MC14543B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
VDD
MC14543B
OUTPUT
Ph
MC14543B
OUTPUT
Ph
VSS
VDD
NOTE: Bipolar transistors may be added for gain (for VDD
v 10 V or Iout 10 mA).
PIN ASSIGNMENT
LD
16
VDD
15
14
13
12
PH
11
BI
10
VSS
VSS
CONNECTIONS TO SEGMENTS
a
f
VDD = PIN 16
VSS = PIN 8
DISPLAY
MC14543B
6386
c
d
MOTOROLA
MC14544B
Latch/Decoder/Driver for
Liquid Crystals
L SUFFIX
CERAMIC
CASE 726
CMOS MSI (LowPower Complementary MOS)

The MC14544B BCDtoseven segment latch/decoder/driver is designed
for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode devices. The circuit provides the
functions of a 4bit storage latch and an 8421 BCDtoseven segment
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display, and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to the
segments of the LC readout. The Ripple Blanking Input (RBI) and the Ripple
Blanking Output (RBO) can be used to suppress either leading or trailing
zeroes.
For other types of readouts, such as lightemitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display driver,

Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Capability for Suppression of Nonsignificant zero
Range
P SUFFIX
PLASTIC
CASE 707
MC14XXXBCP
MC14XXXBCL
PIN ASSIGNMENT
LD
18
VDD
17
16
15
14
PH
13
BI
12
RBO
11
VSS
10
RBI

Rating
DC Supply Voltage
Symbol
Value
Unit
VDD
0.5 to + 18
Vin
0.5 to VDD + 0.5
DC Input Current per Pin
Iin
10
mAdc
TA
55 to + 125
_C
PD
500
mW
Tstg
65 to + 150
_C

Current (Source or Sink) per Output
IOHmax
IOLmax
10
mAdc
Maximum Continuous Output Power*

(Source or Sink) per Output
POHmax
POLmax
70
mW
* POHmax = IOH (VOH VDD) and POLmax = IOL (VOL VSS)

Plastic
Ceramic
a
f
b
c
DISPLAY

to the range VSS
(Vin or Vout)
VDD.
MC14544B
6387

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
10.1
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
10.1
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage #
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 0.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 9.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

IT = (4.7 A/kHz )f + IDD
Adc

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
MC14544B
6388

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 12.5 ns
tTHL
TurnOff Delay Time

tPLH = (0.66 ns/pF) CL + 217 ns
tPLH
TurnOn Delay Time

tPHL = (0.66 ns/pF) CL + 172 ns
tPHL
VDD
Min
Typ
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
605
250
185
1210
500
370
5.0
10
15
505
205
155
1650
660
495
Unit
ns
ns
ns
ns
Setup Time
tsu
5.0
10
15
0
0
0
40
15
10
ns
Hold Time
th
5.0
10
15
80
30
20
40
15
10
ns
tWH
5.0
10
15
250
100
80
125
50
40
ns
Latch Disable Pulse Width (Strobing Data)
LOGIC DIAGRAM
BI 7
VDD = PIN 18
VSS = PIN 9
11 a
A 5
12 b
13 c
B 3
14 d
15 e
C 2
17 f
16 g
D 4
LD 1
RBI 10
8 RBO
6
PHASE
MC14544B
6389

MC14544B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
ONE OF SEVEN SEGMENTS

COMMON
BACKPLANE
MC14544B
OUTPUT
Ph
SQUARE WAVE
(VSS TO VDD)
VSS
COMMON
CATHODE LED
COMMON
ANODE LED
MC14544B
OUTPUT
Ph
APPROPRIATE
VOLTAGE
VDD
MC14544B
OUTPUT
Ph
MC14544B
OUTPUT
Ph
VSS
VDD
NOTE: Bipolar transistors may be added for gain (for VDD
v 10 V or Iout 10 mA).
VSS
TRUTH TABLE
Inputs
Outputs
RBI
LD
BI
Ph*
RBO
Display
Blank
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Blank
0
X
X
X
X
X
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
2
3
4
5
X
X
X
X
X
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
6
7
8
9
Blank
X
X
X
X
X
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
Bl k
Blank
**
**
Inverse of Output
Combinations Above
Display
as above
MC14544B
6390
X = Dont Care
Above Combinations
* For liquid crystal readouts, apply a square wave
to Ph. For common cathode LED readouts, select
Ph = 0. For common anode LED readouts, select
Ph = 1.
** Depends upon the BCD Code previously applied
when LD = 1.
# RBO = RBI (A B C D)
24
VDD = 15 Vdc
VDD = 5.0 Vdc
POHmax = 70 mWdc
IOL , SINK CURRENT (mAdc)
IOH, SOURCE CURRENT (mAdc)
6.0
VDD = 10 Vdc
12
18
18
VDD = 10 Vdc
12
6.0
VDD = 15 Vdc
24
16
POLmax = 70 mWdc
VDD = 5.0 Vdc

VSS = 0 Vdc
VSS = 0 Vdc
12
8.0
4.0
(VOH VDD), SOURCE DEVICE VOLTAGE (Vdc)
4.0
8.0
12
(VOL VSS), SINK DEVICE VOLTAGE (Vdc)

Characteristics
16

Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

20 ns
20 ns
90%
10%
VDD
50%
VSS
tPLH
tPHL
90%
50%
VOH
10%
VOL
tTLH
tTHL
(b) Inputs D, Ph, and BI low, and Inputs A and B high.

20 ns
90%
10%
LD
VSS
tsu
Inputs BI and Ph low, and Inputs D and LD high.
VDD
50%
th
50%
50%
VDD
VSS

20 ns
A, B, AND C
10%
20 ns
90%
50%
1
2f
50% DUTY CYCLE
ANY OUTPUT
VOH
VDD
VSS
VOH
VOL

Signal Waveforms
VOL
(c) Data DCBA strobed into latches

LD
VDD
50%
VSS
tWH
MC14544B
6391
TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION
DISPLAYS
a g
RBI
RBO
VDD (1) D C B A
CONNECT TO
INPUT
CODE
MC14544B
0 0 0 0
(0)
a g
RBI
RBO
1
D C B A
MC14544B
0 0 0 0
(0)
a g
RBI
RBO
1
D C B A
MC14544B
0 1 0 1
(5)
a g
RBI
RBO
D C B A
a g
RBI
RBO
D C B A
MC14544B
0 0 0 0
(0)
MC14544B
0 0 0 1
(1)
a g
RBI
RBO
D C B A
MC14544B
0 0 1 1
(3)
TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
INPUT
CODE
MC14544B
6392
a g
RBI
RBO
D C B A
MC14544B
0 1 0 1
(5)
a g
RBI
RBO
0
D C B A
MC14544B
0 0 0 0
(0)
a g
RBI
RBO
0
D C B A
MC14544B
0 0 0 1
(1)
a g
RBI
RBO
D C B A
MC14544B
0 0 1 1
(3)
a g
RBI
RBO
D C B A
MC14544B
0 0 0 0
(0)
a g CONNECT TO
RBI
RBO
D C B A VDD (1)
MC14544B
0 0 0 0
(0)
INPUT
CODE
MOTOROLA
MC14547B
High Current BCD-to-Seven
Segment Decoder/Driver
L SUFFIX
CERAMIC
CASE 620
The MC14547 BCDtoseven segment decoder/driver is constructed with

complementary MOS (CMOS) enhancement mode devices and NPN bipolar
output drivers in a single monolithic structure. The circuit provides the
functions of an 8421 BCDtoseven segment decoder with high output drive
capability. Blanking (BI), can be used to turn off or pulse modulate the
brightness of the display. The MC14547 can drive sevensegment
lightemitting diodes (LED), incandescent, fluorescent or gas discharge
readouts either directly or indirectly.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
High Current Sourcing Outputs (Up to 65 mA)

Supply Voltage Range = + 3.0 V to + 18 V
Blanking Input
Readout Blanking on All Illegal Combinations
Multiplexing Capability
Capable of Driving Two LowPower TTL Loads, One LowPower
Schottky TTL Load or Two HTL Loads over the Rated Temperature
Range
Use MC14511B for Applications Requiring Data Latches
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MAXIMUM RATINGS* (Voltages referenced to VSS, Pin 8)

Rating
DC Supply Voltage
Symbol
Plastic
Ceramic
SOIC
16
VDD
15
NC
14
BI
13
NC
12
Value
Unit
11
VDD
0.5 to + 18
10
Vin
0.5 to VDD + 0.5
VSS
TA
55 to + 125
_C
Tstg
65 to + 150
_C
IOHmax
65
mA
PD
1200*

Current (Source) per Output
Maximum Continuous Power Dissipation
b
c
a
g
DISPLAY
mW
TRUTH TABLE
* See Power Derating Curve Figure 1.
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to
the range VSS (Vin or Vout) VDD.
Due to the sourcing capability of this circuit, damage can occur to the
device if VDD is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
level (e.g., either VSS or VDD).
Inputs
Outputs
BI
D C B A a b c d e f g
Display
X X X X 0 0 0 0 0 0 0
Blank
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
2
3
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
Blank
Blank
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
X = Dont care
MC14547B
6393

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.1
9.1
14.1
4.4
9.4
14.4
4.6
9.6
14.6
4.3
9.3
14.4
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
4.0
3.8
3.1
4.2
4.1
3.9
3.7
3.2
4.3
4.3
4.2
4.0
3.7
4.3
4.0
3.0
Vin = 0 or VDD
Input Voltage #
0 Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
Output Drive Voltage
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 20 mA)
(IOH = 40 mA)
(IOH = 65 mA)
55_C
VDD
Vdc
VIL
VIH
Vdc
VOH
Source
Vdc
Vdc
(IOH = 5.0 mA)

(IOH = 10 mA)
(IOH = 20 mA)
(IOH = 40 mA)
(IOH = 65 mA)
10
9.1
8.8
8.4
9.2
9.1
9.0
8.9
8.5
9.3
9.3
9.2
9.0
8.8
9.3
9.2
8.1
Vdc
(IOH = 5.0 mA)

(IOH = 10 mA)
(IOH = 20 mA)
(IOH = 40 mA)
(IOH = 65 mA)
15
14
13.8
13.5
14.2
14.1
14.0
13.8
13.5
14.3
14.3
14.2
14.0
13.7
14.4
14.2
13.3
Vdc
5.0
10
15
0.32
0.80
2.10
0.26
0.65
1.7
0.44
1.13
4.4
0.18
0.45
1.2

(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
Sink
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15

Adc
#Noise immunity specified for worst input combination.

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
MC14547B
6394

Characteristic
Symbol
VDD
Vdc
Min
Typ
Max
Unit
Output Rise Time
tTLH
5.0
10
15
40
40
40
80
80
80
ns
Output Fall Time
tTHL
5.0
10
15
125
75
70
250
150
140
ns
tPLH
5.0
10
15
750
300
200
1500
600
400
ns
tPHL
5.0
10
15
750
300
200
1500
600
400
tPLH
5.0
10
15
750
300
200
1500
600
400
tPHL
5.0
10
15
500
250
170
1000
500
340
Blank Propagation Delay Time
ns
MC14547B
6395
LOGIC DIAGRAM
BI 4
A 7
13 a
12 b
B 1
11 c
10 d
C 2
9 e
15 f
D 6
14 g
PD, MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE
1200
1000
(L) CERAMIC
800
600
(P) PDIP
400
410 mW (L)
(D) SOIC
230 mW (P)
150 mW (D)
200
0
25
50
75
100
125
150
175
TA, AMBIENT TEMPERATURE (0C)
MC14547B
6396

VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
1.7 V
1.7 V
VSS
VSS
VDD
VDD
LIGHTEMITTING DIODE (LED) READOUT

USING A ZENER DIODE TO REPLACE DROPPING RESISTORS
VDD
**
COMMON
CATHODE LED
VSS
VSS

VDD
APPROPRIATE
VOLTAGE
VZD*
VSS
FLUORESCENT READOUT
VDD
DIRECT
(LOW BRIGHTNESS)
VSS
* VZD should be set at VDD 1.3 V VLED. Wattage of zener diode
must be calculated for number of segments and worstcase
conditions.
** A filament prewarm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
FILAMENT
SUPPLY
VSS
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(Caution: Absolute maximum
working voltage = 18.0 V)
MC14547B
6397
MOTOROLA
MC14549B
MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation registers are
8bit registers providing all the digital control and storage necessary for
successive approximation analogtodigital conversion systems. These
parts differ in only one control input. The Master Reset (MR) on the
MC14549B is required in the cascaded mode when more than 8 bits are
desired. The Feed Forward (FF) of the MC14559B is used for register
shortening where EndofConversion (EOC) is required after less than eight
cycles.
Applications for the MC14549B and MC14559B include analogtodigital
conversion, with serial and parallel outputs.
Totally Synchronous Operation
Serial Output
Retriggerable
Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8Bit D/A Converter
All Control Inputs PositiveEdge Triggered
Range
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
PIN ASSIGNMENT
Q4
16
VDD
Q5
15
Q3
Q6
14
Q2
Q7
13
Q1
Sout
12
Q0
_C
11
EOC
_C
10
VSS
Symbol
Value
Unit
VDD
0.5 to + 18
Vdc
Vin
0.5 to VDD + 0.5
Vdc
Iin
10
mAdc
PD
500
mW
TA
55 to + 125
Rating
DC Supply Voltage
Tstg
65 to + 150
P and D/DW Packages: 7.0 mW/C From 65_C To 125_C Ceramic
L Packages: 12 mW/_C From 100_C To 125_C
MC14549B
TRUTH TABLES
SC SC(t1) MR MR(t1) Clock

Action
X
X
X
X
None
X
X
1
X
Reset
1
0
0
0
Start
Conversion
1
X
0
1
Start
Conversion
1
1
0
0
Continue
Conversion
0
X
0
X
Continue
Previous
Operation
X = Dont Care t1 = State at Previous Clock
MC14549B MC14559B
6398
Plastic
Ceramic
SOIC
SC
* For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.
MC14559B
SC SC(t1) EOC Clock

X
1
X
0
X
0
Action
None
Start
Conversion
Continue
Conversion
Continue
Conversion
Retain
Conversion
Result
Start
Conversion

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
5.0
10
15
1.28
3.2
8.4
1.02
2.6
6.8
1.76
4.5
17.6
0.72
1.8
4.8
mAdc
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Vin = 0 or VDD
Input Voltage #
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
55_C
VDD
Vdc
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Q Outputs
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Pin 5, 11 only
IOL
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
(Clock = 0 V,
Other Inputs = VDD
or 0 V, Iout = 0 A)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

Per Package)
buffers switching)

Adc

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
IT(CL) = IT(50 pF) + 3.5 x 103 (CL = 50) VDDf
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it
is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or
Vout)
VDD.
MC14549B MC14559B
6399

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

Clock to Q
Clock to Sout
Clock to EOC
tPLH,
tPHL
VDD
Min
Typ
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
500
210
155
1000
420
310
5.0
10
15
750
310
220
1500
620
440
5.0
10
15
300
130
100
600
260
200
tsu
5.0
10
15
250
100
80
125
50
40
ns
tWH(cl)
5.0
10
15
700
270
200
350
135
100
ns
Pulse Width D, SC, FF or MR
tWH
5.0
10
15
500
200
160
250
100
80
ns
tTLH,
tTHL
5.0
10
15
15
1.0
0.5
5.0
10
15
1.5
3.0
4.0
0.8
1.5
2.0
MHz
SC, D, FF or MR Setup Time
Clock Pulse Width
fcl
MC14549B MC14559B
6400
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

VDD
Q7
Q6
Q5
PROGRAMMABLE
PULSE
GENERATOR
CL
CL
Q4
Q3
SC
CL
CL
Q2
Q1
FF(MR)
CL
CL
Q0
EOC
CL
CL
Sout
CL
CL
1
fcl
VSS
C
tWH(cl)
50%
SC
D
tsu
50%
tsu
50%
tPLH
Q7
tWH(D)
tsu
tPHL
50%
90%
tTLH
Sout
10%
tTHL
50%
tPLH
90%
10%
tTLH
NOTE: Pin 10 = VSS
TIMING DIAGRAM
CLOCK
SC
D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
EOC
Sout
INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH

Dont care condition
INH Indicates Serial Out is inhibited low.

* Q8 is ninthbit of serial information available from 8bit register.
NOTE: Pin 10 = VSS
MC14549B MC14559B
6401
Both the MC14549B and MC14559B can be operated in
either the free run or strobed operation mode for conversion schemes with any number of bits. Reliable cascading
and/or recirculating operation can be achieved if the End of
Convert (EOC) output is used as the controlling function,
since with EOC = 0 (and with SC = 1 for MC14549B but
either 1 or 0 for MC14559B) no stable state exists under continual clocked operation. The MC14559B will automatically
recirculate after EOC = 1 during externally strobed operation,
provided SC = 1.
All data and control inputs for these devices are triggered
into the circuit on the positive edge of the clock pulse.
Operation of the various terminals is as follows:
C = Clock A positivegoing transition of the Clock is
required for data on any input to be strobed into the circuit.
SC = Start Convert A conversion sequence is initiated
on the positivegoing transition of the SC input on succeeding clock cycles.
D = Data in Data on this input (usually from a comparator in A/D applications) is also entered into the circuit on a
positivegoing transition of the clock. This input is Schmitt
triggered and synchronized to allow fast response and guaranteed quality of serial and parallel data.
MR = Master Reset (MC14549B Only) Resets all output to 0 on positivegoing transitions of the clock. If removed
while SC = 0, the circuit will remain reset until SC = 1. This
allows easy cascading of circuits.
FF = Feed Forward (MC14559B Only) Provides register shortening by removing unwanted bits from a system.
For operation with less than 8 bits, tie the output following
the least significant bit of the circuit to EOC. E.g., for a 6bit
FROM A/D
COMPARATOR
D
C
SC
conversion, tie Q1 to FF; the part will respond as shown in

the timing diagram less two bit times. Not that Q1 and Q0 will
still operate and must be disregarded.
For 8bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16 bits, use
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly to
the least significant bit used in the MC14559B allows EOC to
provide the cascading signal, and results in smooth transition
of serial information from the MC14559B to the MC14549B.
The Serial Out (S out) inhibit structure of the MC14559B
remains inactive one cycle after EOC goes high, while Sout of
the MC14549B remains inhibited until the second clock cycle
of its operation.
Qn = Data Outputs After a conversion is initiated the
Qs on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once conditionally reset they remain in the proper state until the circuit is
either reset or reinitiated.
EOC = End of Convert This output goes high on the
negativegoing transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can indicate complete conversion.
Sout = Serial Out Transmits conversion in serial fashion. Serial data occurs during the clock period when the corresponding parallel data bit is conditionally reset. Serial Out
is inhibited on the initial period of a cycle, when the circuit is
reset, and on the second cycle after EOC goes high. This
provides efficient operation when cascaded.
EXTERNAL
CLOCK
1/4 MC14001
Sout
C
SC
MC14559B
* FF
Q7 Q6 Q5 Q4 Q0 EOC
Sout
MC14549B
MR
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC
**
MSB
SERIAL OUT
(CONTINUAL
UPDATE EVERY
13 CLOCK CYCLES)
NC
TO D/A AND PARALLEL DATA
LSB
TO D/A AND
PARALLEL DATA
FREE RUN MODE
EXTERNAL STROBE
* FF allows EOC to activate as if in 4stage register.
** Cascading using EOC guaranteed; no stable unfunctional state.
Completion of conversion automatically reinitiates cycle in free run mode.
Figure 1. 12Bit Conversion Scheme
MC14549B MC14559B
6402
Externally Controlled 6Bit ADC (Figure 2)
Continuously Cycling 12Bit ADC (Figure 4)
Several features are shown in this application:

Shortening of the register to six bits by feeding the seventh
output bit into the FF input.
Continuous conversion, if a continuous signal is applied to
SC.
Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
The EOC output indicating that the parallel data are valid
and that the serial output is complete.
Because each successive approximation register (SAR)

has a capability of handling only an eightbit word, two must
be cascaded to make an ADC with more than eight bits.
When it is necessary to cascade two SARs, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling, because during switchon or due to outside influences, the first
stage has entered a reset state, the entire ADC will remain in
a stable nonfunctional condition.
This 12bit ADC is continuously recycling. The serial as
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of
Continuously Cycling 8Bit ADC (Figure 3)

This ADC is running continuously because the EOC signal
is fed back to the SC input, immediately initiating a new cycle
on the next clock pulse.
C
SC
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 2. Externally Controlled 6Bit ADC
C
SC
Sout
MC14559B
Q7 Q6
Q5
Q4
Q3
Q2
Q1
Q0
FF EOC
TO DAC
Figure 3. Continuously Cycling 8Bit ADC
MC14549B MC14559B
6403
Sout
C
SC
Sout
Sout
MC14549B
MR
SC
MC14559B
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
TO DAC
EOC
Figure 4. Continuously Cycling 12Bit ADC
the 12bit conversion cycle, the end of the serial output

word, and the validity of the parallel data output.
Additional Motorola Parts for Successive

Approximation ADC
Externally Controlled 12Bit ADC (Figure 5)
Monolithic digitaltoanalog converters The

MC1408/1508 converter has eightbit resolution and is available with 6, 7, and 8bit accuracy. The amplifiercomparator block The MC1407/1507 contains a high speed
operational amplifier and a high speed comparator with adjustable window.
With these two linear parts it is possible to construct SA
ADCs with an accuracy of up to eight bits, using as the register one MC14549B or one MC14559B. An additional CMOS
block will be necessary to generate the clock frequency.
Additional information on successive approximation ADC
is found in Motorola Application Note AN716.
In this circuit the external pulse starts the first SAR and
simultaneously resets the cascaded second SAR. When Q4
of the first SAR goes high, the second SAR starts conversion, and the first one stops conversion. EOC indicates that
the parallel data are valid and that the serial output is complete. Updating the output data is started with every external
control pulse.
SC
Sout
MC14559B
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOC
TO DAC
Sout
MC14549B
MR
SC
TO DAC
EOC
Sout
Figure 5. Externally Controlled 12Bit ADC
MC14549B MC14559B
6404
MOTOROLA
MC14551B
Quad 2-Channel Analog
L SUFFIX
CERAMIC
CASE 620
The MC14551B is a digitallycontrolled analog switch. This device

implements a 4PDT solid state switch with low ON impedance and very low
OFF Leakage current. Control of analog signals up to the complete supply
voltage range can be achieved.
Triple Diode Protection on All Control Inputs
Analog Voltage Range (VDD VEE) = 3.0 to 18 V
Note: VEE must be
VSS
Low Noise 12 nVCycle, f 1.0 kHz typical
For Low RON, Use The HC4051, HC4052, or HC4053 HighSpeed
CMOS Devices
Switch Function is Break Before Make
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced to VEE,

VSS VEE)
0.5 to + 18.0
Vin, Vout

(Referenced to VSS for Control Input &
VEE for Switch I/O)
0.5 to VDD + 0.5
Iin
Input Current (DC or Transient), per

Control Pin
10
mA
Isw
25
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
9
SWITCHES
IN/OUT
15
1
2
3
6
10
11
12
CONTROL
W
W0
W1
X0
X1
Y0
Y1
Z0
Z1
14
4
COMMONS
OUT/IN
13
16
VDD
Control
ON
X0
15
W0
W0 X0 Y0 Z0
X1
14
W1 X1 Y1 Z1
13
12
Z1
Y0
11
Z0
VEE
10
Y1
VSS
VDD = Pin 16
VSS = Pin 8
VEE = Pin 7
NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be
W1
CONTROL
v VSS.
MC14551B
6405
55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit

Range
VDD
VDD 3.0 VSS

VEE
3.0
18
3.0
18
3.0
18

Package
IDD
5.0
10
15

VSS or VDD,
Switch I/O: VEE VI/O
VDD, and Vswitch
500 mV**
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
5.0
10
15
TA = 25_C only (The

channel component,
(Vin Vout)/Ron, is
not included.)

(Dynamic Plus
Quiescent, Per Package)
ID(AV)
v
v
Typical

CONTROL INPUT (Voltages Referenced to VSS)

VIL
5.0
10
15
Ron = per spec,

Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
VIH
5.0
10
15
Ron = per spec,

Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Iin
15
Vin = 0 or VDD
0.1
0.00001
0.1
1.0
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN W, X, Y, Z (Voltages Referenced to VEE)

Recommended Peakto
Peak Voltage Into or Out
of the Switch
VI/O
Channel On or Off
VDD
VDD
VDD
Vpp
Vswitch
Channel On
600
600
300
mV
VOO
Vin = 0 V, No Load
10
ON Resistance
Ron
5.0
10
15
Vswitch
500 mV**,
Vin = VIL or VIH
0 to VDD (Switch)
800
400
220
250
120
80
1050
500
280
1200
520
300
Ron
5.0
10
15
70
50
45
25
10
10
70
50
45
135
95
65
Ioff
15
Vin = VIL or VIH

Channel or Any One
Channel
100
0.05
100
1000
nA
CI/O
Switch Off
10
pF
CO/I
17
pF
(Channel Off)
CI/O
0.15
0.47
pF
Any Two Channels
in the Same Package
OffChannel Leakage
Current (Figure 8)
Pins Not Adjacent

Pins Adjacent
** current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
** Ratings are exceeded. (See first page of this data sheet.)
MC14551B
6406
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE

Characteristic
Symbol

Switch Input to Switch Output (RL = 10 k)
tPLH, tPHL
Control Input to Output (RL = 10 k)

VEE = VSS (Figure 4)
tPLH, tPHL
VSS)
VDD VEE
Vdc
Min
Typ #
Max
Unit
ns
5.0
10
15
35
15
12
90
40
30
5.0
10
15
350
140
100
875
350
250
10
0.07
BW
10
17
MHz
Off Channel Feedthrough Attenuation, Figure 5

RL = 1 k, Vin = 1/2 (VDD VEE) pp,
fin = 55 MHz
10
50
dB

fin = 3 MHz
10
50
dB
Crosstalk, Control Input to Common O/I, Figure 7

R1 = 1 k, RL = 10 k,
Control tr = tf = 20 ns
10
75
mV

RL = 10 k, f = 1 kHz, Vin = 5 Vpp
Bandwidth (Figure 5)
20 Log (Vout / Vin) = 3 dB, CL = 50 pF
ns
circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD for control inputs and VEE
(Vin or Vout) VDD for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must
be left open.
MC14551B
6407
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16
CONTROL 9
VDD
LEVEL
CONVERTER
VSS
CONTROL
VEE
W0 15
14 W
W1 1
X0 2
4 X
X1 3
Y0 6
5 Y
Y1 10
Z0 11
13 Z
Z1 12
MC14551B
6408
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
PULSE
GENERATOR
CONTROL
Vout
LOAD
V
RL
CL
SOURCE
VDD VEE VEE VDD
Figure 4. Propagation Delay Times,

Control to Output
Control input used to turn ON or OFF

RL
ON
CONTROL
Vout
RL
CONTROL
OFF
CL = 50 pF
Vout
RL
CL = 50 pF
Vin
VDD VEE
2
Vin
VDD VEE
2


(Adjacent Channels Used for Setup)

VDD
CONTROL
Vout
RL
CONTROL
SECTION
OF IC
VEE
OTHER
CHANNEL(S)
CL = 50 pF
VEE
VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input

to Common O/I
MC14551B
6409
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
VDD
X/Y
PLOTTER
VEE = VSS
350
300
300
250
200
150
TA = 125C
100
25C
55C
50
RON, ON RESISTANCE (OHMS)
0
10 8.0 6.0 4.0 2.0
2.0
4.0
6.0
8.0
350
250
200
150
TA = 125C
100
25C
55C
50
0
10 8.0 6.0 4.0 2.0
10
2.0
4.0
6.0
8.0
Figure 10. VDD @ 7.5 V, VEE @ 7.5 V
700
350
600
300
500
400
300
TA = 125C
200
25C
100
55C
0
10 8.0 6.0 4.0 2.0
2.0
4.0
6.0
8.0
10
10
TA = 25C
VDD = 2.5 V
250
200
150
5.0 V
100
7.5 V
50
0
10 8.0 6.0 4.0 2.0
2.0
4.0
6.0
8.0
10
Figure 13. Comparison at 25_C, VDD @ VEE
MC14551B
6410
Figure A illustrates use of the onchip level converter
detailed in Figure 2. The 0to5 volt Digital Control signal is
used to directly control a 9 Vpp analog signal.
V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at
and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the
maximum swing below V SS. For the example, V DD V SS
= 5 volt maximum swing above V SS; VSS VEE = 5 volt
maximum swing below VSS. The example shows a 4.5 volt
signal which allows a 1/2 volt margin at each peak. If voltage
transients above V DD and/or below V EE are anticipated on

the analog channels, external diodes (Dx) are recommended
as shown in Figure B. These diodes should be small signal
types able to absorb the maximum anticipated current
surges during clipping.
and V EE is 18.0 volts. Most parameters are specified up to
15 volts which is the recommended maximum difference between V DD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to V EE . For example, V DD =
+ 10 volts, V SS = + 5 volts, and V EE = 3 volts is acceptable.
See the table below.
+5 V
5 V
VDD VSS
9 Vpp
+5 V
SWITCH
I/O
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
VEE
+ 4.5 V
COMMON
O/I
9 Vpp
GND
ANALOG SIGNAL
MC14551B
0TO5 V DIGITAL
4.5 V
CONTROL
CONTROL SIGNAL

VDD
VDD
Dx
Dx
SWITCH
I/O
COMMON
O/I
Dx
Dx
VEE
VEE
Figure B. External Schottky or Germanium Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS

VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
Maximum Analog Signal Range

In Volts
+8
+ 8/0
+ 8 to 8 = 16 Vpp
+5
12
+ 5/0
+ 5 to 12 = 17 Vpp
+5
+ 5/0
+ 5 to 0 = 5 Vpp
+5
+ 5/0
+ 5 to 5 = 10 Vpp
+ 10/ + 5
+ 10 to 5 = 15 Vpp
+ 10
MC14551B
6411
MOTOROLA
MC14553B
3-Digit BCD Counter
L SUFFIX
CERAMIC
CASE 620
The MC14553B 3digit BCD counter consists of 3 negative edge triggered

BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An onchip oscillator provides the lowfrequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
TTL Compatible Outputs

OnChip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC

Parameter
Value
Unit
0.5 to + 18.0
0.5 to VDD + 0.5
10
mA
Iout
+ 20
mA
PD
Tstg
Storage Temperature
Symbol
VDD
Vin, Vout
Iin
TL
DC Supply Voltage
500
mW
65 to + 150
_C
260
_C
BLOCK DIAGRAM
4
CIA
12
CLOCK
10
LE
11
DIS
13
MR
3
CIB Q0
Q1
Q2
Q3
O.F.
DS1
DS2
2
1
DS3
15
14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Master
Reset
0
0
0
0
0
0
0
0
1
Clock
X
1
1
0
X
X
X
Disable
LE
Outputs
0
0
1
0
0
X
0
0
X
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
X
X
X
X
1
0

to the range VSS
(Vin or Vout)
VDD.
X = Dont Care
MC14553B
6412

Characteristic
Symbol
Output Voltage
Vin = VDD or 0
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Vdc
Vdc
IOH

(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
Pin 3
5.0
10
15
0.25
0.62
1.8
0.2
0.5
1.5
0.36
0.9
3.5
0.14
0.35
1.1
(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
Other
Outputs
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
5.0
10
15
0.5
1.1
1.8
0.4
0.9
1.5
0.88
2.25
8.8
0.28
0.65
1.20
mAdc
5.0
10
15
3.0
6.0
18
2.5
5.0
15
4.0
8.0
20
1.6
3.5
10
mAdc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Pin 3
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink Other
Outputs
IOL
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
MR = VDD
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15

Per Package)
buffers switching)

Adc
MC14553B
6413

Figure
Symbol

Characteristic
2a
tTLH,
tTHL
VDD
Min
Typ #
Max
Clock to BCD Out
2a
Clock to Overflow
Unit
5.0
10
15
100
50
40
200
100
80
tPLH,
tPHL
5.0
10
15
900
500
200
1800
1000
400
ns
2a
tPHL
5.0
10
15
600
400
200
1200
800
400
ns
Reset to BCD Out
2b
tPHL
5.0
10
15
900
500
300
1800
1000
600
ns
Clock to Latch Enable Setup Time

Master Reset to Latch Enable Setup Time
2b
tsu
5.0
10
15
600
400
200
300
200
100
ns
Removal Time
Latch Enable to Clock
2b
trem
5.0
10
15
80
10
0
200
70
50
ns
Clock Pulse Width
2a
tWH(cl)
5.0
10
15
550
200
150
275
100
75
ns
Reset Pulse Width
2b
tWH(R)
5.0
10
15
1200
600
450
600
300
225
ns
Reset Removal Time
trem
5.0
10
15
80
0
20
180
50
30
ns
Input Clock Frequency
2a
fcl
5.0
10
15
1.5
5.0
7.0
0.9
2.5
3.5
MHz
Input Clock Rise Time
2b
tTLH
5.0
10
15
Disable, MR, Latch Enable

Rise and Fall Times
tTLH,
tTHL
5.0
10
15
15
5.0
4.0
Scan Oscillator Frequency

(C1 measured in F)
fosc
5.0
10
15
1.5/C1
4.2/C1
7.0/C1
Hz
ns
No
Limit
ns
MC14553B
6414
899
900
901
990
991
992
993
994
995
996
997
998
999
1000
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
HUNDREDS
CLOCK
UP AT 980
UP AT 80
HUNDREDS Q0
HUNDREDS Q3
DISABLE
UP AT 800
(DISABLES CLOCK WHEN HIGH)
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
TENS
DIGIT SELECT 2
DIGIT SELECT 3
HUNDREDS
Figure 1. 3Digit Counter Timing Diagram (Reference Figure 3)
VDD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
C
LE
DIS
MR
8
20 ns
CL
CLOCK
CL
CL
CL
90%
10%
tPLH
BCD OUT
CL
20 ns
1000
16
999
(a)
PULSE
GENERATOR
tWL(cl)
50%
10%
tTLH
90%
tPHL
50%
tTHL
OVERFLOW
1/fcl
tPHL
50%
VSS
tTLH
(b)
GENERATOR
1
GENERATOR
2
GENERATOR
3
CLOCK
VDD
C
LE
MR
DIS
50%
90%
10%
tsu
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
trem
CL
CL
CL
LATCH
ENABLE
tPHL, tPLH
CL
CL
50%
BCD OUT
tsu
50%
tPHL
VSS
50%
MASTER RESET
tWH(R)

MC14553B
6415
The MC14553B threedigit counter, shown in Figure 3,
consists of three negative edgetriggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.
An onchip oscillator provides the low frequency scanning
clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one
LATCH ENABLE
10
CLOCK
12
PULSE
SHAPER
pulse for every 1000 counts.

The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle.
C1A
4
SCAN
R
OSCILLATOR 3
C1B
C1
PULSE
GENERATOR
R SCANNER
Q0
Q1
Q2
R 10
Q3
UNITS
C
QUAD
LATCH
9
11
DISABLE
(ACTIVE
HIGH)
MULTIPLEXER
7
Q0
C
Q1
Q2
R 10
Q3
TENS
Q1
BCD
OUTPUTS
(ACTIVE
HIGH)
QUAD
LATCH
6
Q0
Q1
Q2
R
10 Q3
HUNDREDS
C
13
MR
(ACTIVE HIGH)
Q0
Q2
Q3
QUAD
LATCH
14
OVERFLOW
2
1
15
DS1 DS2 DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
Figure 3. Expanded Block Diagram
MC14553B
6416
STROBE
RESET
12
CLOCK
INPUT
11
10
LE
13
MR
CLK
MC14553B
DIS
10
C1A
C1B
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1 2
4
3
14
0.001
F
12
11
13
LE
MR
CLK
C1 B
MC14553B
DIS
Figure 4. SixDigit Display
3
2
VDD
3
14
B
C
b
c
5
9
a
A
3
B
b 10
2
11
C
c
12
4
D MC14543B d
6
13
Ph
e
1
15
f
LD
7
14
BI
g
DISPLAYS ARE LOW CURRENT LEDs
(I peak < 10 mA PER SEGMENT)
9
10
11
12
D MC14543B d
6
13
Ph
e
1
15
LD
f
7
g 14
BI
4
VDD
LSD
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1
2
5
VDD
C1 A
MSD
MC14553B
6417
MOTOROLA
MC14554B
2-Bit by 2-Bit Parallel
Binary Multiplier
The MC14554B 2 x 2bit parallel binary multiplier is constructed with
complementary MOS (CMOS) enhancement mode devices. The multiplier
can perform the multiplication of two binary numbers and simultaneously add
two other binary numbers to the product. The MC14554B has two
multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five
cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and
carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be
expanded into a straightforward mbit by nbit parallel multiplier without
additional logic elements.
Application areas include arithmetic processing (multiplying/adding,
obtaining square roots, polynomial evaluation, obtaining reciprocals, and
dividing), Fast Fourier Transform processing, digital filtering, communications (convolution and correlation), and process and machine controls.

Straightforward mBit By nBit Expansion
No Additional Logic Elements Needed for Expansion
Multiplies and Adds Simultaneously
Positive Logic Design

VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
260
_C
PIN ASSIGNMENT
MC14554B
6418
Y1
16
VDD
M0
15
Y0
M1
14
X0
C0
13
X1
M2
12
K0
C1 (S3)
11
S0
S2
10
K1
VSS
S1
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
Symbol
L SUFFIX
CERAMIC
CASE 620

to the range VSS
(Vin or Vout)
VDD.
EQUATIONS
S = (X x Y) + K + M
Where:
x Means Arithmetic Times.
+ Means Arithmetic Plus.
S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0,
K = K1 K0, M = M1 M0 (Binary Numbers).
Example:
Given: X = 2(1), Y = 3(11)
K = 1(01), M = 2(10)
Then:
S = (2 x 3) + 1 + 2 = 9
S = (10 x 11) + 01 + 10 = 1001
NOTE: C0 connected to M2 for this size

multiplier. See general expansion
diagram for other size multipliers.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14554B
6419

Characteristic
Symbol

tTLH,
tTHL

K0 to C0
M0 to S2
tPLH,
tPHL
VDD
Min
Typ #
Max
100
50
40
200
100
80
Unit
ns
5.0
10
15
ns
5.0
10
15
270
115
85
675
290
215
5.0
10
15
680
280
210
1700
750
570
20 ns
20 ns
VDD
90%
20 ns
90%
10%
OUTPUT
C0 OR S2
VSS
tPHL
VSS
VOH
50%
VOL
tTLH
1
2f
tTHL
For K0 to C0:
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs
M0 and M1 high.
VOH
VOL
ANY OUTPUT
(50% DUTY CYCLE)
tPLH
VDD
90%
50%
10%
ALL INPUTS
(50% DUTY CYCLE)
10%
INPUT
K0 OR M0
20 ns
50%
For M0 to S2:
Inputs X1, Y1, and K0 low, and inputs X0, Y0,
K1, M1, and M2 high.
All outputs connected to respective

CL loads. f = system clock frequency

Waveforms
LOGIC DIAGRAM
M1
Y1
1
M
C0
M2
M0
15
M
MULTIPLIER
CELL
C
S
Y0
14
X
MULTIPLIER
CELL
C
S
12
X0
MULTIPLIER CELL
K0
5
M
MULTIPLIER
CELL
C
S
6
C1(S3)
MC14554B
6420
MULTIPLIER
CELL
C
S
7
S2
M
X
9
S1
13
X
M
Y
X
K
X1
S
L
C
10
K
K1
11
S0
EXPANSION DIAGRAM
mBit by nBit Parallel Binary Multiplier (Top View)
Y AND M
Y(n1)
M(n2)
M(n1)
Y(n2)
X0
X1
Y(n1)
Y3
M2
M3
Y2
X0
X1
VDD
Y0
X0
X1
K0
M2
C1
S0
K1
S2
VSS S1
Y1
M0
M1
C0
Y0
X0
X1
K0
K1
Y1
Y3
Y(n2)
X2
X3
Y1
M0
M1
X AND K
Y0
X2
X3
K2
Y2
X2
X3
K3
Y(n1)
Y1
Y3
Y(n2)
X(m2)
X(m1)
Y0
X(m2)
X(m1)
K(m2)
Y2
X(m2)
X(m1)
K(m1)
S(m + n1)
S(m + n2)
S(m + n3)
S(m+2)
S(m+1)
S(m)
S(m1)
S3
S1
S(m2) S2
S0
S = (X x Y) + K + M Where: x means Arithmetic Times.

S = (X x Y) + K + M Where: + means Arithmetic Plus.
S = S(m + n1) S(m + n2) S2 S1 S0
X = X(m1) X (m2) X2 X1 X0, Y = Y(n1) Y(n2) Y2 Y1 Y0
K = K(m1) K(m2) K2 K1 K0 and M = M(n1) M(n2) M2 M1 M0
(Binary Numbers).
Number of output binary digits = m + n
Number of packages = mxn/4 (For m or n of both odd select next highest even number.)
MC14554B
6421
MOTOROLA
MC14555B
MC14556B
Dual Binary to 1-of-4

Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with complementary
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
has two select inputs (A and B), an active low Enable input (E), and four
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the high state, and the MC14556B has the selected
output go to the low state. Expanded decoding such as binarytohexadecimal (1of16), etc., can be achieved by using other MC14555B or
MC14556B devices.
Applications include code conversion, address decoding, memory selection control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Active High or Active Low Outputs
Expandable
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
TRUTH TABLE
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Enable
Iin, Iout

per Pin
10
mA
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
_C
260
TL
BLOCK DIAGRAM
MC14555B
2
14
13
15
MC14556B
Q0
Q1
Q2
Q3
4
5
6
7
Q0
Q1
Q2
Q3
12
11
10
9
14
13
15
Q0
Q1
Q2
Q3
4
5
6
7
Q0
Q1
Q2
Q3
12
11
10
9
Inputs
Outputs
Select
MC14555B
MC14556B
X = Dont Care

to the range VSS
(Vin or Vout)
VDD.
VDD = PIN 16
VSS = PIN 8
MC14555B MC14556B
6422

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
Vdc
Vdc
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
mAdc
Source
Sink

Per Package)
buffers switching)

Adc
PIN ASSIGNMENTS
MC14555B
MC14556B
EA
16
VDD
EA
16
VDD
AA
15
EB
AA
15
EB
BA
14
AB
BA
14
AB
Q0A
13
BB
Q0A
13
BB
Q1A
12
Q0B
Q1A
12
Q0B
Q2A
11
Q1B
Q2A
11
Q1B
Q3A
10
Q2B
Q3A
10
Q2B
VSS
Q3B
VSS
Q3B
MC14555B MC14556B
6423

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time A, B to Output

tPLH,
tPHL
Propagation Delay Time E to Output

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
220
95
70
440
190
140
5.0
10
15
200
85
65
400
170
130
Unit
ns
ns
ns
INPUT E LOW
20 ns
A INPUTS
(50% DUTY CYCLE)
INPUT A HIGH, INPUT E LOW

20 ns
20 ns
1
2f
90%
50%
10%
VDD
20 ns
VSS
INPUT B
VDD
tPHL
B INPUTS
(50% DUTY CYCLE)
VSS
OUTPUT Q1
VOL
VOH
All 8 outputs connect to respective CL loads.

VDD
90%
50%
10%
tPLH
OUTPUT Q3
MC14556B
tTHL
tPLH
90%
50%
10%
90%
50%
10%
OUTPUT Q3
MC14555B
tTLH
VSS
VOH
V
tTLH OL
tPHL
VOH
VOL
tTHL
LOGIC DIAGRAM
(1/2 of Dual)
*
Q0
A
*
Q1
B
*
Q2
Q3
* Eliminated for MC14555B
MC14555B MC14556B
6424
MOTOROLA
MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length may
be programmed to be any number of bits between 1 and 64. The number of
bits selected is equal to the sum of the subscripts of the enabled Length
Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be
selected from the A or B data inputs with the A/B select input. This feature is
useful for recirculation purposes. A Clock Enable (CE) input is provided to
allow gating of the clock or negative edge clocking capability.
The device can be effectively used for variable digital delay lines or simply
to implement odd length shift registers.
164 Bit Programmable Length
Q and Q Serial Buffered Outputs
All Inputs Buffered
No Limit On Clock Rise and Fall Times
Capable of Driving Two Lowpower TTL Loads or one Lowpower
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
BLOCK DIAGRAM
3
4
5
6
7
9
2
1
15
14
13
12
RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32
L16
L8
L4
L2
L1
Register Length
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1 Bit
2 Bits
Bit
3 Bits
4 Bits
5 Bits
6 Bits

1
1
0
0
0
0
0
0
0
0
0
1
Bit
33 Bits
34 Bits

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
61 Bits
62 Bits
63 Bits
64 Bit
Bits
10
11
VDD = PIN 16
VSS = PIN 8
LENGTH SELECT TRUTH TABLE

L32
TRUTH TABLE
Inputs
Rst
A/B
0
0
0
0
1
0
1
0
1
X
Output
Clock
1
1
X
CE
0
0
B
A
B
A
0
Q is the output of the first selected shift

register stage.
X = Dont Care
NOTE: Length equals the sum of the binary length control

subscripts plus one.
MC14557B
6425

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
mAdc
IOH
Source
Sink

Per Package)
buffers switching)

Adc
be left open.
MC14557B
6426
Symbol
VDD
Min
Typ #
Max
5
10
15
100
50
40
200
100
80
5
10
15
300
130
90
600
260
180
5
10
15
300
130
95
600
260
190
tWH(cl)
5
10
15
200
100
75
95
45
35
ns
tWH(rst)
5
10
15
300
140
100
150
70
50
ns
Clock Frequency (50% Duty Cycle)
fcl
5
10
15
3.0
7.5
13.0
1.7
5.0
6.7
MHz
Setup Time, A or B to Clock or CE

Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
5
10
15
700
290
145
350
130
85
5
10
15
400
165
60
45
5
0
5
10
15
200
100
10
150
60
50
5
10
15
400
185
85
50
25
22
Characteristic
Rise and Fall Time, Q or Q Output

tTLH,
tTHL
Propagation Delay, Clock or CE to Q or Q

Propagation Delay, Reset to Q or Q
Pulse Width, Clock
tPLH,
tPHL
Pulse Width, Reset
Unit
ns
ns
tPLH,
tPHL
ns
ns
Best case condition: L32 = VDD, L1 through L16 =

Dont Care (Any register length from 33 to 64)
th
Hold Time, Clock or CE to A or B

Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
ns
Worst case condition: L32 = VDD, L1 through L16 =

Dont Care (Any register length from 33 to 64)
Rise and Fall Time, Clock
Rise and Fall Time, Reset or CE
Removal Time, Reset to Clock or CE
tr,
tf
5
10
15
tr,
tf
5
10
15
15
5
4
trem
5
10
15
160
80
70
80
40
35
ns
No Limit
# Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
TIMING DIAGRAM
VDD
50%
CLOCK
tWH(cl)
1/fcl
VSS
VDD
50%
A INPUT
VSS
trem
tsu
VDD
th
50%
VSS
RESET
1bit length:
CE = 0
Q
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0
tTLH
90%
50%
10%
tPLH
tTHL
tPHL
PWR
VOH
tPHL
VOL
MC14557B
6427
MC14557B
6428
CE
5
4
CLOCK
RESET
32 BIT
16 BIT
R
4 BIT
8 BIT
6
B
A/B 9
SELECT
12
13
14
15
L32
L16
L8
L4
2 BIT
R
1 BIT
10
1 BIT
11
L1
L2
14
15
16
L32
L16
L8
L4
VDD
PIN ASSIGNMENT
RESET
13
12
11
10
A/B SEL
CE
CLOCK
VSS
L2
L1
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAM
MOTOROLA
MC14558B
Decoder
L SUFFIX
CERAMIC
CASE 620
The MC14558B decodes 4bit binary coded decimal data dependent on

the state of auxiliary inputs, Enable and RBI, and provides an activehigh
sevensegment output for a display driver.
An auxiliary input truth table is shown, in addition to the BCD to
sevensegment truth table, to indicate the functions available with the two
auxiliary inputs.
Leading Zero blanking is easily obtained with an external flipflop in time
division multiplexed systems displaying most significant decade first.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Segment Blanking for All Illegal Input Combinations
Lamp Test Function
Capability for Suppression of NonSignificant Zeros
Lamp Intensity Function
Capable of Driving Two Lowpower TTL Loads. One Lowpower
Range
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Rating
Symbol
Value
Unit
VDD
0.5 to + 18
Vin
0.5 to VDD + 0.5
DC Input Voltage, per Pin
Iin
10
mAdc
TA
55 to + 125
_C
PD
500
mW
Tstg
65 to + 150
DC Supply Voltage
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
B
16
VDD
15
ENABLE
14
RBO
13
RBI
12
11
10
VSS
_C
a
g
f
e
b
c
DISPLAY
AUXILIARY INPUT TRUTH TABLE

Enable
Pin 3
RBI
Pin 5
BCD
Input
Code
RBO
Pin 4
Lamp Test
Blank Segments
Display Zero
Blank Segments
19
19 Displayed
Function Performed
X = Dont Care
RBI = Ripple Blanking Input
RBO = Ripple Blanking Output
MC14558B
6429

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package) Vin = 0 or VDD
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc

Adc

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however,
it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or
Vout) VDD.
MC14558B
6430
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C; see Figure 1)

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

tPLH = (0.66 ns/pF) CL + 187 ns
tPLH

tPHL = (0.66 ns/pF) CL + 242 ns
tPHL
VDD
Min
Typ
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
100
50
40
200
100
80
5.0
10
15
580
220
145
1160
440
230
5.0
10
15
780
275
185
1560
550
370
Unit
ns
ns
ns
ns
* The formulae given are for the typical characteristics only.
TRUTH TABLE
Inputs
Outputs*
Enable
Pin 3
RBI
Pin 5
D
Pin 6
C
Pin 2
B
Pin 1
A
Pin 7
a
Pin 13
b
Pin 12
c
Pin 11
d
Pin 10
e
Pin 9
f
Pin 15
g
Pin 14
RBO
Pin 4
Display
Blank
Blank
* All nonvalid BCD input codes produce a blank display.

X = Dont Care
20 ns
ANY INPUT
20 ns
10%
tPLH
90%
tPHL
50%
ANY OUTPUT
tTLH
50%
90%
10%
tTHL
Figure 1. Signal Waveforms
MC14558B
6431
MC14558B
6432
RBO
g
D
14
f
15
e
C
d
B
11
10
b
12
7
RBI
5
ENABLE
13
LOGIC DIAGRAM
N4
RBI
VSS
N3
RBO
RBI
En
N2
RBO
RBI
En
N1
RBO
RBI
En
N1
RBO
RBI
En
N2
RBO
RBI
En
N3
RBO
RBI
En
RBO
En
VSS
LAMP TEST
Figure 2. Leading and Trailing Zero

Suppression with Lamp Test
N4
N3
N2
N1
N1
N2
N3
VDD
RBO
RBI
RBI
En
BLANKING
RBO
RBI
En
RBO
RBI
En
RBO
RBI
En
RBO
RBI
En
RBO
RBI
En
RBO
En
Figure 3. Leading and Trailing Zero Suppression

with PWM Intensity Blanking and No Lamp Test
N4
N3
RBO
RBI
RBI
En
N2
RBO
En
RBI
N1
RBO
En
RBI
N1
RBO
En
RBI
RBO
En
N2
RBI
RBO
En
N3
RBI
RBO
En
BLANKING
LAMP TEST
Figure 4. Zero Suppression with Lamp Test

and Intensity Blanking
MC14558B
6433
MOTOROLA
MC14560B
NBCD Adder
L SUFFIX
CERAMIC
CASE 620
The MC14560B adds two 4bit numbers in NBCD (natural binary coded
decimal) format, resulting in sum and carry outputs in NBCD code.
This device can also subtract when one set of inputs is complemented with
a 9s Complementer (MC14561B).
All inputs and outputs are active high. The carry input for the least
significant digit is connected to VSS for no carry in.
P SUFFIX
PLASTIC
CASE 648

D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
TRUTH TABLE*
Input
Output
A4
A3
A2
A1
B4
B3
B2
B1
Cin
Cout
S4
S3
S2
S1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
7
15
14
1
2
3
4
5
6
Cin
A1
B1
A2
B2
A3
B3
A4
B4
S1
13
S2
12
S3
11
S4
10
Cout
VDD = PIN 16
VSS = PIN 8
* Partial truth table to show logic operation for representative input values.

MC14560B
6434

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
A2
16
VDD
B2
15
A1
A3
14
B1
B3
13
S1
A4
12
S2
B4
11
S3
Cin
10
S4
VSS
Cout
MC14560B
6435

Characteristic
Symbol

tTLH, tTHL

A or B to S
tPLH, tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
750
330
220
2100
900
675
A or B to Cout
5.0
10
15
650
230
170
1800
600
450
Cin to Cout
5.0
10
15
550
220
160
1500
600
450
ns
ns
TurnOff Delay Time

Cin to S
tPLH = (0.66 ns/pF) CL + 197 ns
tPLH
TurnOn Delay Time

Cin to S
tPHL = (0.66 ns/pF) CL + 197 ns
tPHL
ns
5.0
10
15
800
350
240
2250
975
750
ns
5.0
10
15
650
230
170
1800
600
450
20 ns
ALL INPUTS
20 ns
VDD
90%
50%
10%
1
2f
VSS
20 ns
20 ns
VDD
90%
50%
10%
ANY INPUT
VSS
tPHL
tPLH
VOH
ANY OUTPUT
VOL
Duty Cycle = 50%
ANY OUTPUT
50%
10%
VOH
90%
VOL
All outputs connected to respective CL loads

f = System clock frequency
Figure 1. Power Dissipation Waveforms
MC14560B
6436
tTLH
tTHL
FUNCTIONAL EQUIVALENT LOGIC DIAGRAM

Cin
A1
B1
A2
B2
A3
B3
A4
B4
7
13
15
14
12
S1
S2
1
2
11
S3
3
10
S4
5
9
Cout
VDD = PIN 16
VSS = PIN 8
ADD/SUBTRACT
MC14561B
A1
ZERO
One MC14560B and MC14561B permit a

BCD digit to be added to or subtracted from
a second digit, such as in this typical configuration. A second MC14561B permits either
digit to be added to or subtracted from the
other, or either word to appear unmodified at
the output.
Result
B plus A
B minus A
X = Dont Care
F2
F3
F4
MC14560B
Cin
A1
A2
A3
A4
B1
B2
B3
B4
S1
S2
UNITS
S3
S4
Cout
MC14561B
TRUTH TABLE
Add/Subtract
F1
B1
A10
Zero
A1
A2
A3
A4
COMP
COMP
Z
A1
A2
A3
A4
COMP
COMP
Z
B10
F1
F2
F3
F4
MC14560B
Cin
A1
A2
A3
A4
B1
B2
B3
B4
S1
S2
TENS
S3
S4
Cout
Figure 3. Parallel Add/Subtract Circuit
MC14560B
6437
INTRODUCTION
Frequently in small digital systems, simple decimal arithmetic is performed. Decimal data enters and leaves the system arithmetic unit in a binary coded decimal (BCD) format.
The adder/subtracter in the arithmetic unit may be required
to accept sign as well as magnitude, and generate sign,
magnitude, and overflow. In the past, it has been cumbersome to build sign and magnitude adder/subtracters. Now,
using Motorolas MSI CMOS functions, the MC14560 NBCD
Adders and MC14561 9s Complementers, NBCD adder/
subtracters may be built economically, with surprisingly low
package count and moderate speed.
Some background information on BCD arithmetic is presented here, followed by simple circuits for unsigned adder/
subtracters. The final circuit discussed is an adder/subtracter
for signed numbers with complete overflow and sign correction logic.
DECIMAL NUMBER REPRESENTATION

Because logic elements are binary or twostate devices,
decimal digits are generally represented as a group of bits in
a weighted format. There are many possible binary codes
which can be used to represent a decimal number. One of
the most popular codes using 4 binary digits to represent 0
thru 9 is Natural Binary Coded Decimal (NBCD or 8421
code).
NBCD is a weighted code. If a value of 0 or 1 is assigned to each of the bit positions, where the rightmost position is 20 and the leftmost is 23, and the values are summed
for a given code, the result is equal to the decimal digit represented by the code. Thus, 0110 equals 0@23 + 1@22 + 1@21 +
0@20 = 4 + 2 = 6. The 1010, 1011, 1100, 1101, 1110, and 1111
binary codes are not used. Because of these illegal states,
the addition and subtraction of NBCD numbers is more complex than similar calculations on straight binary numbers.
ADDITION OF UNSIGNED NBCD NUMBERS

When 2 NBCD digits, A and B, and a possible carry, C, are
added, a total of 20 digit sums (A + B + C) are possible as
shown in Table 1.
The binary representations for the digit sums 10 thru 19
are offset by 6, the number of unused binary states, and are
not correct. An algorithm for obtaining the correct sum is
shown in Figure 1. A conventional method of implementing
the BCD addition algorithm is shown in Figure 2(a). The
NBCD digits, A and B, are summed by a 4 bit binary full adder. The resultant (sum and carry) is input to a binary/BCD
code converter which generates the correct BCD code and
carry.
An NBCD adder block which performs the above function
is available in a single CMOS package (MC14560).
MC14560B
6438
Figure 2(b) shows n decades cascaded for addition of n digit

unsigned NBCD numbers. Add time is typically 0.1 + 0.2n s
for n decades. When the carry out of the most significant decade is a logical 1, an overflow is indicated.
COMPLEMENT ARITHMETIC
Complement arithmetic is used in NBCD subtraction. That
is, the complement of the subtrahend is added to the minuend. The complementing process amounts to biasing the
subtrahend such that all possible sums are positive. Consider the subtraction of the NBCD numbers, A and B:
R=AB
where R is the result. Now bias both sides of the equation
by 10N 1 where N is the number of digits in A and B.
R + 10N 1 A B + 10N 1
Rearranging,
R + 10N 1 A + (10N 1 B)
The term (10N 1 B), B biased by 10N 1, is known as
the 9s complement of B. When A > B, R + 10N 1 > 10N 1;
thus R is a positive number. To obtain R, 1 is added to R +
10N 1, and the carry term, 10N, is dropped. The addition of
1 is called End Around Carry (EAC).
When A < B, R + 10N 1 < 10N 1, no EAC results and R
is a negative number biased by 10N 1; thus R + 10N 1 is
the 9s complement of R.
SUBTRACTION OF UNSIGNED NBCD NUMBERS

Nines complement arithmetic requires an element to perform the complementing function. An NBCD 9s complementer may be implemented using a 4 bit binary adder and 4
inverters, or with combinatorial logic. The Motorola MC14561
9s complementer is available in a single package. It has true
and inverted complement disable, which allow straight
through or complement modes of operation. A zero line
forces the output to 0. Figure 3 shows an NBCD subtracter
block using the MC14560 and MC14561. Also shown are n
cascaded blocks for subtraction of n digit unsigned numbers.
Subtract time is 0.6 + 0.4n s for n stages. Underflow (borrow) is indicated by a logical 0 on the carry output of the
most significant digit. A 0 carry also indicates that the difference is a negative number in 9s complement form. If the result is input to a 9s complementer, as shown, and its mode
controlled by the carry out of the most significant digit, the
output of the complementer will be the correct negative magnitude. Note that the carry out of the most significant digit
(MSD) is the input to carry in of the least significant digit
(LSD). This End Around Carry is required because subtraction is done in 9s complement arithmetic.
By controlling the complement and overflow logic with an
add/subtract line, both addition and subtraction are performed using the basic subtracter blocks (Figure 4).
ADDITION AND SUBTRACTION OF SIGNED NBCD

NUMBERS
Table 1. Sum = A + B + C
Binary Sums
Decimal
Numbers
Corrected
Binary Sums
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000 + Carry
0001 + Carry
0010 + Carry
0011 + Carry
0100 + Carry
0101 + Carry
0110 + Carry
0111 + Carry
1000 + Carry
1001 + Carry
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Non valid
1101
BCD
1110
representation
1111
0000 + Carry
0001 + Carry
0010 + Carry
0011 + Carry
Using MC14560 NBCD Adders and MC14561 9s Complementers, a sign and magnitude adder/subtracter can be configured (Figure 5). Inputs A and B are signed positive (AS, BS
= 0) or negative (AS, BS = 1). B is added to or subtracted
from A under control of an Add/Sub line (subtraction = 1).
The result, R, of the operation is positive signed, positive
signed with overflow, negative signed, or negative signed
with overflow. Add/subtract time is typically 0.6 + 0.4n s for
n decades.
An exclusiveOR of Add/Sub line and BS produces B,
which controls the B complementers. If BS, the sign of B, is a
logical 1 (B is negative) and the Add/Sub line is a 0 (add
B to A), then the output of the exclusiveOR (BS) is a logical
1 and B is complemented. If BS = 1 and Add/Sub = 1, B
is not complemented since subtracting a negative number is
the same as adding a positive number. When Add/Sub is a
1 and BS = 0, BS is a 1 and B is complemented. The A
complementer is controlled by the A sign bit, AS. When AS =
1, A is complemented.
THOUSANDS
HUNDREDS
TENS
UNITS
6,941
0110
1001
0100
0001
5,870
0101
1000
0111
0000
ADDER
Cin
4 BIT BINARY ADDERS
DIGIT BINARY SUMS
1011
1100
BINARY SUMS WITH

CARRY FROM CONVERTERS
ADDER
1
1
ADDER
Cin
Cin
0001
0010
ADDER
1011
1011
0001
0001
CODE CONVERTERS
Cout
Cout
Cout
Cout
CORRECTED SUM
12,811
1
0 0 1 0
1 0 0 0
0 0 0 1
0 0 0 1
Figure 4. Unsigned NBCD Addition Algorithm

A
B
A1
Cin
B1
A2
B2
An
Bn
4 BIT BINARY FULL ADDER

Cout
Cin
MC14560
BINARY TO NBCD
CODE CONVERTER
Cout
Cin
MC14560
Cin
Cout
MC14560
Cout
OVERFLOW
R1
RESULT, R
(a) MC14560 Block Diagram
R2
Rn
Typical Add Time = 0.1 + 0.2n s

where n = Number of Decades
(b) nDecade Adder

Figure 5. Addition of Unsigned NBCD Numbers
MC14560B
6439
translated to ASBS Cout. This is equivalent to the majority

function M3(ASBS Cout). Further evaluation of the maps and
truth table reveal that Overflow can be generated by the
exclusiveOR function of End Around Carry and Carry Out.
This analysis results in a minimum device count consisting of
one exclusiveOR package and one dual Majority Logic
package to implement BS, EAC, Sign and Overflow. The
logic connections of these devices are shown in Figure 5.
The output sign, RS, complements the result of the add/
subtract operation when RS = 1. This is required because
the adder performs 9s complement arithmetic. Complementing, when RS indicates the result is negative, restores sign
and magnitude convention.
Several variations of the adder/subtracter are possible.
For example, 9s complement is available at the output of the
NBCD adders, and output complementers are eliminated if
sign and magnitude output is not required.
The truth table and Karnaugh maps for sign, overflow, and
End Around Carry are shown in Figures 6 and 7. Note the
use of BS from the exclusiveOR of Add/Sub and BS. BS
eliminates Add/Sub as a variable in the truth table. As an example of truth table generation, consider an n decade adder/
subtracter where AS = 0, BS = 1, and Add/Sub = 0. B is
in 9s complement form, 10N 1 B. Thus A + (10N 1 B)
= 10N 1 + (A B). There is no carry when A
B, and the
sign is negative (sign = 1). When AS and BS are opposite
states and Add/Sub is a 0 (add mode), no overflow can occur (overflow = 0). The other output states are determined
in a similar manner (see Figure 6).
From the Karnaugh maps it is apparent that End Around
Carry is composed of the two symmetrical functions S2 and
S3 of three variables with AS BS Cout as the center of symmetry. This is the definition of the majority logic function
M3(ABC). Similarly the Sign is composed of the symmetrical
functions S2(3) and S3(3) but with the center of symmetry
A1
VDD
A2
A3
A4
C
MC14561
C
Z
A1
Cn
A2
A3
A4
F2
F3
F4
B1
B2
B3
AB
MC14560
Cin
FROM Cout
OF MOST SIGNIFICANT
DECADE
F1
Cn + 1
Cout
S1
S2
S3
S4
A1
A2
A3
A4
VDD
MC14561
C
Z
F1
F2
F3
F4
RESULT, R
(a) Basic Subtracter Block

A1
LEAST
SIGNIFICANT
DECADE
B1
A2
BASIC
Cin
C
SUBTRACT out
BLOCK
C
B2
An
MOST
SIGNIFICANT
DECADE
Cin
Cout
Bn
Cin
Cout
R1
R1
R2
Rn
Typical Subtract Time = 0.6 + 0.4n s where n = Number of Decades
0 INDICATES
UNDERFLOW
(NEGATIVE RESULT)
(b) nDecade Subtracter

Figure 6. Subtraction of Unsigned NBCD Numbers
MC14560B
6440
SUMMARY
REFERENCES
1. Chu, Y.: Digital Computer Design Fundamentals, New
York, McGrawHill, 1962.
2. McMOS Handbook, Motorola Inc., 1st Edition.
3. Beuscher, H.: Electronic Switching Theory and Circuits,
New York, Van Nostrand Reinhold, 1971.
4. Garrett, L.: CMOS May Help Majority Logic Win Designers Vote, Electronics, July 19, 1973.
5. Richards, R.: Digital Design, New York, Wiley
Interscience, 1971.
The concepts of binary code representations for decimal

numbers, addition, and complement subtraction were discussed in detail. Using the basic Adder and Complementer
MSI blocks, adder/subtracters for both signed and unsigned
numbers were illustrated with examples.
A1
B1
A2
B2
LSD
An
Bn
MSD
Cin
C
BASIC Cout
SUBTRACT
BLOCK
Cin
C
R1
ADD/SUBTRACT
(1/0)
Cout
Cin
Cout
R2
Rn
1/6 MC14572
OVERFLOW = 1
1/6 MC14572
UNDERFLOW = 1
(NEGATIVE RESULT)
Typical Add/Subtract Time = 0.6 + 0.4 n s
Figure 7. Adder/Subtracter for Unsigned NBCD Numbers
MC14560B
6441
MC14560B
6442
A1
A1
A2
B1
A3
A4
A1
A2
A3
A2
B2
An
Bn
MC14561
MC14561
MC14561
MC14561
A4
C
MC14561
MC14561
C
Z
Figure 8. Sign and Magnitude Adder/Subtracter with Overflow
F1
F2
F3
F4
A1
A2
A3
A4
Cin
F1
F2
F3
F4
B1
B2
B3
B4
Cout
MC14560
S1
S2
S3
S4
A1
A2
A3
A4
C
MC14561
MC14560
MC14560
MC14561
MC14561
R2
Rn
Z
F1
F2
F3
F4
R1
EAC
Cout
AS
A
1/4 MC14070
BS
B S
ADD/SUB
1/4 MC14070
B
M5
OVERFLOW
D
E
VDD
MC14530
1/4 MC14070
A
B
C
VDD
M5
Z
SIGN
D
E
Typical Add/Subtract Time = 0.6 + 0.4n s

SIGN OF RS
Cout
Inputs
AS
1 = Neg
BS
1 = Neg
Coutt
1 = Carry
Arithmatic Expression
for R* (Result)
mber of Digits
(N = N
Number
Digits,
10N = Modulus
A B,
A,
B R are Positive
Magnitudes)
R=A+8
R=AB
= A + (10N 1 B)
= A B + 10N 1
R=BA
= B + (10N 1 A)
= B A + 10N 1
R=AB
= (10N 1 A) +
(10N 1 B)
= (A + B) + 2 x
10N 2
Outputs
End Around
Carry (EAC)
1 = EAC
Sign of R
1 = Negative
Overflow
1 = Overflow
No EAC (0)
because R is correct
result.
Since A and B are

positive signed, R is
positive signed (0).
When Cout = 0, there

is no carry (R < 10N)
and thus no overflow
(0).
No EAC (0)
because 9s
complement
expression for R is
correct result.
A
B when Cout =
0; thus sign of R
must be negative
(1).
EAC = 1 because
expression for R is in
error by 1.
A > B when Cout =

1; thus sign of R
must be positive
(0).
No EAC (0)
because 9s
complement
expression for R is
correct result.
B
A when Cout =
0; thus sign of R
must be negative
(1).
EAC = 1 because
error by 1.
B > A when Cout =

1; thus sign of R
must be positive
(0).
EAC = 1 because
9s complement
error by 1.
Since A and B are

negative signed. R is
negative signed (1).

is a carry (R 10N)
and thus overflow
(1).
There is never an
overflow when
numbers of opposite
sign are added.

is no Carry (R < 0N)
and (A + B) > 10N 1
indicating overflow
(1).
is a carry (R 10N)
and (A + B)
10N 1
indicating no overflow
(0).
* Output of Adders
Figure 9. Truth Table Generation for EAC, Sign, and Overflow Logic
MC14560B
6443
KARNAUGH MAPS
TRUTH TABLE
Inputs
Outputs
End Around Carry

AS
AS
BS
Cout
EAC
SGN
OVF
0*
BS = (Add/Sub)
BS
AS = Sign of A (1 = Negative)
BS = Sign of B (1 = Negative)
Cout = Adder Carry Out
Cout
Sign (SGN)
AS
BS
Cout
0*
Overflow (OVF)
AS
BS
Cout
BS
* = Center of Symmetry
EAC = S2 (ASBS Cout) + S3 (ASBS Cout)
= M3 (ASBS Cout)
SGN = S2 (ASBS Cout) + S3 (ASBS Cout)
= M3 (ASBS Cout)
EAC
0
Cout
OVF
Figure 10. Mapping of EAC, Sign and Overflow Logic
MC14560B
6444
MOTOROLA

MC14561B
9's Complementer
L SUFFIX
CERAMIC
CASE 632
The MC14561B 9s complementer is a companion to the MC14560B

NBCD adder to allow BCD subtraction. A BCD number (8421 code) is
applied to the inputs (A1 = 20, A2 = 21, A3 = 22, A4 = 23). If the complement
control (Comp) is low, the BCD number appears at the outputs unmodified.
The complement disable (Comp) allows the complement control to be gated,
or an inverted control signal to be used. If the complement input is high and
the disable input low, the 9s complement of the number is displayed at the
outputs. The zero control (Z), when high, forces the outputs low regardless of
the state of the other inputs.
When the MC14561B is used to perform BCD subtraction in conjunction
with the MC14560B NBCD adder, the complement control becomes an
add/subtract control.
All Inputs Buffered
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
PIN ASSIGNMENT
Vin, Vout
0.5 to VDD + 0.5
A1
14
VDD
Iin, Iout

per Pin
10
mA
A2
13
F1
A3
12
F2
PD
500
mW
A4
11
F3
Tstg
Storage Temperature
65 to + 150
_C
COMP
10
F4
260
_C
COMP
VSS
NC
TL
TRUTH TABLE
Z
Comp
Comp
F1
F2
F3
F4
Mode
A1
A2
A3
A4
Straightthrough
A1
A2
A2A3 + A2A3
A2A3A4
Complement
Zero
X = Dont Care.
NC = NO CONNECTION

to the range VSS
(Vin or Vout)
VDD.
MC14561B
6445

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
MC14561B
6446

Characteristic
Symbol

tTLH,
tTHL

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
400
160
120
1000
400
300
Unit
ns
ns
20 ns
ANY INPUT
20 ns
VDD
90%
50%
10%
VSS
tPLH
tPHL
90%
ANY OUTPUT
VOH
50%
10%
VOL
tTLH
tTHL
MC14561B
6447
LOGIC DIAGRAM
A1
1
F1
13
A2
2
F2
12
F3
11
A3
3
F4
10
A4
4
COMP
5
VDD = PIN 14
VSS = PIN 7
COMP
6
Z
9
TRUTH TABLE COMPLEMENT MODE

(Z = 0, Comp = 1, Comp = 0)
Illegal
BCD
Input
Codes
MC14561B
6448
Decimal
Equivalent
Eq
ivalent
Input
A1
Decimal
Equivalent
Eq
ivalent
Output
A4
A3
A2
F4
F3
F2
F1
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
10
11
12
13
14
15
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
7
6
5
4
3
2
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
Inputs
Outputs
One MC14560B and one MC14561B permit a BCD digit to
be added to or subtracted from a second digit, such as in
the typical configurations in Figures 2 and 3. A second
MC14561B permits either digit to be added to or subtracted

from the other, or either word to appear unmodified at the
output.
ADD/SUBTRACT
MC14561B
A1
A1
F1
A3
F2
Cin
A1
S1
F3
A2
S2
A4
COMP
A3
COMP
ZERO
MC14560B
A2
F4
B1
UNITS
A4
B1
S3
B2
S4
B3
Cout
MC14561B
A1
A10
F1
A3
F2
Cin
A1
S1
F3
A2
S2
A4
COMP
Z
TENS
A3
COMP
B10
MC14560B
A2
F4
A4
B1
S3
B2
S4
B3
B4
Cout
TRUTH TABLE
Zero
Add/Subtract
Result
B plus A
B minus A
X = Dont Care
Figure 2. Parallel Add/Subtract Circuit (10s Complement)
MC14561B
6449
TYPE D
FLIPFLOP
D
C
ADD/SUBTRACT
A REGISTER
100s
10s
MC14561B
1s
A1
A2
A3
A4
COMP
COMP
Z
F1
F2
F3
F4
CLOCK
100s
10s
1s
MC14560B
Cin
A1
A2
A3
A4
B1
B2
B3
B4
S1
S2
RESULT
S3
S4
Cout
B REGISTER
Figure 3. Serial Add/Subtract Circuit
MC14561B
6450
MOTOROLA
MC14562B
L SUFFIX
CERAMIC
CASE 632
The MC14562B is a 128bit static shift register constructed with MOS

monolithic structure. Data is clocked in and out of the shift register on the
positive edge of the clock input. Data outputs are available every 16 bits,
from 16 through bit 128. This complementary MOS shift register is primarily
used where low power dissipation and/or high noise immunity is desired.
P SUFFIX
PLASTIC
CASE 646

Cascadable to Provide Longer Shift Register Lengths
D SUFFIX
SOIC
CASE 751A
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
12
LOGIC DIAGRAM
DATA
CLOCK
Pins 4 and 11
not used.
CLOCK 5
Q16
Q32
Q48
Q64
Q80
Q96
Q112
Q128
10
13
9
1
8
2
6
3
VDD = PIN 14
VSS = PIN 7
DATA IN 12
DQ
C
1
D Q
C
2
DQ
C
3
DQ
C
16
D Q
C
17
DQ
C
32
D Q
C
33
DQ
C
48
D Q
C
49
DQ
C
64
10 Q16
DQ
C
65
D Q
C
80
DQ
C
81
D Q
C
96
DQ
C
97
DQ
C
112
D Q
C
113
DQ
C
128
13 Q32
9 Q48
1 Q64
8 Q80
2 Q96
6 Q112
3 Q128
MC14562B
6451

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 05 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

PIN ASSIGNMENT
Q64
14
VDD
Q96
13
Q32
Q128
12
DATA
NC
11
NC
CLOCK
10
Q16
Q112
Q48
VSS
Q80
NC = NO CONNECTION
MC14562B
6452

Characteristic
Symbol

tTLH,
tTHL

Clock to Q
tPLH,
tPHL
Clock Pulse Width

(50% Duty Cycle)
Data to Clock Setup Time
Data to Clock Hold Time
Clock Input Rise and Fall Times
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
600
250
170
1200
500
340
tWH
5.0
10
15
600
220
150
300
110
75
ns
fcl
5.0
10
15
1.9
5.6
8.0
1.1
3.0
4.0
MHz
tsu(1)
5.0
10
15
20
10
0
170
64
60
ns
tsu(0)
5.0
10
15
20
10
0
91
58
48
ns
th(1)
5.0
10
15
350
165
155
263
109
100
ns
th(0)
5.0
10
15
350
200
140
267
140
93
ns
tr, tf
5.0
10
15
15
5
4
VDD
Q16
Q32
Q48
Q64
Q80
Q96
Q112
Q128
DATA
CLOCK
CL
VSS
CL
CL
CL
CL
CL
CL
CL
500 F
ID
fo
CLOCK
VDD
DATA
(f = 1/2 fo)
VDD
VSS
VSS
MC14562B
6453
TIMING DIAGRAM
PIN
NO.S
PULSE 16
PULSE 1
PULSE 32
PULSE 128
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28 3
AC TEST WAVEFORMS
PULSE 1
CLOCK
50%
50%
PULSE 2
50%
tWH
tr
tWL
DATA IN
PULSE 16
90%
10%
PULSE 17
VSS
tf
VDD
50%
50%
VSS
tsu(0)
th(0)
50% 10%
Q16
tPHL
PULSE 1
CLOCK
VDD
50%
50%
50%
PULSE 2
90%
VSS
tTHL
PULSE 17
PULSE 16
VDD
50%
50%
VSS
tWH
tWL
DATA IN
50%
tsu(1)
VDD
VDD
50%
VSS
th(1)
50%
Q16
tPLH
90%
10%
VDD
VSS
tTHL
NOTE: The remaining DataBit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
MC14562B
6454
MOTOROLA
Industrial Time Base Generator
MC14566B
The MC14566B industrial time base generator is constructed with MOS

monolithic structure. This device consists of a divideby10 ripple counter
and a divideby5 or divideby6 ripple counter to permit stable time
generation from a 50 or 60 Hz line. By cascading this device as divideby60
counters, seconds and minutes can be counted and are available in BCD
format at the circuit outputs. An internal monostable multivibrator is included
whose output can be used as a reset or clock pulse providing additional
frequency flexibility. Also a pin has been included to allow divideby5
counting for generating 1.0 Hz from European 50 Hz line. Pin 11 = VDD will
cause 5.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Negative Edge Triggered Counters for Ease of Cascading

Pulse Shapers on Counter Inputs Accept Slow Input Rise Times
Monostable Multivibrator Positive or Negative Edge Triggered
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
PIN ASSIGNMENT
0.5 to + 18.0
CA
16
VDD
Vin, Vout
0.5 to VDD + 0.5
RESET
15

per Pin
10
CB
Iin, Iout
mA
Q0A
14
Q2B
Q1A
13
Q1B
Q2A
12
Q0B
Q3A
11
B5/B6
10
Qm
VSS
PD
Tstg
Storage Temperature
500
65 to + 150
mW
_C
TL
260
_C
BLOCK DIAGRAM
CA
10
PULSE
SHAPER
Q0A
Q1A
C
R
RESET
5/ 6 CONTROL
Q2A
Q3A
B
A
5
6
BCD
OUT
2
R
11
Q0B
Q1B
CB
5/ 6
3
4
15
PULSE
SHAPER
7
9
Q2B
12
13
14
BCD
OUT
MONO
STABLE
MULTI
VIBRATOR
10
Qm
MC14566B
6455

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14566B
6456

Characteristic
Symbol

tTLH,
tTHL
Propagation Delay Time, Clock to Q3A

tPLH,
tPHL
Propagation Delay Time, Reset to Q3A

tPHL = (0.66 ns/pF) CL + 282 ns
tPHL
Clock Pulse Width
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
1450
530
320
4500
1500
1000
5.0
10
15
930
315
210
3000
1000
750
5.0
10
15
1200
400
270
400
125
90
5.0
10
15
1200
400
270
400
125
90
5.0
10
15
1.0
2.5
4.2
0.3
1.0
1.5
ns
ns
ns
tWH(cl)
Reset Pulse Width
ns
tWH(R)
ns
fcl
MHz
tTLH,
tTHL
5.0
10
15
No Limit
tWH(Qm)
Monostable Multivibrator Pulse Width
Unit
ns
5.0
10
15
1200
400
300
2800
900
600
VDD
20 ns
20 ns
VDD
90%
50%
10%
500 F
ID
Vin
VSS
VARIABLE
WIDTH
Vin
PULSE
GENERATOR
CA
CB
RESET
5/ 6
CONTROL
B
A
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Qm
VSS
CL
CL
CL
CL
CL
CL
CL
CL
MC14566B
6457
VDD
CA
PROGRAMMABLE
PULSE
GENERATOR
CB
RESET
5/ 6
CONTROL
B
A
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Qm
CL
VSS
CL
CL
CL
CL
CL
CL
CL
NOTE: Assume 10 Counter at 6 and 5/ 6 Counter at 2 at beginning of sequence.

20 ns
10 OR 5/ 6 90%
CLOCK AND B
tWH(cl)
50%
10%
fcl
20 ns
90%
RESET
Q3A OR
Q2B
10%
tPLH
tWH(R)
tPHL
90%
10%
tPLH
50%
tTLH
50%
Qm
50%
tWH(Qm)
tTHL
50%
t WHQm
MC14566B
6458
TIMING DIAGRAM
DivideBy10 Counter
0
CLOCK
RESET
Q0
Q1
Q2
Q3
DivideBy5/DivideBy6
0
CLOCK
RESET
CONTROL
5/ 6
Q0
Q1
Q2
Monostable Multivibrator
Qm
= DONT CARE
MC14566B
6459
APPLICATION 12 HOUR CLOCK
5/ 6
< 1.0 M*
Q0
Q1
Q2
Q3
Q0
60 Hz
10
C
Q1
> 1500 pF*
Q2
10
C
A
B
Qm
+ VDD
Q0
Q1
Qm
Q2
SECONDS
10
5/ 6
Q0
Q1
Q2
Q3
TENTH
SECONDS
5/ 6
Q0
Q1
Q2
Q3
VDD
Q0
Q1
Qm
Q2
MINUTES
A
B
C
MC14011B
10
Q0
C
Q1
Q2
R Q3
5/ 6
C
HOURS
Q0
Q1
Qm
R Q2
5/ 6 Control not shown = VSS

Reset pins not shown = VSS
* Care must be taken in the indicated circuit to filter line
transients which may cause false counting.
MC14566B
6460
MOTOROLA
MC14568B
Phase Comparator and

Programmable Counters
L SUFFIX
CERAMIC
CASE 620
The MC14568B consists of a phase comparator, a divideby4, 16, 64 or

100 counter and a programmable dividebyN 4bit binary counter (all
positiveedge triggered) constructed with MOS Pchannel and Nchannel
enhancement mode devices (complementary MOS) in a monolithic structure.
The MC14568B has been designed for use in conjunction with a
programmable dividebyN counter for frequency synthesizers and phase
locked loop applications requiring low power dissipation and/or high noise
immunity.
This device can be used with both counters cascaded and the output of
the second counter connected to the phase comparator (CTL high), or used
independently of the programmable dividebyN counter, for example
cascaded with a MC14569B, MC14522B or MC14526B (CTL low).
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Supply Voltage Range = 3.0 to 18 V

Range.
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC

Rating
DC Supply Voltage
Symbol
Value
Unit
VDD
Vin
0.5 to + 18
Vdc
0.5 to VDD + 0.5
Vdc
Iin
PD
10
mAdc
500
mW
TA
Tstg
55 to + 125
_C
65 to + 150
_C
TRUTH TABLE
F
Pin 10
G
Pin 11
Division Ratio
of Counter D1
0
0
1
1
0
1
0
1
4
16
64
100
The divide by zero state on the programmable dividebyN 4bit binary

counter, D2, is illegal.
BLOCK DIAGRAM
PCin 14
13 PCout
PHASE
COMPARATOR
(REF.)
B
12 LD
TG
CTL HIGH
TG
CTL LOW
11 G
C1 9
10 F
P/C
CTL 15
TG
PE 2
PCout
LD
D2
DP3
5
6
DP2 DP1
P/C
LD
C1
D1
D2
1 Q1/C2
0
VDD = PIN 16
VSS = PIN 8
PCin
C1
D1
4BIT
PROGRAMMABLE
COUNTER D2
0 3
PCout
PCin
COUNTER D1
Q1/C2
Q1/C2
DP0
MC14568B
6461

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
Iout = 0 A
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15

Pins 1, 13
ITL
15
Vin = 0 or VDD
Input Voltage#
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
#Noise immunity for worst input combination.

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
IT(CL) = IT(50 pF) + 1 x 103 (CL 50) VDDf
Pin 15 is connected to VSS or VDD for input voltage test.
PIN ASSIGNMENT
MC14568B
6462
Q1/C2
16
VDD
PE
15
CTL
14
PCin
DP3
13
PCout
DP2
12
LD
DP1
11
DP0
10
VSS
C1

Characteristic
Symbol
VDD
V
Min
Typ
Max
Unit
Output Rise Time
tTLH
5.0
10
15
180
90
65
360
180
130
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Minimum Pulse Width, C1, Q1/C2, or PCin Input
tWH
5.0
10
15
125
60
45
250
120
90
ns
Maximum Clock Rise and Fall Time,

C1, Q1/C2, or PCin Input
tTLH,
tTHL
5.0
10
15
15
15
15
Input Resistance
Rin
5.0 to 15
106
Input Sensitivity, dc Coupled
5.0 to 15
TurnOff Delay Time,

PCout and LD Outputs
tPHL
5.0
10
15
550
195
120
1100
390
240
ns
TurnOn Delay Time.

PCout and LD Outputs
tPLH
5.0
10
15
675
300
190
1350
600
380
ns
5.0
10
15
3.0
8.0
10
6.0
16
22
5.0
10
15
1.0
3.0
50
2.5
6.3
9.7
5.0
10
15
450
190
130
900
380
260
5.0
10
15
720
300
200
1440
600
400
fcl
5.0
10
15
1.2
3.0
4.0
1.8
8.5
12
MHz
TurnOn Delay Time, 0 Output

(Figure 3a)
tPLH
5.0
10
15
450
190
130
900
380
260
ns
TurnOff Delay Time, 0 Output

(Figure 3a)
tPHL
5.0
10
15
225
85
60
450
170
150
ns
tWH(PE)
5.0
10
15
75
40
30
250
100
75
ns
PHASE COMPARATOR
See Input Voltage
DIVIDEBY4, 16, 64 OR 100 COUNTER (D1)

Maximum Clock Pulse Frequency
Division Ratio = 4, 64 or 100
fcl
Division Ratio = 16
Propagation Delay Time, Q1/C2 Output

Division Ratio = 4, 64 or 100
tPLH,
tPHL
Division Ratio = 16
MHz
ns
PROGRAMMABLE DIVIDEBYN 4BIT COUNTER (D2)

Maximum Clock Pulse Frequency
(Figure 3a)
Minimum Preset Enable Pulse Width
MC14568B
6463
SWITCHING TIME TEST CIRCUITS AND WAVEFORMS

VDD
A LAGS B, PCout IS LOW.
VDD
2
0out REF
B
10 k
CTL
DP0
DP1
DP2
DP3
PCin
F
G
C1
PE
PULSE
GENERATOR 1
PULSE
GENERATOR 2
A LEADS B, PCout IS HIGH.
50%
20 ns
20 ns
PCout
LD
CL
PCin
PG1
CL
tW(PCin)
90%
50%
10%
A
tPLH
tPLH
tTHL
Q1/C2
tPLH
90%
LD
10%
tPHL
THREESTATE
PCout
VSS
Figure 1. Phase Comparator
tTLH
tPHL
75%
THREESTATE
25%
VOH
VOL
tPHL
tPLH
VDD
CTL
DP0
DP1
DP2
DP3
PCin
F
G
C1
PE
PULSE
GENERATOR
20 ns
C1
10%
90%
50%
fin fmax
tPHL
Q1/C2
CL
Q1/C2
10%
90%
50%
tTLH
VSS
tTHL
Figure 2. Counter D1
VDD
DP0
DP1 PCout
DP2
LD
DP3
Q1/C2
PCin
F
G
0
C1
CTL
PE
VSS
PULSE
GENERATOR
tW(C1)
20 ns
PCout
LD
PULSE
GENERATOR 1
PULSE
GENERATOR 2
VDD
DP0
DP1 PCout
DP2
LD
DP3
Q1/C2
PCin
F
G
0
C1
CTL
PE
CL
CL
VSS
N PULSES*
20 ns
Q1/C2
Q1/C2 = PG 1
20 ns
tPHL
10%
50%
20 ns
90%
50%
10%
tPLH
tW(Q1/C2)
20 ns
fin fmax
PE = PG2
90%
50%
90%
50%
10%
tW(PE)
tTLH
tTHL
0
* N is the value programmed on the DP Inputs.
a.
MC14568B
6464
Figure 3. Counter D2
b.
LOGIC DIAGRAM
PCin
14
13
B (REF.)
PCout
LD
C
C
COUNTER
D1
9
C1
10
F
11
G
1
Q1/C2
15
CTL
3
0
PE
2
PE
COUNTER
D2
C
Q
D
VDD = PIN 16
VSS = PIN 8
4
DP3
5
DP2
6
DP1
7
DP0
MC14568B
6465
Typical Maximum Frequency Divider D1

Division ratios: 4, 64 or 100 (CL = 50 pF)

Division ratio: 16 (CL = 50 pF)
12
26
10
f, FREQUENCY (MHz)
28
24
22
20
f, FREQUENCY (MHz)
VDD = 15 V
VDD = 15 V
6
VDD = 10 V
4
18
16
0
40
VDD = 5 V
20
14
+ 20
+ 40
+ 60
T, TEMPERATURE (C)
+ 80
+ 100
VDD = 10 V
12

Division ratio: 2 (CL = 50 pF)
10
6
8
5
VDD = 5 V
4
2
0
40
20
+ 20
+ 40
+ 60
T, TEMPERATURE (C)
+ 80
+ 100
f, FREQUENCY (MHz)
6
4
VDD = 15 V
3
VDD = 10 V
2
0
40
MC14568B
6466
VDD = 5 V
20
+ 20
+ 40
+ 60
T, TEMPERATURE (C)
+ 80
+ 100
The MC14568B contains a phase comparator, a fixed
divider ( 4, 16, 64, 100) and a programmable divide
byN 4bit counter.
PHASE COMPARATOR
The phase comparator is a positive edge controlled logic
circuit. It essentially consists of four flipflops and an output
pair of MOS transistors. Only one of its inputs (PCin, pin 14)
is accessible externally. The second is connected to the output of one of the two counters D1 or D2 (see block diagram).
Duty cycles of both input signals (at A and B) need not be
taken into consideration since the comparator responds to
leading edges only.
If both input signals have identical frequencies but different
phases, with signal A (pin 14) leading signal B (Ref.), the
comparator output will be high for the time equal to the
phased difference.
If signal A lags signal B, the output will be low for the same
time. In between, the output will be in a threestate condition
and the voltage on the capacitor of an RC filter normally connected at this point will have some intermediate value (see
Figure 4). When used in a phase locked loop, this value will
adjust the Voltage Controlled Oscillator frequency by reducing the phase difference between the reference signal and
the divided VCO frequency to zero.
VDD
VSS
A (PCin)
1/f
VOH
VOL
VOH
B (REF.)
LD
VOL
VOH
PCout
VOL
Figure 4. Phase Comparator Waveforms
If the input signals have different frequencies, the output

signal will be high when signal B has a lower frequency than
signal A, and low otherwise.
Under the same conditions of frequency difference, the
output will vary between VOH (or VOL) and some intermediate value until the frequencies of both signals are equal and
their phase difference equal to zero, i.e. until locked condition
is obtained.
Capture and lock range will be determined by the VCO frequency range. The comparator is provided with a lock indicator output, which will stay at logic 1 in locked conditions.
The state diagram (Figure 5) depicts the internal state
transitions. It assumes that only one transition on either signal occurs at any time. It shows that a change of the output
state is always associated with a positive transition of either
signal. For a negative transition, the output does not change
state. A positive transition may not cause the output to
change, this happens when the signals have different frequencies.
DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1)

This counter is able to work at an input frequency of 5 MHz
for a VDD value of 10 volts over the standard temperature
range when dividing by 4, 64 and 100. Programming is accomplished by use of inputs F and G (pins 10 and 11) according to the truth table shown. Connecting the Control
input (CTL, pin 15), to VDD allows cascading this counter with
the programmable dividebyN counter provided in the
same package. Independent operation is obtained when the
Control input is connected to VSS.
The different division ratios have been chosen to generate
the reference frequencies corresponding to the channel
spacings normally required in frequency synthesizer applications. For example. with the division ratio 100 and a 5 MHz
crystal stabilized source a reference frequency of 50 kHz is
supplied to the comparator. The lower division ratios permit
operation with low frequency crystals.
INPUT STATE
00
01
X X
10
11
00
10
00
01
01
11
10
11
PCout
3STATE
OUTPUT DISCONNECTED
LD
(LOCK DETECT)
Figure 5. Phase Comparator State Diagram
MC14568B
6467
If used in cascade with the programmable dividebyN

counter, practically all usual reference frequencies, or channel spacings of 25, 20, 12.5, 10, 6.25 kHz, etc. are easily
achievable.
(pins 7 ... 4). The Preset Enable input enables the parallel
preset inputs DP0... DP3. The 0 output must be externally
connected to the PE input for single stage applications.
Since there is not a cascade feedback input, this counter,
when cascaded, must be used as the most significant digit.
Because of this, it can be cascaded with binary counters as
well as with BCD counters (MC14569B, MC14522B,
MC14526B).
PROGRAMMABLE DIVIDEBYN
4BIT COUNTER (D2)
This counter is programmable by using inputs DP0 ... DP3
fin
CF
MC14569B
ZERO DETECT
PE
CF
MC14522B
OR
MC14526B
Q4
PE
DP0 DP3
CF
MC14522B
OR
MC14526B
Q4
Q1/C2
PE
MC14568B
DP0 DP3
DP0 DP3
LSD
fout
MSD
Figure 6. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
PCin
C1
CTI
VSS
MC14568B
fout
VCO
PCout
G
(144 146 MHz)
VSS
VSS
F
Q1/C2
PE
VDD
DP0 DP3
MC14011
Q
CF
MC14569B
ZERO DETECT
C
MIXER
2k
2M
CRYSTAL
OSCILLATOR
Frequencies shown in parenthesis are given as an example.
(143.5 MHz)
Figure 7. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)
MC14568B
6468
PCin
C1
(5 MHz)
(VDD)
CTL
0
MC14568B
PCout
G
F
PE
VDD
VDD
VDD
VSS
fout
VCO
MC14569B
MC14522B
DP0 DP3
CF
ZERO DETECT
0
PE
(BCD)
BINARY
DP0 DP3
N1
(0 5)
(625 kHz STEPS)
N2
(0 9)
(62.5 kHz STEPS)
N3
(0, 4, 8, 12)
(6.25 kHz STEPS)
Divide ratio = 160N1 + 16N2 + N3
Figures shown in parenthesis refer to example.
Example:
Recommended reading:
fout = N1 (MHz) + N2 (x 100 kHz) + N3 (x25 kHz)

Frequency range = 5 MHz
(1) AN535: PhaseLock Techniques

(2) AR254: PhaseLocked Loop Design Articles
Channel spacing = 25 kHz

Reference frequency = 6.25 kHz
Figure 8. Frequency Synthesizer Using MC14568B, MC14569B and MC14522B

(Without Mixer)
MC14568B
6469
MC14568B
6470
26.96527.255
(28.605) MHz
RECEIVER
SECOND MIXER
RECEIVER
FIRST MIXER
10.695 MHz
Figure 9. Typical 23Channel CB Frequency Synthesizer for

Double Conversion Transceivers
TO 455 kHz
IF
RF
AMP
16.27016.560 (17.910) MHz
LOCK DETECTOR
MC14568B
REFERENCE
OSCILLATOR
64
LOOP LOW
PASS FILTER
VCO
10 kHz
10.24 MHz
X3
.911.20 (2.55) MHz
N = 91120 (255) MHz
N
MC14526B
NOTE:
1. 10 kHz Channel Spacing
2. Expandable to 165 Channels
(Expanded frequency range
shown in parenthesis)
TRX
VDD
OSCILLATOR
(TRASMIT ONLY)
RCV
10.695 MHz
DOWN
MIXER
MIXER
TO TRANSMITTER
26.96527.255
(28.605) MHz
MOTOROLA
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
L SUFFIX
CERAMIC
CASE 620
The MC14569B is a programmable dividebyN dual 4bit binary or BCD

down counter constructed with MOS Pchannel and Nchannel enhancement mode devices (complementary MOS) in a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phaselocked loops, and
other frequency division applications requiring low power dissipation and/or
high noise immunity.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
Speedup Circuitry for Zero Detection

Each 4Bit Counter Can Divide Independently in BCD or Binary Mode
Can be Cascaded With MC14568B, MC14522B or MC14526B for
Frequency Synthesizer Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
BLOCK DIAGRAM
P0 P1 P2 P3
CTL = Low for Binary Count
CTL = High for BCD Count
CLOCK
CASCADE 7
FEEDBACK
BINARY/BCD
COUNTER #1
CTL1 CTL2
2
10
P4 P5 P6 P7
11 12 13
CLOCK
LOAD
ZERO DETECT ENCODER
14
BINARY/BCD
COUNTER #2
VDD = PIN 16
VSS = PIN 8
15
1 ZERO
DETECT
MC14569B
6471

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
Vdc
mAdc

Adc
be left open.
MC14569B
6472

Characteristic
Symbol
All Types
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
TurnOn Delay Time

Zero Detect Output
tPLH
5.0
10
15
420
175
125
700
300
250
5.0
10
15
675
285
200
1200
500
400
5.0
10
15
380
150
100
600
300
200
5.0
10
15
530
225
155
1000
400
300
ns
tWH
5.0
10
15
300
150
115
100
45
30
ns
fcl
5.0
10
15
3.5
9.5
13.0
2.1
5.1
7.8
MHz
tTLH, tTHL
5.0
10
15
Q Output
TurnOff Delay Time

Zero Detect Output
ns
ns
tPHL
Q Output
Clock Pulse Width
ns
NO LIMIT
SWITCHING WAVEFORMS
20 ns
20 ns
CLOCK
10%
90%
50%
fin = fmax
tWH
tPLH
Q
10%
tPHL
90%
50%
tTLH
tTHL
Figure 1.
20 ns
20 ns
CLOCK
10%
90%
50%
tWH
tPLH
tPHL
90%
ZERO DETECT
10%
tTLH
tTHL
Figure 2.
MC14569B
6473
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) Preset Inputs. Programmable inputs for the least significant counter. May be binary
or BCD depending on the control input.
Cascade Feedback (Pin 7) This pin is normally set

high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are dont cares. Refer to
Table 1 for output characteristics.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) Preset Inputs. Programmable inputs for the most significant counter. May be
binary or BCD depending on the control input.
Clock (Pin 9) Preset data is decremented by one on
each positive transition of this signal.
OUTPUTS
CTL1 (Pin 2) This pin controls the counting mode of the

least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10) This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
Zero Detect (Pin 1) This output is normally low and

goes high for one clock cycle when the counter has decremented to zero.
VSS (Pin 18) Negative Supply Voltage. This pin is usually connected to ground.
Q (Pin 15) Output of the last stage of the most significant counter. This output will be inactive unless the preset
input P7 has been set high.
VDD (Pin 16) Positive Supply Voltage. This pin is connected to a positive supply voltage ranging from 3.0 volts to
18.0 volts.
The MC14569B is a programmable dividebyN dual 4bit
down counter. This counter may be programmed (i.e., preset) in BCD or binary code through inputs P0 to P7. For each
counter, the counting sequence may be chosen independently by applying a high (for BCD count) or a low (for binary
count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a division ratio of one is not possible. After N clock cycles, one
pulse appears on the Zero Detect output. (See Timing Diagram.) The Q output is the output of the last stage of the most
significant counter (See Tables 1 through 5, Mode Controls.)
When cascading the MC14569B to the MC14568B,
MC14522B or the MC14526B, the Cascade Feedback input,
Q, and Zero Detect outputs must be respectively connected
to 0, Clock, and Load of the following counter. If the
MC14569B is used alone, Cascade Feedback must be connected to VDD.
18
CL = 50 pF
f, FREQUENCY (MHz), TYPICAL
16
PIN ASSIGNMENT
14
12
VDD = 15 V
10
8.0
10 V
6.0
4.0
5.0 V
2.0
0
40
20
MC14569B
6474
0
+ 20
+ 40
+ 60
+ 80
ZERO
DETECT
CTL1
16
VDD
15
P0
14
P7
P1
13
P6
P2
12
P5
P3
CASCADE
FEEDBACK
VSS
11
P4
10
CTL2
CLOCK
+ 100
Table 1. Mode Controls (Cascade Feedback = Low)

Counter Control Values
Divide Ratio
CTL1
CTL2
Zero Detect
0
0
1
1
0
1
0
1
256
160
160
100
256
160
160
100
NOTE: Data Preset Inputs (P0P7) are Dont Cares while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
256
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
32
64
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
27
1
26
128
64
Comments
Max Count
Illegal State
Min Count
127
128
256
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128
136
136
1
25
1
24
1
23
1
22
1
21
1
20
255
255
32
16
Counter #2
Binary
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
MC14569B
6475
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Divide Ratio
Preset Inputs
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19
20
30
40
50
60
70

Comments
Max Count
Illegal State
Min Count
80
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
90
90
150
150
159
159
80
40
20
10
Counter #2
Binary
Counter #1
BCD
Q Output Active
Bit Value
Counting
Sequence
MC14569B
6476
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Divide Ratio
Preset Values
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
31
32

Comments
Max Count
Illegal State
Min Count
48
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64
80
112
128
128
144
144
1
27
0
26
0
25
1
24
1
23
1
22
1
21
1
20
159
159
64
32
16
128
Counter #2
BCD
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
MC14569B
6477
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Divide Ratio
Preset Values
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
30
40
50
70
80
40
Comments
Max Count
illegal state
Min Count
80
100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
90
90
99
99
20
10
Counter #2
BCD
Q Output Active
Bit Value
Counter #1
BCD
Counting
Sequence
TIMING DIAGRAM MC14569B
CLOCK
10
11
12
13
14
15
16
DIVIDE
BY 2
ZERO
DETECT
OUTPUT
DIVIDE
BY 3
DIVIDE
BY 4
DIVIDE
BY 12
MC14569B
6478
LOGIC DIAGRAM
CTL1
2
DP Q
D
DP Q
P0
P1
P2
D
DP Q
P3
PE
C
PE
C
DP Q
PE
DP Q
D
PE
C
DP Q
D
DP Q
D
DP Q
D
IU
PE
C
PE
C
PE
C
PE
C
VDD
CASCADE 7
FEEDBACK
CLOCK
P4
P5
P6
P7
CTL2
11
12
13
14
VDD
9
1 ZERO
DETECT
DP D
Q
PE
DP D
Q
PE
DP D
Q
PE
DP D
Q
PE
10
15
MC14569B
6479
fin
CF
MC14569B
ZERO DETECT
PE
CF
MC14522B
OR
MC14526B
Q4
PE
DP0 DP3
CF
MC14522B
OR
MC14526B
Q4
Q1/C2
PE
MC14568B
DP0 DP3
DP0 DP3
LSD
fout
MSD
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
PCin
C1
CT1
VSS
fout
VCO
PCout
G
(144 146 MHz)
VSS
VSS
F
Q1/C2
PE
VDD
DP0 DP3
MC14011
CF
MC14569B
ZERO DETECT
MIXER
2k
2M
CRYSTAL
OSCILLATOR
Frequencies shown in parenthesis are given as an example
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer

(Channel Spacing 10 kHz)
MC14569B
6480
MOTOROLA
MC14572UB
Hex Gate
L SUFFIX
CERAMIC
CASE 620
The MC14572UB hex functional gate is constructed with MOS Pchannel

These complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. The chip contains four
inverters, one NOR gate and one NAND gate.

NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND Application

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
500
mW
65 to + 150
_C
260
_C
CIRCUIT SCHEMATIC
VDD
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
2
10
12
11
VDD
VDD
7
2
13
14
13
15
6
VSS
VDD = PIN 16
VSS = PIN 8
14
15
VSS
VSS
MC14572UB
6481

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc

MC14572UB
6482
PIN ASSIGNMENT
OUTA
16
VDD
INA
15
IN 2F
OUTB
14
IN 1F
INB
13
OUTF
OUTC
12
INE
IN 1C
11
OUTE
IN 2C
10
IND
VSS
OUTD

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
90
50
40
180
100
80
Unit
ns
ns
ns
VDD
VDD
PULSE
GENERATOR
INPUT
7
16
INPUT
2
PULSE
GENERATOR
OUTPUT
16
OUTPUT
1
8
VSS
CL
VSS
CL
VDD
20 ns
16
PULSE
GENERATOR
INPUT
15
INPUT
14
OUTPUT
VSS
90%
50%
10%
tPHL
13
8
90%
50%
10%
CL
OUTPUT
20 ns
VDD
VSS
tPLH
90%
50%
10%
90%
50%
10%
tf
tr
VOH
VOL
MC14572UB
6483
MOTOROLA
MC14580B
4 x 4 Multiport Register
L SUFFIX
CERAMIC
CASE 623
The MC14580B is a 4 by 4 multiport register useful in small scratch pad

memories, arithmetic operations when coupled with an adder, and other data
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.
Address changing and data entry occur on the rising edge of the clock.
When the write enable input is low, the contents of any word may be
accessed but not altered.
No Restrictions on Clock Input Rise or Fall Times

3State Outputs
Single Phase Clocking
Capable of Driving Two Lowpower TTL Loads or one Lowpower
Pin Compatible with CD40108
DW SUFFIX
SOIC
CASE 751E

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
Tstg
Storage Temperature
TL
16
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Q3B
24
VDD
23
Q1B
500
mW
Q2B
65 to + 150
_C
3STATE A
22
Q0B
260
_C
Q0A
21
3STATE B
Q1A
20
D0
Q2A
19
D1
Q3A
18
D2
CLOCK
P SUFFIX
PLASTIC
CASE 709
WRITE 0
17
D3
BLOCK DIAGRAM
WRITE 1
16
CLOCK
W0 W1 R0A R1A R0B R1B

8 9 13 14 11 10
READ 1B
10
15
WE
READ 0B
11
14
READ 1A
VSS
12
13
READ 0A
DECODER
3STATE A
3
WE
DATA
INPUT
15
20
D0
19
D1
18
D2
17
D3
4X4
MEMORY
VDD = PIN 24
VSS = PIN 12
MC14580B
6484
Q0A
Q1A
Q2A
Q3A
4
5
6
7
22
Q0B
23
Q1B
2
Q2B
1
Q3B
WORD A
OUTPUT
WORD B
OUTPUT
21
3STATE B

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.010
0.020
0.030
5.0
10
20
150
300
600
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
0.1
Adc
3.0
Adc
be left open.
MC14580B
6485

Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
tPLH, tPHL
(Figures 3 and 6)
5.0
10
15
650
250
170
1300
500
340
ns
Write Enable Setup Time

(Enabling a Write or Read)
tsu
(Figure 5)
5.0
10
15
800
300
200
400
150
100
ns
Write Enable Removal Time

(Disabling a Write or Read)
trem
(Figure 5)
5.0
10
15
0
0
0
100
50
35
ns
Setup Time**
Address, Data to Clock
tsu
(Figure 3)
5.0
10
15
50
30
25
20
0
0
ns
Hold Time**
Clock to Address, Data
th
(Figure 3)
5.0
10
15
480
195
150
160
65
50
ns
tPHZ, tPLZ
tPZH, tPZL
(Figures 4 and 7)
5.0
10
15
130
60
45
260
120
90
ns
tw
(Figure 3)
5.0
10
15
820
330
220
410
165
110
ns

(Figures 3 and 6)

Clock to Output
3State Enable/Disable Delay Time
Clock Pulse Width
Unit
tTLH, tTHL
ns
** When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected
and data is valid after the propagation delays listed in the Switching Characteristics Table.
VDD
PULSE
GENERATOR
VDD
VSS
1
2
S1
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
Vout
Q0A
Q1A
IDS
Q2A
Q3A
Q0B
Q1B
Sink Current
EXTERNAL
POWER
SUPPLY
Source Current
Position of S1
VGS =
VDS =
VDD
Vout
VDD
Vout VDD
Q2B
Q3B
VSS
Figure 1. Output Drive Current Test Circuit
MC14580B
6486
VDD
IDD
WE
W0
W1
R0A
R1A
R0B
R1B
C
D0
D1
D2
D3
PULSE
GENERATOR
1
PULSE
GENERATOR
2
PULSE
GENERATOR
3
Q0A
REPETITIVE WAVEFORMS
CL
Q1A
CL
Q2A
P.G. 1
CL
Q3A
CL
Q0B
P.G. 2
CL
Q1B
CL
Q2B
P.G. 3
OUTPUT
Qn A, B
CL
Q3B
CL
VSS
Figure 2. Power Dissipation Test Circuit and Waveforms (3State Inputs are High)
tw(H)
tw(L)
CLOCK
VDD
50%
tsu
th
VSS
3STATE
A OR B
VDD
tPHZ
50%
ADDRESS DATA
VSS
tPLH, tPHL
Q
50%
VOH
90%
QA
VDD
50%
50%
VSS
tPZH
90%
VOH
10%
tPZL
VOH
90%
10%
VOL
tTLH, tTHL
QB
Figure 3.
VOL
tPZL
10%
VOL
Figure 4.
VDD
50%
CLOCK
50%
Q
VSS
tsu
WE
trem
50%
DEVICE
UNDER
TEST
VDD
CL
50%
VSS
Figure 5.
1 k
Q
DEVICE
UNDER
TEST
CONNECT TO VCC WHEN TESTING tPLZ AND tPZL

CONNECT TO GND WHEN TESTING tPHZ AND tPZH
CL
MC14580B
6487
LOGIC DIAGRAM
CLOCK
WE
R0A
13
R1A
14
16
15
R1B
10
R0B
11
3STATE A
3
Q
Q
C
D
3STATE
Q
C
D
3STATE
D3
D2
17
18
C
D
Q
C
D
3STATE
Q
C
D
3STATE
C
D
Q
C
D
3STATE
D1
D0
W1
W0
19
20
C
D
Q
C
D
3STATE
Q
C
D
3STATE
Q
C
D
3STATE
Q
Q
C
D
Q3A
Q2A
Q1A
Q0A
Q3B
Q2B
23
Q1B
22
Q0B
21
3STATE B
TRUTH TABLE
Clock
WE
Write 1
Write 0
Read 1A
Read 0A
Read 1B
Read 0B
3State A
3State B
Dn
QnA
QnB
1
1
X
0
0
X
1
1
X
0
0
X
1
1
X
0
0
X
1
1
X
1
1
1
1
1
1
1
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
X
X
Dn to
word 0
Word 0
not
altered
1
0
No
Change
Z
No
Change
No
Change
Contents
of word 1
displayed
Contents
of word 1
displayed
1
0
No
Change
Z
No
Change
No
Change
Contents
of word 2
displayed
Contents
of word 2
displayed
Z = High Impedance
X = Dont Care
MC14580B
6488
MOTOROLA
MC14581B
4-Bit Arithmetic Logic Unit
The MC14581B is a CMOS 4bit ALU capable of providing 16 functions of
two Boolean variables and 16 binary arithmetic operations on two 14bit
words. The level of the mode control input determines whether the output
function is logic or arithmetic. The desired logic function is selected by
applying the appropriate binary word to the select inputs (S0 thru S3) with
the mode control input high, while the desired arithmetic operation is
selected by applying a low voltage to the mode control input, the required
level to carry in, and the appropriate word to the select inputs. The word
inputs and function outputs can be operated with either active high or active
low data.
Carry propagate (P) and carry generate (G) outputs are provided to allow
a full lookahead carry scheme for fast simultaneous carry generation for the
four bits in the package. Fast arithmetic operations on long words are
obtainable by using the MC14582B as a second order look ahead block. An
inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included
for ripple through operation.
When the device is in the subtract mode (LHHL), comparison of two 4bit
words present at the A and B inputs is provided using the A = B output. It
assumes a highlevel state when indicating equality. Also, when the ALU is
in the subtract mode the Cn+4 output can be used to indicate relative
magnitude as shown in this table:
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
Data
Level
Cn
Cn+4
Magnitude
H
L
H
L
H
H
L
L
A
B
A<B
A>B
A
B
L
H
L
H
L
L
H
H
Active
High
Active
Low
L SUFFIX
CERAMIC
CASE 623
B0
24
VDD
A0
23
A1
w
AvB
S3
22
B1
S2
21
A2
S1
20
B2
S0
19
A3
Cn
18
B3
MC
17
F0
16
Cn+4
F1
10
15
F2
11
14
A=B
VSS
12
13
F3
A<B
A>B
A
B
Functional and Pinout Equivalent to 74181.


Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
MC14581B
6489

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.64
1.6
4.2
1.0
0.51
1.3
3.4
1.7
0.88
2.25
8.8
0.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14581B
6490

Characteristic
Symbol

tTLH,
tTHL

Sum in to Sum Out
tPLH,
tPHL
Sum in to Sum Out (Logic Mode)

tPLH,
tPHL
Sum in to A = B
tPLH,
tPHL
Sum in to P or G
tPLH,
tPHL
Sum in to Cn+4
tPLH
Carry in to Sum Out

tPLH,
tPHL
Carry in to Cn+4
tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
705
250
180
1410
500
360
5.0
10
15
605
215
180
1210
430
360
5.0
10
15
955
330
245
1910
660
490
5.0
10
15
485
180
130
970
360
260
5.0
10
15
615
220
160
1230
440
360
5.0
10
15
380
145
105
760
290
210
5.0
10
15
305
120
85
610
240
170
ns
ns
ns
ns
ns
ns
AC TEST SETUP REFERENCE TABLE

AC Paths
DC Data Inputs
Test
Inputs
Outputs
To VSS
To VDD
Mode
Fig.
g 3
Waveform
Sumin to Sumout
Delay Time
A0
Any F
Remaining As
Cn
All Bs
Add
#1
Sumin to P
Delay Time
A0
Remaining As
Cn
All Bs
Add
#1
Sumin to G
Delay Time
B0
All As
Cn
Remaining Bs
Add
#1
Sumin to Cn+4
Delay Time
B0
Cn+y
All As
Cn
Remaining Bs
Add
#2
Cn to Sumout
Delay Time
Cn
Any F
All As
All Bs
Add
#1
Cn to Cn+4
Delay Time
Cn
Cn+4
All As
All Bs
Add
#1
Sumin to A = B
Delay Time
A0
A=B
All Bs
Remaining As
Cn
Sub
#2
Sumin to Sumout
Delay Time
(Logic Mode)
B0
Any F
All As
Exclusive
OR
#2
MC14581B
6491
Vout = VOH
VDD
S0 S1 S2 S3
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
VDD
HIGH FOR
ALL OUTPUTS
EXCEPT Cn+4
S0 S1 S2 S3
F0
IOH
F2
F3
A=B
Cn+4
G
P
EXTERNAL
POWER
SUPPLY
HIGH FOR
ALL OUTPUTS
EXCEPT Cn+4
Figure 1. Typical Source Current Test Circuit
50 pF
TPin
S0 S1 S2 S3
F0
A0
F1
A1
A2
F2
A3
F3
B0
B1
A=B
B2
Cn+4
B3
G
Cn
P
MC
SEE AC TEST
SETUP
REFERENCE
TABLE FOR
CONNECTIONS
F0
F1
IOH
F2
F3
A=B
Cn+4
G
P
EXTERNAL
POWER
SUPPLY
VSS
Figure 2. Typical Sink Current Test Circuit
LOAD A TP
out
VDD
PULSE
GENERATOR
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
VDD
F1
VSS
Vout = VOH
VDD
20 ns
20 ns
VDD
90%
TPin
10%
tPHL
tTLH
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
0V
VOH
#1
TPout
10%
VOL
tPLH
tTHL
tTHL
90%
#2
TPout
tPHL
VOH
10%
VOL
tTLH
tPLH
VDD
LOAD A
S0 S1 S2 S3
TPin
PULSE
GENERATOR
DUTY CYCLE = 50%
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
TPout
50 pF
F0
F1
F2
LOAD A
F3
LOAD A
A=B
LOAD A
Cn+4
G
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
20 ns
TPin
90%
50%
20 ns
VDD
10%
0V
VARIABLE
WIDTH
MC14581B
6492
BLOCK DIAGRAM
(ACTIVE LOW)
FUNCTION
SELECT
INPUTS
WORD A
WORD B
BLOCK DIAGRAM
(ACTIVE HIGH)
3
4
5
6
3
4
5
6
VDD = PIN 24
VSS = PIN 12
S0 S1 S2 S3
A0
F0
A1
F1
A2
F2
A3
F3
B0
B1
A=B
B2
Cn+4
B3
G
Cn
P
MC
2
23
21
19
1
22
20
18
CARRY IN 7
MODE CONTROL 8
9
10
11
13
S0 S1 S2 S3
A0
F0
A1
F1
A2
F2
A3
F3
B0
B1
A=B
B2
Cn+4
B3
G
Cn
P
MC
2
23
OUTPUT
FUNCTION
21
19
1
22
14 COMPARISON OUTPUT
20
18
16 RIPPLE CARRY OUTPUT

17 LOOK AHEAD
15 CARRY OUTPUTS
7
8
9
10
11
13
14
16
17
15
TRUTH TABLE
Function Select
Inputs/Outputs Active Low

Logic
Function
(MC = H)
Arithmetic*
Function
(MC = L, Cn = L)
Inputs/Outputs Active High

Logic
Function
(MC = H)
Arithmetic*
Function
(MC = L, Cn = H)
S3
S2
S1
S0
L
L
L
L
L
L
L
H
A
AB
A minus 1
AB minus 1
A
A+B
A
A+B
A+B
AB minus 1
AB
A+B
Logic 1
minus 1
Logic 0
minus 1
A+B
A plus (A + B)
AB
A plus AB
AB plus (A + B)
(A + B) plus AB
A minus B minus 1
A+B
A+B
AB
AB minus 1
AB
A plus (A + B)
A+B
A plus AB
A plus B
A plus B
AB plus (A + B)
(A + B) plus AB
A+B
A+B
AB
AB minus 1
Logic 0
A plus A
Logic 1
A plus A
AB
AB plus A
A+B
(A + B) plus A
AB
AB plus A
A+B
(A + B) plus A
A minus 1
B
B
B
B
A minus B minus 1
* Expressed as twos complements. For arithmetic function with Cn in the opposite state, the resulting
function is as shown plus 1.
MC14581B
6493
MOTOROLA
MC14582B
Look-Ahead Carry Block
L SUFFIX
CERAMIC
CASE 620
The MC14582B is a CMOS lookahead carry generator capable of

anticipating a carry across four binary adders or groups of adders. The
device is cascadable to perform full lookahead across nbit adders. Carry,
generatecarry, and propagatecarry functions are provided as enumerated
in the pin designation table shown below.
Expandable to any Number of Bits

All Buffered Outputs
Low Power Dissipation
D SUFFIX
SOIC
CASE 751B

Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
P SUFFIX
PLASTIC
CASE 648
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
PIN ASSIGNMENT
LOGIC EQUATIONS
Cn+x = G0 + (P0 Cn)
Cn+y = G1 + (P1 G0) + (P1 P0 Cn)
G1
16
VDD
P1
15
P2
G0
14
G2
P0
13
Cin
G3
12
Cn+x
P3
11
Cn+y
10
VSS
Cn+z
Cn+z = G2 + (P2 G1) + (P2 P1 G0) + (P2 P1 P0 Cn)

G = G3 + (P3 G2) + (P3 P2 G1) + (P1 P2 P3 G0)
P = P3 P2 P1 P0
PIN DESIGNATIONS
Designation
Pin Nos
Function
G0, G1, G2, G3
3, 1, 14, 5
ActiveLow
CarryGenerate Inputs
P0, P1, P2, P3
4, 2, 15, 6
ActiveLow
CarryPropagate Inputs
Cn
13
Carry Input
Cn+x, Cn+y
Cn+z
12, 11, 9
Carry Outputs
10
ActiveLow Group
CarryGenerate Output
ActiveLow Group
CarryPropagate Output
MC14582B
6494

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
be left open.
MC14582B
6495

Characteristic
Symbol

tTLH,
tTHL

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
345
140
110
690
280
220
Unit
ns
ns
VDD
Cin
G0
20 ns
PULSE
GENERATOR
10% V
SS
VARIABLE
WIDTH
CL
G3
Vin
CL
Cn+y
G2
VDD
90%
50%
Vin
Cn+x
G1
20 ns
Cn+z
P0
CL
P1
CL
P2
P3
CL

Test Circuit and Waveform
Vout = VOH
VDD
16
Cin
G0
16
Cin
G0
Cn+x
G1
G3
Cn+z
P0
P2
IOH
VSS
Cn + z
P0
P3
EXTERNAL
POWER
SUPPLY
IOL
P2
Figure 2. Source Current Test Circuit
MC14582B
6496
G3
P1
P3
Cn + y
G2
P1
Cn + x
G1
Cn+y
G2
Vout = VOL
VDD
VSS
EXTERNAL
POWER
SUPPLY
Figure 3. Sink Current Test Circuit
TEST TABLE
AC Paths
VDD
VSS
Output
To VSS
P0
To VDD
Remaining
Gs
Ps, Cn
Ps, Cn
Remaining
Gs
G0
Cn
Cn+x, Cn+y,
Cn+z
Vout
Cin
G0
G1
G2
G3
P0
P1
P2
P3
SEE
TEST
TABLE
PULSE
GENERATOR
DC Data
Input
Cn+x
Cn+y
CL
Cn+z
Ps
Gs
20 ns
20 ns
90%
50%
Vin
tPLH
VDD
10%
tPHL
VSS
VOH
Vout
VOL
tTHL
tTLH
MC14581B
Cn Cn+4
Cn
Cn+4
Cn
Cn+4
Cn Cn+4
16BIT ALU, RIPPLE CARRY

MC14581B
Cn
Cn
G P
G0 P0 Cn+x
Cn
Cn
G P
Cn Cn+4
G P
G P
G1 P1 Cn+y
G2 P2 Cn+z
MC14582B
G3 P3
G P
16BIT ALU, TWO LEVEL LOOKAHEAD

MC14581B
Cn
G P
Cn
G0 P0 Cn+x
Cn
G P
Cn
Cn
G P
G1 P1 Cn+y
G2 P2 Cn+z
MC14582B
Cn+4
G P
Cn
G3 P3
Cn
G P
G P
Cn
G0 P0 Cn+x
G P
Cn
Cn Cn+4
G P
G P
G1 P1 Cn+y
G2 P2 Cn+z
MC14582B
G3 P3
G P
32BIT ALU, TWO LEVEL LOOKAHEAD OVER 16BIT GROUPS

MC14581B
Cn
Cn+4
Cn+4
Cn
Cn
G P
G0 P0 Cn+x
Cn
Cn
G P
G1 P1
G P
Cn Cn+4
G P
Cn+y
G2 P2 Cn+z
MC14582B
Cn Cn+4
Cn
G3 P3
G P
Cn
G P
G0 P0 Cn+x
G1 P1
Cn
MC14582B
G P
Cn+y
COMBINED TWOLEVEL LOOKAHEAD AND RIPPLE CARRY ALU

MC14581B
Cn
G P
G0 P0 Cn+x
Cn
Cn
G P
Cn
Cn
G1 P1 Cn+y
G2 P2 Cn+z
MC14582B
Cn
G P
G3 P3
G0 P0 Cn+x
Cn
G P
G0 P0
Cn
G P
Cn
G P
Cn
G P
G1 P1 Cn+y
G2 P2 Cn+z
MC14582B
Cn+x
Cn
Cn+4
G P
Cn
G0 P0 Cn+x
Cn MC14582B
G3 P3
G P
G1 P1
G P
Cn+y
MC14582B
64BIT ALU, FULLCARRY LOOKAHEAD IN THREE LEVELS.

A AND B INPUTS AND F OUTPUTS ARE NOT SHOWN (MC14581B).
MC14582B
6497
MOTOROLA
MC14583B
Dual Schmitt Trigger
L SUFFIX
CERAMIC
CASE 620
The MC14583B is a dual Schmitt trigger constructed with complementary

Pchannel and Nchannel MOS devices on a monolithic silicon substrate.
Each Schmitt trigger is functionally independent except for a common
3state input and an internallyconnected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive,
negative, and common terminals with the use of external resistors.
Applications include the speedup of a slow waveform edge in interface
receivers, level detectors, etc.
P SUFFIX
PLASTIC
CASE 648

Resistor Adjustable Trigger Levels
D SUFFIX
SOIC
CASE 751B
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Symbol
VDD
Parameter
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
DC Supply Voltage
Value
BLOCK DIAGRAM
6
Plastic
Ceramic
SOIC
VDD = PIN 16
VSS = PIN 8
APos ANeg ACom

Aout
Ain
Aout
Dis
9
13
4
11
14
10
Bout
Bin
Bout
BPos BNeg BCom
15
LOGIC DIAGRAM
12
POSITIVE A NEGATIVE A
6 5
7 COMMON A
Ain 9
2
4
Aout
TRUTH TABLE
Inputs
11 Aout
3STATE
OUTPUT DISABLE
13
14 EXCLUSIVE OR
Bin 15
10 Bout
12 Bout
1 COMMON B
2 3
POSITIVE B2 NEGATIVE B
MC14583B
6498
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
Outputs
Dis Aout Aout Bout Bout

0
0
Z
0
Z
1
0
1
0
1
0
0
Z
1
Z
1
0
1
1
0
0
1
0
1
1
1
1
1
Z
0
Z
0
0
0
1
1
Z
1
Z
0
0
0
1
1
1
1
0
0
Z = High impedance at output
VDD = PIN 16
VSS = PIN 8

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
1.2
0.25
1.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc

Per Package)
buffers switching)
IT
5.0
10
15
ITL
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc

0.1
0.0001
Adc
0.1
3.0
Adc

PIN ASSIGNMENT
BCom
16
VDD
BPos
15
Bin
BNeg
14
Aout
13
DIS
ANeg
12
Bout
APos
11
Aout
ACom
10
Bout
VSS
Ain
MC14583B
6499

Characteristic
Symbol
Output Rise Time

tTLH
Output Fall Time

tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL

Ain, Bin to Aout, Bout
tPLH,
tPHL
Ain, Bin to Aout, Bout

tPLH,
tPHL
Ain, Bin to Exclusive OR

tPLH,
tPHL
3State Enable, Disable Delay Time (see figure 5)

ton, toff = (1.7 ns/pF) CL + 140 ns
ton,
toff
Positive Threshold Voltage

(R1, R2 = 5.0 k)
VDD
Min
Typ #
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
650
230
150
1300
460
300
5.0
10
15
1100
380
260
2200
760
520
5.0
10
15
750
280
170
1500
560
340
5.0
10
15
225
90
55
450
180
110
VT+
5.0
10
15
3.30
5.70
8.20
Vdc
Negative Threshold Voltage

(R1, R2 = 5.0 k)
VT
5.0
10
15
1.70
4.30
6.80
Vdc
Hysteresis Voltage
(R1, R2 = 5.0 k)
VH
5.0
10
15
0.85
0.70
0.70
1.70
1.40
1.40
3.40
2.80
2.80
Vdc
Threshold Voltage Variation, A to B

(R1, R2 = 5.0 k)
VT
5.0
10
15
0.1
0.15
0.20
Vdc
ns
ns
ns
MC14583B
6500
VDD
Vout
VDD
1
VSS
SW1
Ain
Aout
Aout
DIS
Bin
Bout
Bout
2
2
SW2
Output
Under Test
IO
Output Source
Characteristics
Output Sink
Characteristics
Test
VGS = VDD
Value VDS = Vout VDD
Switch Position
SW1
SW2
Test
VGS = VDD
Value VDS = Vout
Switch Position
SW1
SW2
Aout, Bout
Aout, Bout
Exclusive OR
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Sink Characteristics Test Circuit
VDD
500 F
0.01 F
CERAMIC
ID
PULSE
GENERATOR 1
Ain
PULSE
GENERATOR 2
Aout
Aout
DIS
Bin
Bout
Bout
VSS
fout, Ain
fout, Bin
CL
CL
CL
CL
CL
80
R1
70
POSITIVE
COMMON
NEGATIVE
R2
B Feedback scheme for hysteresis adjustment:

POSITIVE
COMMON
R1
NEGATIVE
TYPICAL THRESHOLD POINT (%VDD)
A Feedback scheme for independent threshold adjustment:
60
50
40
30
VSS = 0
VDD = 5.0 V
VDD = 10 V
VDD = 15 V
20
10
6 8
10 20 40 100
1.0 k
10 k
R1, R2, RESISTANCE (OHMS)
100 k
1.0 M
Figure 3. Typical Threshold Points
MC14583B
6501
VDD
PULSE
GENERATOR 1
Ain
PULSE
GENERATOR 2
DIS
Bin
Bout
Bout
PULSE
GENERATOR 3
Aout
Aout
CL
VSS
CL
CL
CL
CL
INPUT = tr = tf = 20 ns
VDD
Ain
50%
VSS
VDD
50%
Bin
VSS
VDD
3STATE
DISABLE
50%
tPLH
tPHL
Aout
tr
tf
90%
50%
10%
tPHL
tr
Bout
10%
tPHL
tPLH
50%
Aout
VOL
ton
tf toff
90%
VOH
10%
tr
tPLH
tPHL
VOH
90%
50%
VOL
ton
toff
VOH
Bout
tf
EXCLUSIVE
OR
tr
90%
VOH
VOL
tf
tPLH
VSS
tf
VOL
tPHL
tPLH
tPHL
tPLH
50%
10%
VOH
VOL
tr
NOTE: Dashed lines indicate high output resistance
MC14583B
6502
VDD
VDD
1 k*
PULSE
GENERATOR 1
Ain
PULSE
GENERATOR 2
DIS
Bin
Aout
Aout
1
SW
2
Bout
Bout
Test
Switch Position
ton HL
ton LH
toff HL
toff LH
2
1
1 k*
CL
* Metal film, 1%, 1/4 W or greater
VSS
CL = 15 pF, which includes test circuit capacitance.
VDD
Ain
VSS
VDD
Bin
VSS
VDD
3STATE
DISABLE
50%
ton LH
Aout
10%
VOL
ton LH
Bout
10%
90%
VOH
SWITCH POSITION 2
toff LH
ton HL
VOH
90%
toff HL
VOH
VSS
toff LH
90%
VOH
toff LH
90%
VOH
VOH
10% (VOH VOL)
VOL
VOL
VOH
10% (VOH VOL)
VOL
VOL
SWITCH POSITION 1
VOL and VOH refer to the levels present as a result of the 1 k ohm load resistors.
Figure 5. 3State Switching Time Test Circuit and Waveforms
MC14583B
6503
MOTOROLA
MC14584B
Hex Schmitt Trigger
L SUFFIX
CERAMIC
CASE 632
The MC14584B Hex Schmitt Trigger is constructed with MOS Pchannel

MC14069UB hex inverter for enhanced noise immunity to square up slowly
changing waveforms.
P SUFFIX
PLASTIC
CASE 646

Can Be Used to Replace MC14069UB
For Greater Hysteresis, Use MC14106B which is PinforPin
Replacement for CD40106B and MM74Cl4
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
D SUFFIX
SOIC
CASE 751A
Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
EQIVALENT CIRCUIT SCHEMATIC

Plastic
Ceramic
SOIC
LOGIC DIAGRAM
1
11
10
13
12
VDD = PIN 14
VSS = PIN 7

MC14584B
6504

Characteristic
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Hysteresis Voltage
VH
5.0
10
15
0.27
0.36
0.77
1.0
1.3
1.7
0.25
0.3
0.6
0.6
0.7
1.1
1.0
1.2
1.5
0.21
0.25
0.50
1.0
1.2
1.4
Threshold Voltage
PositiveGoing
VT+
5.0
10
15
1.9
3.4
5.2
3.5
7.0
10.6
1.8
3.3
5.2
2.7
5.3
8.0
3.4
6.9
10.5
1.7
3.2
5.2
3.4
6.9
10.5
5.0
10
15
1.6
3.0
4.5
3.3
6.7
9.7
1.6
3.0
4.6
2.1
4.6
6.9
3.2
6.7
9.8
1.5
3.0
4.7
3.2
6.7
9.9

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
Source
Sink

Per Package)
buffers switching)
NegativeGoing
VT
mAdc

Adc
Vdc
Vdc
Vdc
VH = VT+ VT (But maximum variation of VH is specified as less than VT + max VT min).
MC14584B
6505
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
tPLH, tPHL
5.0
10
15
125
50
40
250
100
80
ns
Characteristic
PULSE
GENERATOR
20 ns
VDD
14
OUTPUT
INPUT
INPUT
7 VSS
20 ns
tPHL
CL
VDD
90%
50%
10%
VSS
tPLH
90%
50%
10%
OUTPUT
tf
VOH
VOL
tr

Vin
VH
Vout
VH
VDD
VT+
VT
Vin
VDD
VT+
VT
Vin
VSS
VSS
VDD
VDD
Vout
Vout
VSS
VSS
(a) Schmitt Triggers will square up inputs with slow

rise and fall times.
(b) A Schmitt trigger offers maximum noise immunity

in gate applications.
Figure 2. Typical Schmitt Trigger Applications
VDD
PIN ASSIGNMENT
VT
VT+
IN 1
14
VDD
OUT 1
13
IN 6
IN 2
12
OUT 6
OUT 2
11
IN 5
OUT 5
IN 3
10
OUT 3
IN 4
VSS
OUT 4
VDD
VH
MC14584B
6506
MOTOROLA
MC14585B
4-Bit Magnitude Comparator
The MC14585B 4Bit Magnitude Comparator is constructed with complementary MOS (CMOS) enhancement mode devices. The circuit has eight
comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0), three cascading inputs
(A < B, A = B, and A > B), and three outputs (A < B, A = B, and A > B). This
device compares two 4bit words (A and B) and determines whether they
are less than, equal to, or greater than by a high level on the appropriate
output. For words greater than 4bits, units can be cascaded by connecting
outputs (A > B), (A < B), and (A = B) to the corresponding inputs of the next
significant comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low, a high, and a low,
respectively.
Applications include logic in CPUs, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and controls.
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B

Expandable
Applicable to Binary or 8421BCD Code
Can be Cascaded See Fig. 3
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin, Vout
0.5 to VDD + 0.5
Iin, Iout

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
TL
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
4
6
5
10
11
7
9
2
1
15
14
(A > B)in
(A = B)in
(A < B)in
A0
B0
A1
B1
A2
B2
A3
B3
(A > B)out
13
(A = B)out
(A < B)out
12
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE (x = Dont Care)

Inputs
Comparing
Outputs
Cascading
A3, B3
A2, B2
A1, B1
A0, B0
A<B
A=B
A>B
A<B
A=B
A>B
A3 > B3
A3 = B3
A3 = B3
A3 = B3
x
A2 > B2
A2 = B2
A2 = B2
x
x
A1 > B1
A1 = B1
x
x
x
A0 > B0
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
A0 = B0
0
0
1
1
0
1
0
1
x
x
x
x
0
0
1
1
0
1
0
1
1
0
0
0
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 < B2
A1 = B1
A1 < B1
x
A0 < B0
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
0
0
0
0
0
A3 < B3
MC14585B
6507

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
5.0
5.0
10
15
3.0
0.64
1.6
4.2
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
1.7
0.36
0.9
2.4
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
1 Level
VIH
(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink

Per Package)
buffers switching)
mAdc

Adc
PIN ASSIGNMENT
B2
16
VDD
A2
15
A3
(A = B)out
14
B3
(A
13
(A
12
(A
(A = B)in
11
B0
A1
10
A0
VSS
B1
u B)in
(A t B)in
MC14585B
6508
u B)out
t B)out

Characteristic
Symbol

tTLH,
tTHL
TurnOn, TurnOff Delay Time

tPLH,
tPHL
VDD
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
430
180
130
860
360
260
Unit
ns
ns
20 ns
20 ns
VDD
A3
1
2f
VSS
VDD
B3
VSS
20 ns
20 ns
VOH
(A > B)out
VOL
50%
B0
10%
VOH
tPLH
(A = B)out
VOH
50%
(A < B)out
10%
tTLH

Signal Waveforms
VOH
90%
VOL
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low.
VSS
tPHL
VOL
(A < B)out
VDD
90%
VOL
tTHL
Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
A2, B1, A1, A0, and (A<B) low.
be left open.
MC14585B
6509
(A>B)
(A=B)
(A<B)
(A>B)
(A=B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT
MC14585B
VSS VDD VSS

(A<B)
WORD
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B = B11
WORD
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A=
INPUTS
MC14585B
WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A>B)
(A=B)
(A<B)
MC14585B
OUTPUTS
Figure 3. Cascading Comparators
LOGIC DIAGRAM
A3
B3
A2
B2
A1
B1
A0
B0
(A < B)in
15
14
2
1
7
12
9
10
11
5
3
(A = B)in
(A > B)in
(A < B)out
MC14585B
6510
13
(A = B)out
(A > B)out
MOTOROLA
MC14597B
MC14598B
8-Bit Bus-Compatible Latches

The MC14597B and MC14598B are 8bit latches, one addressed with an
internal counter and the other addressed with an external binary address.
The 8 latchoutputs are high drive, threestate and bus line compatible. The
drive capability allows direct applications with MPU systems such as the
Motorola 6800 family.
With MC14597B, a 3bit address counter (clocked on the falling edge of
Increment) selects the appropriate latch. The latches of the MC14598B are
accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on
the MC14597B to indicate the position of the Address counter.
All 8 outputs from the latches are available in parallel when Enable is in the
low state. Data is entered into a selected latch from the Data pin when the
Strobe is high. Master reset is available on both parts.
Serial Data Input
ThreeState Bus Compatible Parallel Outputs
ThreeState Control Pin (Enable) TTL Compatible Input
Open Drain Full Flag (Multiple Latch WireO Ring)
Master Reset
Level Shifting Inputs on All Except Enable
Diode Protection All Inputs
Supply Voltage Range 3.0 Vdc to 18 Vdc
Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows:
1 TTL Load
4 LSTTL Loads
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MC14597BCP
MC14597BCL
MC14597BDW
L SUFFIX
CERAMIC
CASE 726
4 ENABLE
RESET
LOGIC
DATA
STROBE
3BIT
ADDRESS
COUNTER
ADDRESS
DECODER
3
6
THREE
STATE
OUTPUT
BUFFERS
8
LATCHES
1
15
14
13
12
11
10
9
INCREMENT
FULL
LOGIC
VDD = 16
VSS = 8
Plastic
Ceramic
SOIC
BLOCK DIAGRAMS
MC14597B
RESET
L SUFFIX
CERAMIC
CASE 620
D0
D1
D2
D3
D4
D5
D6
D7
D0
16
VDD
RESET
15
D1
DATA
14
D2
ENABLE
13
D3
FULL
12
D4
MC14598BCP
MC14598BCL
STROBE
11
D5
INCREMENT
10
D6
VSS
D7
5
FULL
MC14598B
OUTPUT
TRUTH TABLE
ENABLE
4
RESET
DATA
STROBE
2
3
6
A0 7
A1 8 ADDRESS
A2 10 DECODER
VDD = 18
VSS = 9
8
LATCHES
1
17
THREE
16
STATE
15
OUTPUT
14
BUFFERS
13
12
11
D0
D1
D2
D3
D4
D5
D6
D7
P SUFFIX
PLASTIC
CASE 707
Enable
Outputs
High Impedance
Plastic
Ceramic
D0
18
VDD
RESET
17
D1
DATA
16
D2
ENABLE
15
D3
NC
14
D4
STROBE
13
D5
Dn
A0
12
D6
Dn = State of nth latch
A1
11
D7
VSS
10
A2
NC = NO CONNECTION
MC14597B MC14598B
6511

Parameter
Symbol
VDD
DC Supply Voltage
Value
Unit
0.5 to + 18.0
Vin
Input Voltage, Enable (DC or Transient)
0.5 to VDD + 0.5
Vin
Input Voltage, All other Inputs

(DC or Transient)
0.5 to VDD + 12
Vout
0.5 to VDD + 0.5

per Pin
10
mA
PD
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
Iin, lout
TL

to the range VSS
(Vin or Vout)
VDD.

Characteristic
Output Voltage
Vin = VDD or 0
Symbol
55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
5.0
10
15
0.8
1.6
2.4
1.1
2.2
3.4
0.8
1.6
2.4
0.8
1.6
2.4
5.0
10
15
2.0
6.0
10
2.0
6.0
10
1.9
3.1
4.3
2.0
6.0
10
Vin = 0 or VDD
Input Voltage** Enable 0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
1 Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL
VIH
Input Voltage
0 Level
Other Inputs
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Source
(Full Sink Only)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
VIH
Vdc
Vdc
Vdc
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
IOH
Vdc
mAdc
5.0
10
15
1.0
1.0
2.0
6.0
12
1.0
IOL
5.0
10
15
1.6
1.6
3.2
6.0
12
1.6
mAdc
15
0.1
0.00001
0.1
1.0
Adc
Iin
ITL
15
0.1
0.00001
0.1
3.0
Adc
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
Adc
(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Sink

Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
**External Load Capacitance of
**130 pF
MC14597B MC14598B
6512
IT
5.0
10
Adc
SWITCHING CHARACTERISTICS* (TA = 25_C, CL = 130 pF + 1 TTL Load)
All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
100
50
40
200
100
80
5.0
10
15
160
125
100
320
250
200
Strobe to Output
5.0
10
15
200
100
80
400
200
160
Strobe to Full (MC14597B only)
5.0
10
15
200
100
80
400
200
160
Reset to Output
5.0
10
15
175
90
70
350
180
140
5.0
10
15
320
240
160
160
120
80
Strobe
5.0
10
15
200
100
80
100
50
40
Increment (MC14597B only)
5.0
10
15
200
100
80
100
50
40
Reset
5.0
10
15
300
160
100
150
80
50
5.0
10
15
100
50
35
50
25
20
Address (MC14598B only)
5.0
10
15
200
100
70
100
50
35
Increment (MC14597B only)
5.0
10
15
400
200
170
200
100
85
5.0
10
15
100
50
35
50
25
20
5.0
10
15
100
50
35
50
25
20
5.0
10
15
20
20
20
25
15
10
Characteristic
Symbol

tTLH,
tTHL

Enable to Output
tPLH,
tPHL
Pulse Width
Enable
Setup Time
Data
Hold Time
Data
tWH,
tWL
Reset Removal Time
ns
ns
ns
tsu
ns
th
Address (MC14598B only)
trem
Unit
ns
ns
MC14597B MC14598B
6513
MC14597B FUNCTION DIAGRAM

VDD
ENABLE 4
TO OTHER
LATCHES
RESET 2
VDD
5 FULL
R
D Q
CLK
STROBE 6
VDD
DATA 3
1 D0
TO OTHER
LATCHES
SEVEN
SELECT
VSS
ONE LATCH
ZERO
SELECT
R
3 STAGE COUNTER
AND DECODER
15
14
13
12
11
10
9
ADDITIONAL 7 LATCHES
CLK
D1
D2
D3
D4
D5
D6
D7
INCREMENT 7
MC14597B TIMING DIAGRAMS

D6 (INTERNAL)
D7 (INTERNAL)
tWL
tWH
INCREMENT
20 ns
90%
DATA
tsu
tsu
10%
th
STROBE
10%
20 ns
tW
FULL
tPHL
trem
50%
RESET
tW
NOTE: Enable in High state.

tTLH
Dn
90%
10%
90%
tTHL
90%
10%
tPHL
FULL
ENABLE
*
tWL
* 1.4 V with VDD = 5.0 V

NOTES:
1. Highimpedance output state (another device controls bus).
2. Reset in High state.
MC14597B MC14598B
6514
MC14598B FUNCTION DIAGRAM
RESET 2
VDD
DATA 3
1 D0
TO OTHER
LATCHES
STROBE 6
ENABLE 4
VSS
EACH LATCH
TO OTHER
LATCHES
ZERO
SELECT
17
16
15
14
13
12
11
A0 7
ADDRESS
DECODER
A1 8
ADDITIONAL 7 LATCHES
A2 10
(M.S.B)
D1
D2
D3
D4
D5
D6
D7
MC14598B TIMING DIAGRAM

90%
10%
50%
tPLH
tTHL
D7
90%
10%
50%
tPLH
RESET
tPHL
tTLH
20 ns
tW
90%
10%
50%
A0, A1, A2
tsu th
DATA
90%
10%
STROBE
tsu
th
50%
90%
10%
20 ns
20 ns
ENABLE
tW
*
tW
* 1.4 V with VDD = 5.0 V

NOTES:
1. Highimpedance output state (another device controls bus).
2. Output Load as for MC14597B.
MC14597B MC14598B
6515
LATCH TRUTH TABLE
TRUTH TABLE FOR MC14597B
Address
Latch
Other
Latches
Data
Strobe
Reset
0
1
X
Increment
Address
Counter
Full
Count Up
No Change
Reset to Zero
Set to One
No Change
Set to One
If at
ADDRESS 7
To Zero on
Falling Edge
of STROBE
Enable
Reset
X
X
X
* = No change in state of latch

X = Dont care
X = Dont care
TEST LOAD
ALL OUTPUTS
+5.0 V
RL = 2.5 k
Dn
130 pF
11.7 k
Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete
information sufficient for construction purposes may not be
fully illustrated. Although the information herein has been
carefully checked and is believed to be reliable. Motorola
assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under the
MC14597B MC14598B
6516
patent rights of Motorola or others.

The information contained herein is for guidance only, with
no warranty of any type, expressed or implied. Motorola reserves the right to make any changes to the information and
the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time.
CMOS Reliability
RELIABILITY
Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the
applicability of a particular device has been established, its
effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that an
expression of how well it will serve the customer. The
following discussion will attempt to present an overview of
Motorolas reliability efforts.
Other forms include FIT (Failures in Time = (%/103 hrs) x

104 = 109 failures per hour) and MTTF (Mean Time To
Failure) or MTBF (Mean Time Between Failures), both being
equal to 1/ and having units of hours.
Since reliability evaluations usually involve only samples
of an entire population of devices, the concepts of the Central Limit Theorem apply and is calculated using x2 distribution through the equation:
x2 (x, 2r + 2)
2nt
BASIC CONCEPTS
where x =
100 CL
100
CL = Confidence Limit in percent

r = Number of rejects
n = Number of devices
t = Duration of test
The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higher which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 2). The term (2r + 2) is called the degrees of freedom
and is an expression of the number of rejects in a form
suitable to x2 tables.
50% CL
FREQUENCY
It is essential to begin with an explanation of the various

parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 1). The reliability performance of a device is characterized by three phases: infant
mortality, useful life, and wearout. When a device is
produced, there is often a small distribution of failure
mechanisms which will exhibit themselves under relatively
moderate stress levels and therefore appear early. This
period of early failures, termed infant mortality is reduced
significantly through proper manufacturing controls and
screening techniques. The most effective period is that in
which only occasional random failure mechanisms appear.
The useful life typically spans a long period of time with a
very low failure rate. The final period is that in which the
devices literally wear out due to continuous phenomena
which existed at the time of manufacture. Using strictly
controlled design techniques and selectivity in applications,
this period is shifted well beyond the lifetime required by the
user.
90% CL
FAILURE RATE
INFANT MORTALITY
(SUCH AS EARLY
BURNIN FAILURES)
, FAILURE RATE
USEFUL LIFE
10
100
1000 10,000 100,000

TIME (HOURS)
WEAROUT
FAILURES
1,000,000
Figure 1.
Both the infant mortality and random failure rate regions
can be described through the same types of calculations.
During this time the probability of having no failures to a
specific point in time can be expressed by the equation:
Po = et
where is the failure rate and t is time. Since is changing
rapidly during infant mortality, the expression does not
become useful until the random period, where is relatively
constant. In this equation is failures per unit of time. It is
usually expressed in percent failures per thousand hours.
Figure 2.
The number of rejects is a critical factor since the definition
of rejects often differs between manufacturers. While
Motorola uses data sheet limits to determine failures, sometimes rejects are counted only if they are catastrophic. Due to
the increasing chance of a test not being representative of
the entire population, as sample size and test time are decreased, the x2 calculation produces surprisingly high values
of for short test durations even though the true long term
failure rate may be quite low. For this reason relatively large
amounts of data must be gathered to demonstrate the real
long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behavior fits
the form of the Arrhenius equation:
R (t) = R0(t)e /kT
CHAPTER 7
72
NOTE: This data sheet has a new look the technical content has not changed.
where R(t) = Reaction rate as a function of time and

temperature
R0 = A constant
t
= Time
= Activation energy in electron volts
k = Boltzmans constant
T = Temperature in degrees Kelvin
corrosion in plastic devices and metal fatigue for Power

devices.
1.2
CHAPTER 7
73
2.4
2.8
3.2
3.6
10 k
t2
TIME (HOURS)
t = t0e /kT
P2
1.0 k
100
10
t1
P1
1.0 eV
SLOPE
1.0
0.1
T1
200
100
TEMPERATURE (C)
500
T2
50
Figure 3. Normalized TimeTemperature

Regressions for Various Activation Energy Values
100 k
1.2
100
1.6
2.0
2.4
2.8
3.2
3.6
10
, FAILURE RATE (%/1000 HOURS)
t0 = A constant
The Arrhenius equation essentially states that reaction
rate increases exponentially with temperature. This produces a straight line when plotted in loglinear paper with a
slope expressed by . may be physically interpreted as
the energy threshold of a particular reaction or failure mechanism. The activation energy exhibited by semiconductors
varies from about 0.3 eV. Although the relationships do not
prohibit devices from having poor failure rates and high
activation energies, good performance usually does not
imply a high . Studies by Bell Telephone Laboratories have
indicated that an overall for semiconductors is 1.0 eV. This
value has been accepted by the Rome Air Development
Command for timetemperature acceleration in powered
burnin. Data taken by Motorola on Integrated Circuits have
verified this number and it is therefore applied as our standard timetemperature regression for extrapolation of high
temperature failure rates to temperatures at which the
devices will be used (Figure 3). For Discrete products, 0.7 eV
is generally applied.
To accomplish this, the time in device hours (t1) and temperature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
with a 1.0 eV slope is drawn through point P1.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (t2). This
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming T1 of
125_C at t1 of 10,000 hours, a t2 of 7.8 million hours results
at a T2 of 50_C. If one reject results in the 10,000 device
hours of testing at 125_C, the failure rate at that temperature
will be 0.1%/1,000 hours using a 60% confidence level. One
reject at the equivalent 7.8 million device hours at 50_C will
result in a 0.0008%/1,000 hour failure rate, as illustrated in
Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the
activation energy employed, and the difference between the
test temperature and the temperature of the quoted . A term
often used in this manipulation is the acceleration factor
which is simply the equivalent device hours at the lower temperature divided by the actual test device hours.
Every device will eventually fail, but with the present techniques in Semiconductor design and applications, the wearout phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parameter used to describe performance in this area is Median Life
and is the point at which 50% of the devices have failed.
There are currently only few significant wearout mechanisms: electromigration of circuit metallization, electrolytic
2.0
100 k
To provide timetemperature equivalents this equation is

applied to failure rate calculations in the form:
where t = time
1.6
1000 k
1.0
2
0.01
0.0001
0.00001
500
200
100
TEMPERATURE (C)
50
Figure 4. Failure Rate
For increased flexibility in working with a broad range of

device hours, the timetemperature regression lines have
been normalized to 500_C and the time scale omitted, permitting the user to define the scale based on his own requirements.
THERMAL MANAGEMENT
Circuit performance and longterm circuit reliability are
affected by die temperature. Normally, both are improved by
keeping the IC junction temperatures low.
Electrical power dissipated in any integrated circuit is a
source of heat. This heat source increases the temperature
of the die relative to some reference point, normally the
ambient temperature of 25 _C in still air. The temperature
increase, then, depends on the amount of power dissipated
in the circuit and on the net thermal resistance between the
heat source and the reference point.
The temperature at the junction is a function of the packaging and mounting systems ability to remove heat generated in the circuit from the junction region to the ambient
environment. The basic formula for converting power
dissipation to estimated junction temperature is:
TJ = TA + PD(JC + CA)
(1)
TJ = TA + PD(JA)
(2)
or
where
TJ
TA
PD
= maximum junction temperature

= maximum ambient temperature
= calculated maximum power dissipation
including effects of external loads (see
Power Dissipation in section III).
JC = average thermal resistance, junction to case
CA = average thermal resistance, case to ambient
JA = average thermal resistance, junction to ambient
This Motorola recommended formula has been approved
by RADC or DESC for calculating a practical maximum
operating junction temperature for MILM38510 (JAN)
devices.
Only two terms on the right side of equation (1) can be varied by the user the ambient temperature, and the device
casetoambient thermal resistance, CA. (To some extent
the device power dissipation can also be controlled, but
under recommended use the VCC supply and loading dictate
a fixed power dissipation.) Both system air flow and the package mounting technique affect the CA thermal resistance
term. JC is essentially independent of air flow and external
mounting method, but is sensitive to package material, die
bonding method, and die area.
Thermal Resistance in Still Air

Package Description
JC (_C/Watt)
No.
Leads
Body
Style
Body
Material
Body
WxL
Die
Bonds
Die Area
(Sq. Mils)
Flag Area
(Sq. Mils)
Avg.
Max.
14
16
DIL
DIL
Epoxy
Epoxy
1/4 x 3/4
1/4 x 3/4
Epoxy
Epoxy
4096
4096
6,400
12,100
38
34
61
54
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is DualInLine.
3. Standard Mounting Method: DualInLine Socket or P/C board with no contact between bottom of package and socket or P/C board.
Figure 5. Thermal Resistance Values for Standard I/C Packages
For applications where the case is held at essentially a

fixed temperature by mounting on a large or temperature
controlled heat sink, the estimated junction temperature is
calculated by:
TJ = TC + PD(JC)
(3)
where TC = maximum case temperature and the other parameters are as previously defined.
The maximum and average JC resistance values for standard IC packages are given in Figure 5.
AIR FLOW
The majority of users employ some form of airflow cooling. As air passes over each device on a printed circuit
board, it absorbs heat from each package. This heat gradient
from the first package to the last package is a function of the
air flow rate and individual package dissipations. Figure 6
provides gradient data at power levels of 200 mW, 250 mW,
300 mW, and 400 mW with an air flow rate of 500 Ifpm.
These figures show the proportionate increase in the junction

temperature of each dual inline package as the air passes
over each device. For higher rates of air flow the change in
junction temperature from package to package down the airstream will be lower due to greater cooling.
Power Dissipation
(mW)
Junction Temperature Gradient

(_C/Package)
200
0.4
250
0.5
300
0.63
400
0.88
Devices mounted on 0.062 PC board with Z axis spacing of 0.5.

Air flow is 500 Ifpm along the Z axis.
Figure 6. Thermal Gradient of Junction Temperature

(16Pin DualinLine Package)
CHAPTER 7
74
Based on the results of almost ten (10) years of +125_C

operating life testing, a special arrhenius equation has been
developed to show the relationship between junction temperature and reliability.
11554.267
Eq. (1) T = (6.376 x 109)e
273.15 + TJ
Table 1. Device Junction Temperature versus Time

to 0.1% Bond Failures
Junction
Temperature _C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
CHAPTER 7
75
TJ = 80 C
TJ = 90 C
TJ = 100C
TJ = 110C
10
100
1000
TIME, YEARS
Where: T = Time in hours to 0.1% bond failure (1 failure

Where: T = per 1,000 bonds).
TJ = Device junction temperature, _C.
And:
Eq. (2) TJ = TA + PDJA = TA + TJ
Where: TJ = Device junction temperature, _C.
TA = Ambient temperature, _C.
PD = Device power dissipation in watts.
JA = Device thermal resistance, junction to air,
_C/Watt.
TJ = Increase in junction temperature due to
onchip power dissipation.
Table 1 shows the relationship between junction temperature, and continuous operating time to 0.1%. bond failure,
(1 failure per 1,000 bonds).
TJ = 120C
Predicting Bond Failure Time:
FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLIC FAILURES OCCUR
TJ = 130C
Todays plastic integrated circuit packages are as reliable

as ceramic packages under most environmental conditions.
However when the ultimate in system reliability is required,
thermal management must be considered as a prime system
design goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the electronics industry. When exposed to high temperatures for protracted periods of time an intermetallic compound can form in
the bond area resulting in high impedance contacts and degradation of device performance. Since the formation of intermetallic compounds is directly related to device junction
temperature, it is incumbent on the designer to determine
that the device junction temperatures are consistent with
system reliability goals.
Table 1 is graphically illustrated in Figure 7 which shows

that the reliability for plastic and ceramic devices are the
same until elevated junction temperatures induces intermetallic failures in plastic devices. Early and midlife failure
rates of plastic devices are not effected by this intermetallic
mechanism.
NORMALIZED FAILURE RATE
OPTIMIZING THE LONG TERM RELIABILITY OF

PLASTIC PACKAGES
Figure 7. Failure Rate versus Time

Junction Temperature
Procedure
After the desired system failure rate has been established
for failure mechanisms other than intermetallics, each device
in the system should be evaluated for maximum junction
temperature. Knowing the maximum junction temperature,
refer to Table 1 or Equation 1 to determine the continuous
operating time required to 0.1% bond failures due to intermetallic formation. At this time, system reliability departs
from the desired value as indicated in Figure 7.
Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
used methods include heat sinks for higher powered devices, refrigerated air flow and lower density board stuffing.
Since CA is entirely dependent on the application, it is the
responsibility of the designer to determine its value. This can
be achieved by various techniques including simulation,
modeling, actual measurement, etc.
The material presented here emphasizes the need to consider thermal management as an integral part of system design and also the tools to determine if the management
methods being considered are adequate to produce the
desired system reliability.
139C
125C
500
134C
TJ SOIC
400
121C
100C 99C
TJ PDIP
PD
PDIP & SOIC
300
7 mW/C
200
81C
75C
100
50C
25C
65C
TA, AMBIENT TEMPERATURE
125C
150C
135C
500
130C
400
PD
PDIP & SOIC
300
125C
129C
TJ SOIC
100C
98C
89C
75C
7 mW/C
200
TJ PDIP
100
58C
50C
25C
65C
TA, AMBIENT TEMPERATURE
125C
P , MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
TJ , JUNCTION TEMPERATURE ( C)
137C
TJ , JUNCTION TEMPERATURE ( C)
150C
P , MAXIMUM POWER DISSIPATION PER PACKAGE (mW)
Figure 8. Junction Temperature for Worst Case

CMOS Logic Device
Figure 9. Junction Temperature for Typical

CMOS Logic Device
This graph illustrates junction temperature for the worst case CMOS
Logic device (MC14007UB) smallest die area operating at
maximum power dissipation limit in still air. The solid line indicates the
junction temperature, TJ, in a DualInLine (PDIP) package and in a
Small Outline IC (SOIC) package versus ambient temperature, TA.
The dotted line indicates maximum allowable power dissipation
derated over the ambient temperature range, 25_C to 125_C.
This graph illustrates junction temperature for a CMOS Logic device

(MC14053B) average die area operating at maximum power
dissipation limit in still air. The solid line indicates the junction
temperature, TJ, in a DualInLine (PDIP) package and in a Small
Outline IC (SOIC) package versus ambient temperature, TA. The
dotted line indicates maximum allowable power dissipation derated
over the ambient temperature range, 25_C to 125_C.
CHAPTER 7
76

The following is a list of equivalent gate counts for some of Motorolas CMOS devices. In general for CMOS, the number of
equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only those devices with
equivalent gate counts known at the time of this printing.
DEVICE
EQUIVALENT
GATE COUNT
MC14000UB
MC14001B
MC14001UB
MC14002B
MC14002UB
MC14006B
MC14007UB
MC14008B
MC14011B
MC14011UB
MC14012B
MC14012UB
MC14013B
MC14014B
MC14015B
MC14016B
MC14017B
MC14018B
MC14020B
MC14021B
MC14023B
MC14023UB
MC14024B
MC14025B
MC14025UB
MC14028B
MC14029B
MC14034B
MC14035B
MC14040B
MC14042B
MC14046B
MC14049UB
MC14049B
MC14050B
MC14051B
MC14052B
MC14053B
MC14060B
MC14066B
MC14067B
MC14068B
MC14069UB
MC14071B
MC14072B
MC14073B
MC14075B
MC14076B
MC14078B
MC14081B
MC14082B
MC14093B
3.5
8
4
7
4
61.5
1.5
40
8
4
7
4
16
74
53
8
62.5
38.25
84
74
9
4.5
59
9
4.5
26
65.5
145
38.5
73
17.5
35
3
9
6
48.5
38.5
38
73.5
13
65
8
3
10
8
10.5
10.5
32.5
7.5
10
8
18
DEVICE
EQUIVALENT
GATE COUNT
MC14094B
MC14099B
MC14161B
MC14163B
MC14174B
MC14175B
MC14194B
MC14490
MC14500B
MC1 4503B
MC14504B
MC14508B
MC14510B
MC14511B
MC14512B
MC14514B
MC14515B
MC14516B
MC14517B
MC14518B
MC14519B
MC14520B
MC14522B
MC14526B
MC14527B
MC14528B
MC14530B
MC14531B
MC14532B
MC14534B
MC14536B
MC14538B
MC14539B
MC14541B
MC14543B
MC14549B
MC14551B
MC14553B
MC14555B
MC14556B
MC14557B
MC14559B
MC14562B
MC14568B
MC14569B
MC14572UB
MC14573
MC14574
MC14575
MC14583B
MC14584B
79
70
72.5
72.5
43.5
39.5
40.5
136.5
192
17
37.5
42
74
54
17.25
59
67
61
119
43.5
11.5
43.5
86
86
46
24
22
44
38.5
206
103
38
20
93
52
122
35
147.5
21
25
232.5
122
206
137.25
156
4
7
9
11
14
18

82
PACKAGE DIMENSIONS
The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensions for
the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes: D
(narrow SOIC), DW (wide SOIC), or FN (PLCC). For example, to order a quad NOR gate, use MC14001BD.
A
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
F
G
J
K
L
M
N
SEATING
PLANE
G
D
M
J
14 PL
0.25 (0.010)
T A
14 PL
0.25 (0.010)
T B
INCHES
MIN
MAX
0.750
0.785
0.245
0.280
0.155
0.200
0.015
0.020
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15_
0.51
1.01
CASE 63208
ISSUE Y
14
NOTES:
Y14.5M, 1982.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
1
A
F
T
SEATING
PLANE
K
H
D 14 PL
0.13 (0.005)
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
10_
0.38
1.01
CASE 64606
ISSUE M
CHAPTER 9
92
PACKAGE OUTLINE DIMENSIONS (continued)
NOTES:
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
14
B
1
P 7 PL
0.25 (0.010)
R X 45 _
T
D 14 PL
0.25 (0.010)
SEATING
PLANE
K
T B
CASE 751A03
ISSUE F
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
M
16
L
1
16X
0.25 (0.010)
J
T B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
C
K
T
N
SEATING
PLANE
G
16X
0.25 (0.010)
T A
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
CASE 620A01
ISSUE O
(REPLACES 62010)
CHAPTER 9
93
NOTES:
Y14.5M, 1982.
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
16
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
T
SEATING
PLANE
H
G
16 PL
0.25 (0.010)
T A
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
CASE 64808
ISSUE R
16
NOTES:
Y14.5M, 1982.
MOLD PROTRUSION.
PER SIDE.
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
X 45 _
C
T
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
T B
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
CASE 751B05
ISSUE J
CHAPTER 9
94
D
9
h X 45 _
0.25
8X
16
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16X
M
T A
DIM
A
A1
B
C
D
E
e
H
h
L
SEATING
PLANE
A1
14X
0.25
CASE 751G03
ISSUE B
18
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
10
B
1
A
L
N
F
H
D
G
SEATING
PLANE
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
K
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
22.22
23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
0.875
0.915
0.240
0.260
0.140
0.180
0.014
0.022
0.050
0.070
0.100 BSC
0.040
0.060
0.008
0.012
0.115
0.135
0.300 BSC
0_
15 _
0.020
0.040
CASE 7O702
ISSUE C
CHAPTER 9
95
A
18
10
B
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
18X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
DIM
A
B
C
D
F
G
J
K
L
M
N
K
SEATING
PLANE
T
N
D
0.25 (0.010)
18X
18 PL
0.25 (0.010)
T A
T B
CASE 726B01
ISSUE O
(REPLACES 72604)
24
B
12
DIM
A
B
C
D
F
G
J
K
L
M
N
SEATING
PLANE
L
G
N
K
MILLIMETERS
MIN
MAX
22.35
23.11
6.10
7.49
5.08
0.38
0.53
1.40
1.78
2.54 BSC
0.20
0.30
3.18
4.32
7.62 BSC
0_
15_
0.51
1.02
NOTES:
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
13
INCHES
MIN
MAX
0.880
0.910
0.240
0.295
0.200
0.015
0.021
0.055
0.070
0.100 BSC
0.008
0.012
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
31.24
32.77
12.70
15.49
4.06
5.59
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
0_
15 _
0.51
1.27
INCHES
MIN
MAX
1.230
1.290
0.500
0.610
0.160
0.220
0.016
0.020
0.050
0.060
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0_
15_
0.020
0.050
CASE 62305
ISSUE M
CHAPTER 9
96
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
DIM
A
B
C
D
F
G
H
J
K
L
M
N
C
N
K
SEATING
PLANE
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
CASE 70902
ISSUE C
A
24
NOTES:
Y14.5M, 1982.
MOLD PROTRUSION.
PER SIDE.
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
12X
P
0.010 (0.25)
12
24X
0.010 (0.25)
T A
F
R
C
T
SEATING
PLANE
M
22X
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
CASE 751E04
ISSUE E
CHAPTER 9
97
Master Index
The Better Program
Data Sheets
CMOS Reliability

Cmos Logic Data

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Master Index

Product Selection Guide

The Better Program

B and UB Series Family Data

CMOS Handling and Design Guidelines

Equivalent Gate Count

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

MOTOROLA CMOS LOGIC DATA

Product Selection Guide

CMOS Selection Guide by Function

Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MOTOROLA CMOS LOGIC DATA

BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 681

Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6112

MOTOROLA CMOS LOGIC DATA

Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6301

Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6321

MOTOROLA CMOS LOGIC DATA

4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6315

12Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6338

4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6484

MOTOROLA CMOS LOGIC DATA

The Better Program

all sales offices. Also available is the Reliability and Quality

MOTOROLA CMOS LOGIC DATA

2.0 RAP TEST FLOW

3.0 TEST CONDITIONS AND COMMENTS

MOTOROLA CMOS LOGIC DATA

2. Any indicated failure is first verified and then submitted to

B and UB Series Family Data

Exceptions to the B and UB Series Family

Output Drive Current

MOTOROLA CMOS LOGIC DATA

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

Input or Output Current (DC or Transient),

Power Dissipation, per Package

VIL = 1.5 V SECOND STAGE

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

Vin = VSS or VDD

VIN = VSS or VDD

VIN = VSS or VDD

VIN = VSS or VDD

VIN = VSS or VDD

MOTOROLA CMOS LOGIC DATA

All valid input

MOTOROLA CMOS LOGIC DATA

Table 2. Motorola Format for CMOS Industry B and UB Series Specifications

FlipFlop and Buffer Quiescent Current

MSI Quiescent Current