SRAM Design

Memory

Chapter Overview
Memory Classification Memory Architectures The Memory Core Periphery Reliability

Memory

Semiconductor Memory Classification

RWM NVRWM ROM

Random Access SRAM DRAM

Non-Random Access FIFO LIFO Shift Register CAM

EPROM E2PROM FLASH

Mask-Programmed Programmable (PROM)

Memory

Memory Architecture: Decoders

M bits S0 S1 N Words S2 Word 0 Word 1 Word 2 Storage Cell A0 Decoder A1 AK -1 S0 M bits Word 0 Word 1 Word 2 Storage Cell

SN-2 SN_1

Word N-2 Word N-1

Word N-2 Word N-1

Input-Output (M bits)

Input-Output (M bits)

N words => N select signals Too many select signals

Memory

Decoder reduces # of select signals K = log2N

Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L-K AK AK+1 AL-1 Bit Line Storage Cell Word Line

Row Decoder

M.2K Sense Amplifiers / Drivers A0 AK -1 Amplify swing to rail-to-rail amplitude Selects appropriate word

Column Decoder

Input-Output (M bits)
Memory

Hierarchical Memory Architecture

Row Address Column Address Block Address

Global Data Bus Control Circuitry Block Selector Global Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
Memory

Memory Timing: Definitions

Read Cycle READ Read Access WRITE Write Access Data Valid DATA Data Written Read Access Write Cycle

Memory

Memory Timing: Approaches

MSB
Address Bus RAS

LSB

Row Address Column Address Address Bus

Address Address transition initiates memory operation

CAS

RAS-CAS timing

DRAM Timing Multiplexed Adressing

Memory

SRAM Timing Self-timed

Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential

DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
Memory

6-transistor CMOS SRAM Cell

WL VDD M2 Q M5 M1 BL M3 BL M4 Q M6

Memory

CMOS SRAM Analysis (Write)

WL VDD M4 Q=0 M5 M1 VDD BL = 1 BL = 0 M6

Q=1

2 2 V DD V DD V DD V DD - ---------- ---------- = k p, M4 ( V DD V Tp ) ---------- k n, M6 ( V DD V Tn ) ---------2 2 8 8 2 V DD VDD kn, M5 VDD V DD 2 - = kn M1 ( VDD V Tn )---------- ----------- ------------ ---------- VTn ---------, 2 2 2 2 8

(W/L)n,M6 0.33 (W/L)p,M4 (W/L)n,M5 10 (W/L)n,M 1

Memory

CMOS SRAM Analysis (Read)

WL VDD BL Q= 0 M5 M1 VDD Q=1 M4 M6 BL

V DD Cbit

V DD C bit

VDD V 2 kn, M5 V VD D 2 DD D D --------------- ----------- = kn M1 ( VD D V Tn ) ----------- ----------- VTn ----------, 2 2 2 2 8

(W/L)n,M5 10 ( W/L)n,M1

(supercedes read constraint)

Memory

6T-SRAM Layout
VDD
M2 M4

Q
M1 M3

GND
M5 M6

WL

BL
Memory

BL

Resistance-load SRAM Cell

WL VDD RL M3 BL Q RL Q M4 BL

M1

M2

Static power dissipation -- Want RL large Bit lines precharged to VDD to address t p problem
Memory

Periphery
Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Memory

Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder

NOR Decoder

Memory

Dynamic Decoders
Precharge devices GND GND VDD WL 3

WL 3

VDD

WL 2 WL 1 WL 0

VDD

WL 2

VDD

WL 1

WL 0 A0 A0 A1 A1

V DD

A0

A0

A1

A1

Dynamic 2-to-4 NOR decoder

2-to-4 MOS dynamic NAND Decoder

Propagation delay is primary concern

Memory

A NAND decoder using 2-input predecoders

WL 1

WL 0

A0A1 A0 A1 A0 A1 A0A 1

A 2A3 A2 A3 A2 A3 A2 A3

A1 A 0

A0

A1

A3 A2

A2

A3

Splitting decoder into two or more logic layers produces a faster and cheaper implementation
Memory

4 input pass-transistor based column decoder

BL0 S0 S1 S2 S3 BL1 BL2 BL3

A1

2 input NOR decoder

A0

dvantage: speed (tpd does not add to overall memory access time) only 1 extra transistor in signal path sadvantage: large transistor count
Memory

4-to-1 tree based column decoder

BL0 A0 A0 A1 A1 BL1 BL2 BL3

Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Memory

Decoder for circular shift-register

VDD WL0 R VDD R VDD WL1 R VDD VDD WL2 ... VDD VDD

Memory

Sense Amplifiers
t C V = ---------------p Iav large make V as small as possible small

Idea: Use Sense Amplifer small transition input

Memory

s.a. output

Differential Sensing - SRAM

VDD V DD BL PC VDD BL x SE y M3 M1 M4 M2 M5 x x SE VDD y x

EQ

WLi

(b) Doubled-ended Current Mirror Amplifier SRAM cell i Diff. Sense x x Amp y y D D y x SE VDD y x

(a) SRAM sensing scheme.

Memory

(c) Cross-Coupled Amplifier

Latch-Based Sense Amplifier

EQ BL VDD SE BL

SE

Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Memory

Single-to-Differential Conversion
WL BL x Diff. S.A. x
+ _

cell y

Vref

How to make good Vref?

Memory

Address Transition Detection

VDD

A0

DELAY td

ATD

ATD

A1

DELAY td

AN-1

DELAY td

...

Memory

Reliability and Yield

Memory

Open Bit-line Architecture Cross Coupling

EQ

WL1 BL CBL C

WL0 WLD CWBL

CWBL

WLD

WL0

WL1 BL

Sense C C Amplifier C C C

CBL

Memory

Folded-Bitline Architecture
WL1 BL ... CBL C C C WL1 WL0 WL0 CWBL WLD WLD x C C Sense EQ Amplifier x CWBL y y

BL

CBL

Memory

Transposed-Bitline Architecture
BL BL BL BL" (a) Straightforward bitline routing. BL BL BL BL" (b) Transposed bitline architecture.
Memory

Ccross SA

Ccross SA

Alpha-particles
-particle WL BL n+ SiO2 VDD

1 particle ~ 1 million carriers

Memory

Yield

Yield curves at different stages of process maturity (from [Veendrick92])

Memory

Redundancy
Redundant rows : Redundant columns Memory Array Row Decoder Fuse Bank Row Address

Column Decoder
Memory

Column Address

Semiconductor Memory Trends

Memory Size as a function of time: x 4 every three years

Memory

Semiconductor Memory Trends

Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation

Memory

Semiconductor Memory Trends

Technology feature size for different SRAM generations

Memory