FPGA Design Flow

Verilog RTL Coding Verilog model Functional/Gate simulation & Verification Verilog Netlist Verilog test bench

Design Stage Tools

Verilog Design Verification Synthesis Text Editor Emacs, Nedit, Vi Modelsim SE Leda Xilinx ISE - XST Synplify Pro Xilinx ISE Xilinx Impact

sdc

Logic Synthesis

ucf

ngc

Pyhsical Design & Implementation

Physical Layout

par

Device Configuration

bit

Digital Design Flow

Verilog test bench Verilog Coding Verilog RTL

Design Stage Tools

Verilog Design Text Editor Emacs, Nedit, Vi Mentor - Modelsim SE Synopsys - Leda Synposys - Design Compiler

Functional/Gate Simulation/Verification

Verification Synthesis

Logic Synthesis Verilog Netlist

scr

Test Insertion
Test-Insertion
test.scr

Synopsys - TetraMax Mentor - Fastscan Synopsys - Primetime Cadence - Sensemble/ SOC Encounter Synopsys - Apolllo
Cadence - CTgen

Static Timing Anal. Place & Route

_pre.sdf

Static Timing Analysis Floorplanning/ Place & Route

techfile.lef techfile.gcf *.lef *.tlf *.def

Clock Tree Insertion

Timing Extraction DRC/ANT Checking

LVS

ctgen.con

Clock Tree Insertion Final Layout

Synopsys - StarRXT Cadence - Pearl Cadence - Assura, Dracula Mentor Callibre

Cadence - Assura, Dracula Mentor Callibre

_post.sdf

Timing Extraction

Final Design Check DRC/LVS

gds2

Analogue Design Flow

Schematic Entry

Design Stage
Schematic Entry

Tools
Composer Spectre Virtuosso Assura Calibre Spectre

Simulation

Simulation Layout
techfile.lef techfile.gcf *.lef *.tlf *.def

Layout

Pyhsical Verification/ Extraction Post-Layout Simulation

Physical Verification / Extraction

Post-Layout Simulation

gds2

Mixed Signal Design Flow

Digital Flow
Cadence - SpectreVerilog Cadence -UltraSim Co-simulation Environement

Analog Flow

Verilog test bench

Verilog Coding

Verilog RTL

Schematic Entry

Behavioural Modelling

Functional/Gate Simulation/Verification Simulation

Logic Synthesis
Verilog Netlist Test-Insertion

scr test.scr

Layout

_pre.sdf

Static Timing Analysis

Floorplanning/ Place & Route
techfile.lef techfile.gcf *.lef *.tlf *.def

techfile.lef techfile.gcf *.lef *.tlf *.def

ctgen.con

Clock Tree Insertion Final Layout

Timing Extraction Final Design Check DRC/LVS

Physical Verification / Extraction

_pst.sdf

Post-Layout Simulation

gds2

gds2