---------------------------- Carry-Save Adder library ieee; use ieee.std_logic_1164.

all; package csadder_pkg is constant datawidth : positive := 16; -- carry save add, 3 words in, 2 words out, redundant notation -- outputs are one bit wider to avoid overflow in adder component csadder is port(adden1, adden2, adden3 : in std_logic_vector(datawidth-1 downto 0); sum_part1, sum_part2: out std_logic_vector(datawidth dow nto 0)); end component csadder; -- convert carry save to binary, if you would like to be able to underst and the result component binary_out is port(sum_part1, sum_part2: in std_logic_vector(datawidth downto 0); sum_unified : out std_logic_vector(datawidth downto 0)); end component binary_out; end csadder_pkg; library ieee; use ieee.std_logic_1164.all; library work; use work.csadder_pkg.all; entity csadder is port(adden1, adden2, adden3 : in std_logic_vector(datawidth-1 downto 0); sum_part1, sum_part2: out std_logic_vector(datawidth dow nto 0)); end csadder; -- sum_part1 full adder sum outputs -- sum_part2 full adder carry outputs (shifted by one bit) -- sum_unified sum with all carries propagated (not part of carry-save adder architecture carry_save_adder of csadder is begin -- full adder sums sum_part1 <= '0' & (adden1 xor adden2 xor adden3); -- and full adder carries sum_part2 <= ((adden1 and adden2) or (adden1 and adden3) or (adden2 and adden3)) & '0'; end carry_save_adder; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all; library work; use work.csadder_pkg.all; entity binary_out is port(sum_part1, sum_part2: in std_logic_vector(datawidth downto 0); sum_unified : out std_logic_vector(datawidth downto 0)); end binary_out; architecture cs_to_binary of binary_out is begin -- sum_unified = (sum_part1+sum_part2) = (adden1+adden2+adden3) -- sum_unified is slower, but is only for demonstration purposes sum_unified <= sum_part1 + sum_part2; end cs_to_binary;