---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 15:22:05 09/16/2013 -- Design Name: -- Module Name: ENCODERA - Behavioral -- Project

Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ENCODERA is Port ( RESET CLK_IN CLK EXP_SEL UTOB_EN BP_IN DAC_B end ENCODERA; : in STD_LOGIC; : in STD_LOGIC; : in STD_LOGIC; F_SEL : IN STD_LOGIC; : in STD_LOGIC_VECTOR (2 downto 0); : in STD_LOGIC; : in STD_LOGIC; : out STD_LOGIC_VECTOR (7 downto 0));

architecture Behavioral of ENCODERA is SIGNAL TT : STD_LOGIC:='0'; signal sig1 : std_logic; -- signal from 1st flop signal sig2 : std_logic; -- signal from 2nd flop signal edt : std_logic; signal CLOCK : std_logic:='0'; signal n : integer range 0 to 3000:=0; begin PROCESS(RESET,CLK,EXP_SEL) variable bit_dec : std_logic; BEGIN if RESET='1' then bit_dec:='0'; elsif CLK'event and CLK='0' then IF EXP_SEL="010" then bit_dec:= bit_dec xor BP_IN;

else bit_dec:= '0'; end if; end if; TT<=bit_dec; END PROCESS; n<=736 when F_SEL='0' else 1472; --184 AND 592

process(CLK_IN) variable t : integer range 0 to 3000 :=0; begin if CLK_IN'event and CLK_IN='1' then t:=t+1; if t>=n then CLOCK<=not CLOCK; t:=0; end if; end if; end process; edge : process(RESET,CLOCK,TT) begin if RESET = '1' then sig1 <= '0'; sig2 <= '0'; elsif CLOCK'event and CLOCK='1' then sig1 <= TT; sig2 <= sig1; end if; end process edge; edt <= sig1 xor sig2; --DAC_B<=x"FF" WHEN edt='1' else x"00"; count : process(EXP_SEL,UTOB_EN,CLOCK,RESET,edt,TT) begin if RESET='1' then DAC_B<=x"7F"; elsif CLOCK'event and CLOCK='0' then if EXP_SEL="010" AND UTOB_EN='1' THEN if edt='1' and TT='1' then DAC_B<=x"FF"; elsif edt='1' and TT='0' then DAC_B<=x"00"; else DAC_B<=x"7F"; end if; end if; END IF; END PROCESS; end Behavioral;