Professional Documents
Culture Documents
Joshi-VLSI Signal Processing
Joshi-VLSI Signal Processing
Introduction
Efficient implementation of signal processing algorithms required for real time signal processing Many ways
Working at architectural level Implementation level
Using Digital Signal Processors Using FPGAs Using Full custom design
IUCEE Workshop presentation-YVJoshi
Complex
Neuro Computing Computer Vision Artificial organ development
etc
IUCEE Workshop presentation-YVJoshi
Applications
MP3 players Mobiles Embedded systems (automobiles, aircraft, satellite etc) Robots Projection systems Biomedical/Life support systems Communication systems- Software defined radios, etc
IUCEE Workshop presentation-YVJoshi
Architectural level
Techniques of reducing the critical path
Pipelining and Parallel Processing Retiming Unfolding Folding
Implementation levelFPGA
Resources
Basic units
Adder Multiplier and A delay
Example
A second order notch filter 1 2 b0 b1 z b2 z H ( z) a0 a1 z 1 a2 z 2
Example (Contd)
With values of
1 tan(B / 2) k1 cos( 0 ) and k 2 1 tan(B / 2)
With 0 being the notch frequency and B being the rejection bandwidth implementation with only two multipliers with minimum critical path
IUCEE Workshop presentation-YVJoshi
Thanks
Contact : Y. V. Joshi Yashwant.joshi@gmail.com