IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO.

12, DECEMBER 2007

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PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies
Zhiyu Liu, Student Member, IEEE, and Volkan Kursun, Member, IEEE
AbstractA circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only pchannel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods. Index TermsDynamic CMOS, electron tunneling, gate oxide tunneling, hole leakage, low-leakage sleep mode, multithreshold voltage, subthreshold leakage current.

Fig. 1. Comparison of the maximum gate oxide leakage current of an nMOS =V =V ) in two successive CMOS technology transistor (V = V generations.

I. INTRODUCTION EATURE size scaling in MOSFETs requires reducing the supply and threshold voltages. The lowering of threshold voltages leads to an exponential increase in the subthreshold leakage current. Several circuit techniques based on multiple threshold voltage (multiple ) CMOS technologies are described in the literature for reducing the subthreshold leakage current [1][6], [15], [16], [22]. The effect of these multiple CMOS circuit techniques on the gate oxide leakage current characteristics, however, has not been explored until recently. In the CMOS technologies with a gate insulator thicker is orders than 20 , the gate oxide leakage current of magnitude smaller than the subthreshold leakage current [8], [10]. The has, therefore, typically been ignored in the previous CMOS technologies. is caused by the direct tunneling of the electrons and holes through the insulating gate dielectric layer. The tunneling probability of carriers in increases with the scaling of the gate oxide thickness each new technology generation. The tunneling probability also has a strong dependence on the voltage difference across the

Manuscript received August 11, 2005; revised May 28, 2006. This work was supported by a Grant from the Wisconsin Alumni Research Foundation (WARF). The authors are with the Department of Electrical and Computer Engineering, University of WisconsinMadison, Madison, WI 53706-1691 USA (e-mail: zhiyuliu@wisc.edu). Digital Object Identier 10.1109/TVLSI.2007.903947

gate dielectric layer. The variation of the with the supply in two successive CMOS technologies (45 and voltage 65 nm) is shown in Fig. 1. While advancing from the 65-nm technology node to the 45-nm technology node, the reduction by 3 increases the by up to 14.9 times depending of on the voltage difference across the gate oxide, as illustrated in Fig. 1. is in the range of 1216 in the current CMOS The technologies [7], [8], [10]. Such a thin leads to a signicant gate tunneling current. The variation of the gate oxide and subthreshold leakage currents of an nMOS transistor with the supply voltage at two different die temperatures is shown in Fig. 2, assuming a 45-nm CMOS technology. At 110 C, the is 6.7 times higher than the gate oxide leakage current (operating at the nominal supply voltage 0.8 V) as illustrated in Fig. 2. Alternatively, at the room temperature, the is 2.5 times higher than the subthreshold leakage current. Due to the aggressive scaling of , the gate dielectric tunneling has become a primary leakage mechanism. Particularly at the low die temperatures during long idle periods, most of the power consumption of a CMOS circuit could occur due to gate oxide leakage. New circuit techniques aimed at simultaneously reducing the subthreshold and gate oxide leakage currents are, therefore, highly desirable. A circuit technique for lowering the gate oxide leakage current in domino logic circuits is presented in [11]. Using P-type (predischarge) domino is proposed in order to exploit the lower gate oxide leakage current characteristics of the pMOS transistors as compared to the nMOS transistors. The transistors

1063-8210/$25.00 2007 IEEE

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Fig. 3. Maximum gate oxide and subthreshold leakage current states in nMOS and pMOS transistors. (a) Maximum gate oxide leakage current state. (b) Maximum subthreshold leakage current state.

Fig. 2. Comparison of the subthreshold and gate oxide leakage currents of an nMOS transistor for various supply voltages at two different die temperatures. I :V = 0 and V = V .I :V = V = V = V .

in a p-type domino circuit, however, must be sized larger for achieving similar speed as compared to an n-type domino circuit. Although this technique can be effective for reducing the leakage current, the area and active power consumption are signicantly increased. In this paper, a new circuit technique with lower overheads of delay and energy is proposed to reduce both the subthreshold and gate oxide leakage currents in domino logic circuits. pMOS sleep transistors are utilized along with a dual threshold voltage (dual- ) CMOS technology to ensure that an idle domino circuit is placed into a low leakage state. The proposed technique reduces the total leakage power by up to 77% and 96.9% as compared to the standard dual- domino logic circuits at 110 C and 25 C, respectively. The paper is organized as follows. The leakage current characteristics of the domino gates are described in Section II. The new circuit technique to reduce the total leakage power consumption is presented in Section III. The simulation results are given in Section IV. Some conclusions are offered in Section V. II. LEAKAGE CURRENT CHARACTERISTICS OF DYNAMIC CMOS CIRCUITS The leakage current characteristics of dynamic CMOS circuits are explored in this section. The subthreshold and gate oxide leakage currents produced by the nMOS and pMOS transistors are described in Section II-A. The leakage current characteristics of the previously published sleep switch dualdomino logic circuit techniques in the literature are discussed in Sections II-B and II-C. A. Comparison of Leakage Currents in n-Channel and p-Channel Devices The subthreshold and gate oxide leakage currents produced by the nMOS and pMOS transistors are illustrated in has four components, as shown in Fig. 3(a): Fig. 3. , gate-to-drain tunneling gate-to-channel tunneling current , gate-to-source tunneling current , and current gate-to-body tunneling current . The tunneling current

Fig. 4. Comparison of the gate oxide leakage current produced by the same sized nMOS and pMOS transistors for various voltages applied across the gate insulator in a 45-nm CMOS technology. V = V =V =V .

is shared from the gate terminal to the conducting channel and are the between the source and drain terminals [14]. edge tunneling currents from the gate terminal to the source and drain terminals through the gate-to-source and gate-to-drain is typically several orders of overlap areas, respectively. magnitude smaller than the other three components of the gate tunneling current [9]. The highest gate oxide leakage current is observed when a transistor operates in the active region with the maximum voltage difference across the gate-to-source and the gate-to-drain terminals, as illustrated in Fig. 3(a). Alternatively, the highest subthreshold leakage current is observed when a cutoff transistor is biased with the maximum voltage difference between the source and drain terminals, as depicted in Fig. 3(b). In a technology utilizing silicon-dioxide as the gate dielectric material, the probability of hole tunneling is much smaller than the probability of electron tunneling through the gate oxide for a pMOS device is, (discussed in Appendix I). The therefore, signicantly lower as compared to an nMOS device and the same voltage difference across the with the same gate insulator. A comparison of the gate oxide leakage currents produced by the n-channel and p-channel devices with similar physical dimensions (width, length, and ) in a 45-nm CMOS produced by an nMOS technology is shown in Fig. 4. The transistor is up to 40 times (depending on the voltage difference across the gate oxide) higher as compared to a pMOS transistor, as illustrated in Fig. 4.

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Fig. 6. Two cascaded dual-V domino OR gates in the sleep mode. The dominant gate oxide leakage current conduction paths in the sleep mode are illustrated with arrows. H: high. L: low. High-V transistors are represented with a thick line in the channel region.

Fig. 5. Two-input standard dual-V domino OR gate. High-V transistors are represented with a thick line in the channel region.

B. Dual-

Domino Logic

Employing dual- transistors for subthreshold leakage current reduction in domino logic circuits was rst proposed by Kao [3]. A two-input standard dual- domino OR gate is shown in Fig. 5. The critical signal transitions that determine the delay of a domino logic circuit occur along the evaluation path. In a dual- domino circuit, therefore, all of the transistors that can be activated during the evaluation phase have a low- . Alternatively, the precharge phase transitions are not critical for the performance of a domino logic circuit. Therefore, those transistors that are active during the precharge phase have a high[22]. Provided that all of the high- transistors are cutoff in a dual- domino logic circuit, the subthreshold leakage current is signicantly reduced as compared to a low- circuit [5]. The clock is gated high, turning off the high- pull-up transistor when a domino logic circuit is idle. In a standard dualdomino logic circuit, the modes of the remaining high- transistors (other than the pull-up transistors) are determined by the input vectors applied after the clock is gated high [15]. A sleep switch technique that places an idle domino logic circuit into a low subthreshold leakage current state, regardless of the input vectors, is presented in [15]. A high- nMOS switch is added to the dynamic node of a domino gate as shown in Fig. 6. The operation of this transistor is controlled by a separate sleep signal. During the standby mode of operation, the clock signal is gated high, turning off the high- pull-up transistor of each domino gate. The sleep signal transitions high, turning on the sleep switch. The dynamic node of the domino gate is discharged through the sleep switch and the output node transitions to high. Following the low-to-high transition of the output of a sleep switch dual- domino gate, the subsequent gates (fed by the noninverting signals) also evaluate and discharge in a domino fashion. After the node voltages settle to a steady state, all of the high- transistors are cutoff, thereby reducing the subthreshold leakage current [15]. Similar subthreshold leakage current reduction techniques based on discharging and charging the dynamic and output nodes, respectively, of all of the domino gates in a dynamic

Fig. 7. Two cascaded two-input dual-V domino OR gates with high-V sleep transistors. The dominant gate oxide leakage current conduction paths in the sleep mode are illustrated with arrows. H: high. L: low. High-V transistors are represented with a thick line in the channel region.

circuit have been proposed in [2][4]. The high output of an idle domino gate, however, places the fan-out domino circuits into the highest gate oxide leakage current state, as illustrated in Fig. 6. The techniques proposed in [2][4], [15], and [16], therefore, increase the gate oxide leakage current while reducing the subthreshold leakage current. In the sub-65-nm CMOS technologies, the signicant increase in the gate oxide leakage current could negate the subthreshold leakage current reduction provided by these techniques, thereby increasing the total leakage power consumption in the sleep mode. C. NMOS Sleep Switch DualDomino Logic

In addition to setting the dynamic node voltage low for reducing the subthreshold leakage current [15], the output node of a domino logic circuit should also be placed into a low voltage state in order to suppress the gate oxide leakage current into the fan-out gates. A technique to force both the dynamic and output nodes of a domino logic circuit into a low voltage state in the standby mode is proposed in [17]. Two high- nMOS sleep transistors N1 and N2 are placed at the dynamic and output nodes, respectively, as illustrated in Fig. 7. In the standby mode, the clock is gated high. The sleep signal is set high turning on N1 and N2. The dynamic and output nodes are discharged through N1 and N2, respectively. P3 is cutoff to avoid a static dc current path through P4 and N2. After the dynamic and output nodes are discharged, the two nMOS sleep transistors (N1 and N2) are both in the maximum gate oxide leakage current state [see Fig. 3(a)]. The sleep transistors (N1, N2, and P3) are required within every domino gate in a dynamic circuit designed with the technique presented in [17]. The gate oxide leakage current overhead of the nMOS sleep transistors,

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Fig. 8. Two-input dual-V domino OR gate with low-V (P1 and P2) and high-V (P3) pMOS sleep transistors. High-V transistors are represented with a thick line in the channel region.

Fig. 9. Two-input dual-V domino OR gate with high-V pMOS sleep transistors. High-V transistors are represented with a thick line in the channel region.

therefore, imposes a serious limitation to the leakage current reduction that can be provided by this technique. III. PMOS-ONLY SLEEP SWITCH DUALDOMINO LOGIC

A new circuit technique with enhanced effectiveness to simultaneously reduce the subthreshold and gate oxide leakage currents in domino logic circuits is proposed in this paper. Only p-type sleep transistors are employed in order to reduce the gate oxide leakage current overhead of the new sleep switch circuit technique. Since the gate tunneling current produced by a pMOS transistor is much smaller than an nMOS transistor, the pMOS-only sleep switch circuit technique offers a signicant reduction in the total leakage current as compared to the previously published schemes. The proposed circuit technique is illustrated in Fig. 8. Two low- pMOS sleep transistors P1 and P2 are added to the dynamic and output nodes, respectively. Provided that the dynamic node is discharged in the sleep mode, the pMOS transistor (P4) in the output inverter is turned on. The output inverter and P2 .A produce a static dc current if P4 is directly connected to high- pMOS sleep transistor (P3) is employed in series with P4 in order to eliminate the static dc current path through P4 and P2 and to suppress the subthreshold leakage current produced by the output inverter in the sleep mode. In the active mode, the sleep signal is set high. P1 and P2 are cutoff and P3 (driven by the inverted sleep signal) is turned on. The proposed domino circuit operates similar to a standard domino gate. In the standby mode, the clock is gated high, turning off the high- pull-up transistor. The sleep signal is set low, turning on P1 and P2. P3 is cutoff by the inverted sleep signal. The dynamic node is discharged to a voltage level equal to the threshold voltage of a low- pMOS transistor through P1. The dynamic and output nodes are eventually discharged to (after P1 and P2 are a steady-state voltage less than cutoff) by the high subthreshold leakage currents of the lowtransistors in the pull-down network and the output inverter and the gate-oxide leakage current into the fan-out gates. After the node voltages settle to a steady state, all of the high- transistors are strongly cutoff, signicantly reducing the subthreshold

leakage current. Similarly, the voltages across the gate insulating layers of most of the transistors are suppressed, thereby lowering the gate oxide leakage current. Provided that a dual- CMOS technology is employed, the noise immunity of a domino logic circuit is weakened due to the high- keeper transistor [5], [15]. Using low- sleep transistors could further increase the noise vulnerability of the domino circuits since the sleep switches can be turned on by coupling noise to the sleep signal line. An alternative pMOS-only sleep switch technique based on high- sleep transistors is also proposed in this paper. Three high- pMOS sleep transistors (P3, P5, and P6) are employed with the second proposed technique, as illustrated in Fig. 9. The current produced by a high- transistor is smaller as compared to a low- transistor with similar physical dimensions. Employing high- sleep transistors, therefore, enhances the noise immunity as compared to the rst proposed technique. Due to the reduced current provided by the high- sleep transistors, however, the discharging speed of the dynamic and output nodes is reduced while entering the sleep mode. The size of the high- sleep transistors should be increased in order to maintain a similar sleep delay as compared to the rst proposed technique. The active power consumption of the second proposed technique is, therefore, higher as compared to the rst proposed technique (for example, for an eight-input domino OR gate, the active mode power consumption is increased by 2.3% as compared to the rst proposed technique while maintaining a similar sleep delay). IV. SIMULATION RESULTS BSIM4 device models are used in this paper for an accurate estimation of the gate oxide leakage current [14]. The following circuits are simulated in a 45-nm CMOS technology 0.22 V, 0.35 V, ( 0.8 V): cascaded multistage two-input domino AND and gates (AND2), cascaded multistage two-input, four-input, and eight-input domino OR gates (OR2, OR4, and OR8, respectively), and a 16-bit domino multiplexer (MUX16). All of the circuits (other than MUX16) are composed of three stages. Each gate drives a fan-out of four. The domino gates in the rst stage are footed while the domino gates in the second and third stages are footless. All of the circuits are designed with the following three techniques: standard dual- domino (dual- ), the technique

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TABLE I STEADY-STATE NODE VOLTAGES (MILLIVOLTS) WITH THE DUAL-V -LK TECHNIQUE

Fig. 10. Comparison of the active mode power consumption of the three domino circuit techniques. The active mode power consumption is normalized to the power consumption of the standard dual-V technique for each circuit.

presented in [17] (dual- -YWK), and the circuit technique proposed in this paper as illustrated in Fig. 8 (dual- -LK). The sleep mode data are measured at 25 C and 110 C assuming long and short idle periods, respectively. Alternatively, the active mode data are measured at a worst case temperature of 110 C. A 3-GHz clock is applied to the circuits. To have a reasonable comparison, the circuits are sized to have a similar worst case propagation delay with each technique. A. Area Overhead and Active Mode Power The layouts of the circuits are drawn assuming MOSIS deep submicrometer design rules [21]. As shown in Fig. 8, a highpMOS transistor (P3) is placed in series with the low- pMOS transistor of the output inverter in the dual- -LK circuits. Physical size of pMOS transistors in the output inverters of dual-LK circuits must be increased to provide an evaluation delay similar to the standard dual- circuits. Furthermore, two extra pMOS sleep transistors (P1 and P2) are added to the dynamic and output nodes. The areas of the proposed pMOS sleep switch circuits are, therefore, increased by up to 82% (OR2) as compared to the standard dual- circuits based on the layout area comparison. The active power consumption of the domino circuits is shown in Fig. 10. In the dual- -YWK and dual- -LK circuits, two pMOS transistors are placed in series in the pull-up path of the output inverter. The driving capability of the output inverter is, therefore, degraded. Since P3 has a high- , the pull-up strength of the output inverter is further reduced. Increasing the physical size of the dual- -LK and dual- -YWK circuits in order to provide a propagation delay similar to the standard dual- circuits increases the parasitic capacitance. Furthermore, the parasitic capacitance at the dynamic and output nodes is increased due to the sleep transistors. The dual- -LK technique therefore increases the active mode power consumption by 6% (MUX16) to 21% (AND2) as compared to the standard dual- domino logic circuit technique. Similarly, the dual- -YWK technique increases the active mode power consumption by 3% (OR8) to 14% (AND2) as compared to the standard dual- domino circuits. For a higher fan-in, the active power consumption overheads of the dual- -LK and

dual- -YWK techniques become smaller since the parasitic capacitance introduced by the sleep transistors become less important as compared to the parasitic capacitance of the pull-down network transistors. The dual- -LK technique increases the active power consumption by 1.9% (MUX16) to 10.7% (OR2) as compared to the dual- -YWK technique. This difference is primarily due to the higher parasitic capacitance of the pMOS sleep transistors (P1 and P2 in Fig. 8) as compared to the nMOS sleep transistors (N1 and N2 in Fig. 7). B. Sleep Mode Leakage Power Consumption at High Temperature In the dual- -LK circuits, the pMOS sleep transistors are not capable of directly discharging the dynamic and output rise problem). The high subthreshold nodes to zero volts ( leakage currents of the low- transistors in the pull-down network and the output inverter and the gate-oxide leakage current into the fan-out gates continue to discharge the dynamic and output nodes after P1 and P2 are turned off. The steady-state dynamic and output node voltages in the dual- -LK domino , as listed in Table I. circuits are both below The subthreshold leakage current produced by a domino logic circuit strongly depends on the dynamic and output node voltages [5]. Two input conditions are simulated to evaluate the leakage current in the sleep mode with the standard dualtechnique. The rst condition assumes that all of the inputs applied to the rst stage gates are low (high dynamic node voltage state). The second condition assumes that all of the inputs applied to the rst stage gates are high (low dynamic node voltage state). The total leakage power consumption characteristics of the domino circuits with the three techniques at 110 C are shown in Fig. 11. The leakage power reduction offered by the proposed circuit technique is listed in Table II. The dual- -LK technique reduces the total leakage power by 81.9% to 97.3% as compared to the standard dual- circuits driven with low inputs, as listed in Table II. For a higher fan-in, the leakage power reduction provided by the dual- -LK technique is enhanced (OR2: 87.6% versus OR8: 95.5%). For a dual- CMOS technology to be effective for reducing the subthreshold leakage current, the inputs to a standard dual- domino gate must be maintained high during the sleep mode. Maintaining the inputs high ensures that the subthreshold leakage current is produced by the high- transistors. A high input vector, therefore, reduces the leakage power consumption by 57.1% (AND2) to 88.6% (OR4) as compared to a low input vector. The leakage reduction provided by the high input vector is smaller for AND2 as compared to the other circuits since

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Fig. 11. Comparison of the leakage power consumption of the domino circuits with the three circuit techniques at 110 C. The leakage power is normalized to the leakage power of the standard dual-V technique with low inputs for each circuit.

Fig. 12. Comparison of the total leakage power consumption of the domino circuits with the three circuit techniques at 25 C. The leakage power is normalized to the leakage power of the standard dual-V technique with low inputs for each circuit.

TABLE II LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-V -LK TECHNIQUE AS COMPARED TO THE DUAL-V -YWK AND STANDARD DUAL-V TECHNIQUES AT 110 C

TABLE III TOTAL LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-V -LK AS COMPARED TO THE DUAL-V -YWK AND STANDARD DUAL-V TECHNIQUES AT 25 C

the subthreshold leakage current produced by the pull-down network of AND2 is reduced by the stack effect when the inputs are maintained low. A high input vector places the transistors in the pull-down network of a standard dual- domino logic gate into the highest gate oxide leakage current state. Since the gate oxide leakage current of a low- nMOS transistor is signicantly higher than the subthreshold leakage current of a high- transistor (see Appendix II), the gate tunneling current produced by the pulldown network dominates the total leakage power consumption of a standard dual- domino gate when the inputs are maintained high. The dual- -LK technique suppresses both the subthreshold and the gate oxide leakage by discharging the dynamic and output nodes. The dual- -LK technique thereby reduces the total leakage power by 45.6% to 77.0% as compared to the standard dual- circuits with high inputs, as listed in Table II. The sleep switches at the dynamic and output nodes are sized much smaller than the precharge transistor, pull-down network transistors, and the transistors in the output inverter in the dual- -YWK and dual- -LK circuits. Particularly for the wide fan-in gates, the gate oxide leakage current of the sleep switches is a relatively small portion of the total leakage current produced at a high die temperature. The difference between the total leakage power consumption of the dual- -YWK and dual- -LK techniques is within 10.7% (OR4) at 110 C. C. Sleep Mode Leakage Power Consumption at Room Temperature The total leakage power consumption characteristics of the domino circuits with the three techniques at the room temper-

ature are shown in Fig. 12. The leakage power reduction offered by the proposed circuit technique is listed in Table III. The dual- -LK technique reduces the total leakage power by 87.7% to 96.4% as compared to the standard dual- circuits driven with low inputs, as listed in Table III. For a higher fan-in, the leakage power savings provided by the dual- -LK technique is increased (OR2: 91.6% versus OR8: 96.4%). The gate oxide leakage current produced by the nMOS transistors is the dominant source of the total leakage power consumption at the room temperature (see Appendix II). A high input vector places the transistors in the pull-down network into the maximum gate oxide leakage current state. The leakage power reduction provided by the proposed circuit technique is, therefore, higher when the standard dual- domino circuits are driven with high inputs. The dual- -LK technique reduces the total leakage power by 90.2% to 96.9% as compared to the standard dual- circuits with high inputs, as listed in Table III. The standard dual- circuits driven by high inputs consume more power than the standard dual- circuits driven by low inputs in the sleep mode, as illustrated in Fig. 12. This result indicates a dramatic change in the node voltage dependent leakage power characteristics of the standard domino logic circuits fabricated in technologies subject to signicant gate dielectric tunneling current [18][20]. The subthreshold leakage currents produced by AND2 and MUX16 are reduced by the stack effect when the inputs are low [15]. Therefore, the shift in the leakage power characteristics is more signicant in the gates with stacked pull-down transistors.

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An nMOS sleep transistor can produce a signicantly higher gate oxide leakage current as compared to a pMOS transistor (see Appendix I). The high- nMOS sleep switches proposed in [17] cause a signicant increase in the total leakage current of an idle dual- domino gate. The highest gate oxide leakage current produced a pMOS transistor is more than an order of magnitude smaller than the highest gate oxide leakage current produced by an nMOS transistor. Furthermore, there is zero voltage difference across the gate insulator layers of P1 and P2 (see Fig. 8) throughout the idle mode with the dual- -LK technique . The proposed pMOS-only sleep switch technique, therefore, effectively eliminates the gate oxide leakage current overhead introduced by the sleep transistors. The dual- -LK technique reduces the total leakage power by 22.2% to 43.8% as compared to the dual- -YWK technique, as listed in Table III. D. Energy Overhead at High Temperature The energy overhead of a dual- -LK circuit for implementing a low leakage sleep mode is discussed in this section. The circuit is assumed to be operating at a worst case temperature of 110 C before entering the idle mode. The energy overhead of the proposed circuit technique is low, providing a net savings in total energy consumption shortly after the beginning of the idle mode. The energy overhead data are measured at this worst case high die temperature assuming the junction temperature does not signicantly change during the short duration of time at the beginning of the idle mode. When a sleep switch domino logic circuit is idle, the clock is gated high. The sleep signal should be applied after the low-tohigh edge of the clock signal propagates to the gates in the last stage of a clock-delayed domino logic circuit. Activating the sleep switches after the low-to-high transition of the clock ensures that no short-circuit power is consumed while entering the sleep mode. The dynamic and output nodes in all of the domino gates are discharged through the sleep transistors. After the node voltages settle, all of the high- transistors are strongly cut off, minimizing the subthreshold leakage current. Similarly, the gate oxide leakage current is minimized by discharging the output nodes. After the clock is gated and the sleep switches are activated, it takes 2.4 to 7.5 ns (depending upon the circuit type) to place the circuits into a low leakage state. Before the end of an idle mode, the sleep signal transitions high, cutting off the sleep switches attached to the dynamic and output nodes while activating the sleep transistors in the output inverters. Disabling the dynamic and output node sleep transistors before activating the clock is necessary to avoid short-circuit current while leaving the idle mode. The clock is reactivated and all of the dynamic nodes are recharged to activate (wake-up) a sleeping domino circuit. The reactivation time is equal to the time it takes to precharge a domino circuit. The energy overhead of a three-stage sleep switch circuit composed of four-input domino OR gates with a fan-out of four is evaluated in this section. Changing the mode of operation of the sleep transistors to place a dual- domino logic circuit into standby mode requires a specic amount of energy. Additional energy is dissipated at the end of an idle period while precharging the dynamic nodes in order to reactivate a domino logic circuit. Depending upon the input vectors, some or none

Fig. 13. Cumulative standby energy dissipation of the dual-V -LK and standard dual-V circuits for two different input vectors. The step change of the dual-V -LK energy characteristics at the rst nanosecond is the energy overhead for implementing a sleep mode with the dual-V -LK technique.

of the dynamic nodes in the standard dual- circuits are discharged during the sleep mode. Alternatively, all of the dynamic nodes in a pMOS-only sleep switch domino logic circuit are discharged during the sleep mode, independent of the input vectors. The activation energy required by the sleep switch circuit technique is, therefore, higher than the standard dual- circuit technique. In order to justify the proposed sleep switch circuit technique to force a circuit into a low leakage state, the total energy consumed to enter and leave the sleep mode must be less than the total savings in standby leakage energy. The cumulative energy dissipated in the standby mode by the standard dual- and the dual- -LK circuits is shown in Fig. 13. The leakage energy per cycle is assumed to be constant. The cumulative energy of a standard dual- domino circuit is only affected by the subthreshold and gate oxide leakage currents during the standby mode. Alternatively, both the cumulative leakage energy and the energy overhead of entering and leaving the sleep mode are included in the energy characteristics of the dual- -LK circuit. The total energy overhead of the dual- -LK circuit technique is independent of the duration of the idle mode (assuming the duration of idle mode is longer than the time needed to enter the low leakage sleep mode, 3.7 ns for the dual- -LK circuit under consideration). The total energy overhead of the proposed technique is included as an energy step in the rst nanosecond of the standby mode (see Fig. 13). Similar to the dual- energy characteristics, after entering the sleep mode, the dual- -LK circuit energy consumption is due to only the leakage currents. Since the standby leakage energy of dual- -LK is signicantly lower than the standard dual- circuit, the dual- -LK energy characteristics have a much smaller slope as compared to the energy characteristics of the standard domino circuit (see Fig. 13). A specic amount of time in the idle mode, also dependent upon the input vectors, is necessary for the cumulative leakage energy of a standard dual- circuit to exceed the cumulative energy of a dual- -LK circuit. The intersection of the dual- -LK and standard dual- cumulative energy characteristics are evaluated to determine the necessary minimum duration of the sleep mode such that the pMOS-only sleep switch circuit technique offers a net savings

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in energy as compared to a standard dual- circuit. As illustrated in Fig. 13, the cumulative standby energy of the standard dual- and dual- -LK circuits exhibit different behavior depending upon the input vectors. The leakage current produced by the standard dual- circuit is smaller for a high input vector as compared to a low input vector (see Fig. 11). Alternatively, the leakage current of the dual- -LK is virtually independent of the input vector. However, depending upon the input vector, the relative energy overhead of the dual- -LK scheme changes. For low inputs, none of the dynamic nodes of the standard dualcircuit are discharged during the standby mode. Alternatively, all of the dynamic nodes are discharged in the dual- -LK. The relative energy overhead of the dual- -LK circuit technique required to charge the dynamic nodes to reactivate the circuit (to transition from the standby mode to the active mode) is, therefore, higher for a low input vector. As shown in Fig. 13, a minimum duration of 8.9 and 100 ns is required in the idle mode for the dual- -LK circuit technique to provide a net savings in energy as compared to the standard dual- circuit with the low and high input vectors, respectively. V. CONCLUSION In sub-65-nm CMOS technologies, both the subthreshold and gate dielectric leakage currents need to be suppressed for reducing the standby power consumption. A circuit technique based on pMOS-only sleep transistors and a dual- CMOS technology is presented in this paper for simultaneously reducing the subthreshold and gate oxide leakage currents in domino logic circuits. Both the dynamic and output nodes in a domino logic circuit are discharged through pMOS sleep transistors in the idle mode. Placing the dynamic node into a low voltage state reduces the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Furthermore, placing the output node into a low voltage state suppresses the gate dielectric tunneling currents into the fan-out gates. The proposed circuit technique also exploits the intrinsically high subthreshold and gate oxide leakage currents in scaled nanometer CMOS technologies for placing an idle domino logic circuit into a minimum leakage state. The circuit technique reduces the leakage power by up to 77.0% to 96.9% as compared to the standard dual- domino circuits in the sleep mode at the high and low die temperatures, respectively. Furthermore, by employing pMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep technique based on nMOS sleep transistors. The energy overhead of the circuit technique is low, providing a net energy savings during idle periods as short as 8.9 ns. APPENDIX I In a technology with silicon dioxide as the gate dielectric material, the tunneling current of a pMOS device is primarily due to the hole tunneling from the valence band (HVB) in the silicon substrate. The electron tunneling from the polysilicon conduction band is negligible since the electron concentration in the p+ polysilicon gate is low in a pMOS device. Alternatively, the

Fig. 14. Energy band diagrams of pMOS and nMOS transistors under inversion bias. (a) Energy band diagram of a pMOS transistor. (b) Energy band diagram of an nMOS transistor. E : Bottom of the conduction band. E : Top of the valence band. E : Fermi energy level.

electron tunneling from the conduction band (ECB) of the silicon substrate is the dominant tunneling mechanism in an nMOS transistor. The HVB of the polysilicon is negligible due to the smaller number of holes as compared to the electrons in the gate of an nMOS device. The energy barrier heights for the HVB and ECB are 4.5 and 3.1 eV, respectively, as illustrated in Fig. 14 [12], [13]. The probability of hole tunneling is, therefore, much smaller than the probability of electron tunneling through the gate oxide. The for a pMOS device is signicantly lower as compared to an nMOS device with similar physical dimensions (width, length, and ) and voltage difference across the gate insulator. The produced by a low- nMOS transistor produced by a is 47 times and 30 times higher than the low- pMOS transistor at 110 C and 25 C, respectively (see Appendix II). Replacing the nMOS sleep transistors with pMOS sleep transistors is, therefore, an effective method for reducing the gate oxide leakage current of an idle sleep switch dualdomino gate. APPENDIX II A comparison of the normalized subthreshold and gate oxide leakage currents produced by the low threshold voltage (low- ) and high threshold voltage (high- ) transistors in a dualCMOS technology is listed in Table IV. The gate oxide leakage current of a low- nMOS transistor is 4.7 times and 159.1 times higher than the subthreshold leakage current of a highpMOS transistor at the high and low die temperatures, respectively. The difference between the subthreshold leakage currents of the high- nMOS and pMOS transistors is less than 20%. As discussed in Sections II-B and II-C, maintaining inputs high is preferable to reduce the subthreshold leakage current in an idle dual- domino gate. When the inputs are maintained high, the majority of gate tunneling current in an idle wide fan-in dualdomino gate is produced by the low- pull-down network transistors while the subthreshold leakage currents are produced by the high- transistors. The gate oxide leakage current of a low- nMOS transistor is much higher than the subthreshold leakage currents of the high- transistors at both high and low temperatures. The gate tunneling, therefore, becomes the dominant leakage mechanism in an idle dual- domino gate when the inputs are high. When the gate-oxide tunneling phenomenon

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TABLE IV NORMALIZED SUBTHRESHOLD AND GATE OXIDE LEAKAGE CURRENTS OF THE LOW-V AND HIGH-V TRANSISTORS AT TWO DIFFERENT DIE TEMPERATURES

Transistor width = 1 m. Transistor length = 45 nm. Low-V = 0.22 V. = 0.8 V. I : V = 0 and V = V . High-V = 0.35 V. V I : V = V = V = V . For each temperature, the currents are normalized to the subthreshold leakage current produced by the high-V pMOS transistor.

is signicant, a small size active nMOS sleep switch can produce a considerably higher leakage current as compared to a larger cutoff high- pMOS transistor. For example, the produced by an active 0.1 m wide high- nMOS sleep tranproduced by a cutoff 12.4 m sistor is equal to the wide high- pMOS pull-up transistor in a dual- domino gate at room temperature. REFERENCES
[1] S. Shigematsu, S. Mutoh, Y. Matsuya, and J. Yamada, A 1 V high-speed MTCMOS circuit scheme for power-down applications, in Proc. IEEE Int. Symp. VLSI Circuits, 1995, pp. 125126. [2] J. T. Kao and A. P. Chandrakasan, Dual-threshold voltage techniques for low-power digital circuits, IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 10091018, Jul. 2000. [3] J. Kao, Dual threshold voltage domino logic, in Proc. Eur. SolidState Circuits Conf., 1999, pp. 118121. [4] M. W. Allam, M. H. Anis, and M. I. Elmasry, High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des., 2000, pp. 145160. [5] V. Kursun and E. G. Friedman, Node voltage dependent subthreshold leakage current characteristics of dynamic circuits, in Proc. IEEE/ACM Int. Symp. Quality Electron. Des., 2004, pp. 104109. [6] V. Kursun and E. G. Friedman, Domino logic with variable threshold voltage keeper, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 10801093, Dec. 2003. [7] International technology roadmap for semiconductors, 2001. [Online]. Available: http:www//public.itrs.net [8] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors, in Proc. IEEE Int. Symp. VLSI Technol., 2000, pp. 174175. [9] H. Sasaki, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, 1.5 nm direct-tunneling gate oxide Si MOSFETs, IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 12331242, Aug. 1996. [10] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, Boosted Gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free gigascale integration, in Proc. IEEE Int. Custom Integr. Circuits Conf., 2000, pp. 409412. [11] F. Hamzaoglu and M. R. Stan, Circuit level techniques to control gate leakage for sub-100 nm CMOS, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des., 2002, pp. 6063. [12] W.-C. Lee and C. Hu, Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling, in Proc. IEEE Int. Symp. VLSI Technol., 2000, pp. 198199.

[13] Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric, IEEE Electron Device Lett., vol. 21, no. 11, pp. 540542, Nov. 2000. [14] Berkeley predictive technology model (BPTM), Univ. California, Berkeley, 2007. [Online]. Available: http://www.device.eecs.berkeley.edu/~ptm/download.html [15] V. Kursun and E. G. Friedman, Sleep switch dual threshold voltage domino logic with reduced standby leakage current, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 485496, May 2004. [16] S. Heo and K. Asanovic, Leakage-biased dynamic ne-grain leakage reduction, in Proc. IEEE Int. Symp. VLSI Circuits, 2002, pp. 316319. [17] G. Yang, Z. Wang, and S. Kang, Leakage-proof domino circuit design for deep sub-100 nm technologies, in Proc. IEEE Int. Conf. VLSI Des., 2004, pp. 222227. [18] Z. Liu and V. Kursun, Temperature dependent leakage power characteristics of dynamic circuits in sub-65 nm CMOS technologies, in Proc. IEEE Int. Midw. Symp. Circuits Syst., 2005, pp. 551554. [19] Z. Liu and V. Kursun, Leakage power characteristics of dynamic circuits in nanometer CMOS technologies, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 692696, Aug. 2006. [20] Z. Liu and V. Kursun, Leakage biased pMOS sleep switch dynamic circuits, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 10931097, Oct. 2006. [21] MOSIS, Marina del Rey, CA, The MOSIS service, (2007). [Online]. Available: http://www.mosis.org/Technical/Designrules/scmos/scmos-main.htm [22] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design. Hoboken, NJ: Wiley, 2006. Zhiyu Liu (S05) received the B.S. and M.S. degrees in engineering physics from Tsinghua University, Beijing, China, in 2000. He is currently pursuing the Ph.D. degree in electrical and computer engineering from the University of Wisconsin-Madison, Madison, under the supervision of Prof. Kursun. His research interests include low-power and highperformance integrated circuit design and emerging CMOS technologies.

Volkan Kursun (S01M04) received the B.S. degree in electrical and electronics engineering from the Middle East Technical University, Ankara, Turkey, in 1999, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Rochester, Rochester, NY, in 2001 and 2004, respectively. In 2004, he became an Assistant Professor with the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison. In 2000, he was with Xerox Corporation, Webster, NY, where he performed research on mixed-signal thermal inkjet integrated circuits. During the summers of 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro, OR, where he was responsible for the modeling and design of high frequency monolithic power supplies. His current research interests include low-voltage, low-power, and high-performance integrated circuit design, modeling of semiconductor devices, and emerging integrated circuit technologies. He has more than 60 publications and four issued and three pending patents in the areas of high-performance integrated circuits and emerging semiconductor technologies. He is the author of the book Multi-Voltage CMOS Circuit Design (Wiley, 2006). Dr. Kursun is a member of the technical program and organizing committees of a number of IEEE and ACM conferences and serves on the editorial boards of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, and the Journal of Circuits, Systems, and Computers.