Efficient VLSI Architecture for Discrete Wavelet Transform

AIM: The main aim of the project is to design and implement Efficient VLSI Architecture for Discrete Wavelet Transform. ABST A!T: This paper proposes an efficient architecture for 2D DWT. The proposed architecture includes a transform module, a RAM module and a multiplexer. In transform module, poly phase decomposition and coefficient folding techni ue is applied to the decimation filters of stages ! and 2 respecti"ely. The ad"antages of the proposed architecture are the !##$ hard%are utili&ation, fast computing time, regular data flo% and lo% complexity. 'ecause of the regular structure, the proposed architecture can (e easily (e scaled %ith the filter length and 2D DWT le"el. )*+I architecture for the 2,D DWT is implemented using -./A using )erilog 0D*. BL"!# DIA$ AM:

V.Mallikarjuna (Project manager)

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Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

-ig1 'loc2 diagram of the proposed %or2

T""LS: 3ilinx 4.2I+5, Modelsim 6.7c. A%%LI!ATI"& ADVA&TA$ES: The ad"antages of the proposed architecture are !##$ hard%are utili&ation, fast computing time, regular data flo%, lo% control complexity. These ad"antages ma2e the design suita(le for image compression systems in 8.5/,2###. The future %or2 includes implementation of efficient architecture for DWT using *ifting schemes. E'E E&!ES: 9ha2ra(arti, 9. and Mumford, 9. !446. :5fficient reali&ations of analysis and +ynthesis filters (ased on the 2D, Discrete %a"elet transform in .roc. I555 I9A++., pp. ;2<6,;2<<.
V.Mallikarjuna (Project manager)

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Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

 9ha2ra(arti, 9. and )ish%anath, M. !446. :Architectures for %a"elet transforms1A sur"ey=,)*+I signal processing, )ol. !7, pp.!>!,!42, 9hristopoulos, 9., As2elof, 8. and *arsson, M. 2###. :5fficient Methods for 5ncoding Regions of Interest in the upcoming 8.5/ 2### still image 9oding standard=, I555 signal processing letter, pp.27>,274. /a( 9heon 8ung, Du2 ?oung 8in, and +eong Mo .ar2, 2##7. :An 5fficient *ine (ased )*+I Architecture for 2D *ifting DWT=. .arhi, @.@. and Aishitani, T. !44;. :)*+I architectures for discrete %a"elet Transforms=, I555 trans. )*+I sys, )ol. !, pp. !4!,2#2.

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &