8085 Interrupts

Diwakar Yagyasen , AP,
CSE, BBDNITM
EEC-406 : INTRODCTION TO MICROPROCESSOR
Chapter 12
8085 Interrupts
1
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Interrupts
Interrupt is a process where an external device
can get the attention of the microprocessor.
The process starts from the I/ device
The process is as!nchronous.

Classification of Interrupts
Interrupts can "e classified into two t!pes#
$as%a"le Interrupts &Can "e dela!ed or 'e(ected)
*on+$as%a"le Interrupts &Can not "e dela!ed or

'e(ected)
Interrupts can also "e classified into#
,ectored &the address of the service routine is hard+wired)
*on+vectored &the address of the service routine needs to

"e supplied externall! "! the device)
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Interrupts
.n interrupt is considered to "e an emergenc!
signal that ma! "e serviced.
The $icroprocessor ma! respond to it as soon as

possi"le.
/hat happens when $0 is interrupted 1
/hen the $icroprocessor receives an interrupt

signal2 it suspends the currentl! executing
program and (umps to an Interrupt 3ervice 'outine
&I3') to respond to the incoming interrupt.
4ach interrupt will most pro"a"l! have its own

I3'.
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'esponding to Interrupts
'esponding to an interrupt ma! "e immediate or
dela!ed depending on whether the interrupt is
mas%a"le or non+mas%a"le and whether
interrupts are "eing mas%ed or not.
There are two wa!s of redirecting the execution
to the I3' depending on whether the interrupt is
vectored or non+vectored.
,ectored# The address of the su"routine is alread!

%nown to the $icroprocessor
*on ,ectored# The device will have to suppl! the

address of the su"routine to the $icroprocessor
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The 8085 Interrupts
/hen a device interrupts2 it actuall! wants the
$0 to give a service which is e6uivalent to
as%ing the $0 to call a su"routine. This
su"routine is called I3' &Interrupt 3ervice
'outine)
The 74I8 instruction is a one "!te instruction and
is used to 4na"le the non+mas%a"le interrupts.
The 79I8 instruction is a one "!te instruction and
is used to 9isa"le the non+mas%a"le interrupts.
The 8085 has a single *on+$as%a"le interrupt.
The non+mas%a"le interrupt is not affected "! the

value of the Interrupt 4na"le flip flop.
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The 8085 Interrupts
The 8085 has 5 interrupt inputs.
The I*T' input.
The I*T' input is the onl! non+vectored interrupt.
I*T' is mas%a"le using the 4I/9I instruction pair.
'3T 5.52 '3T :.52 '3T ;.5 are all automaticall!

vectored.
'3T 5.52 '3T :.52 and '3T ;.5 are all mas%a"le.
T'.0 is the onl! non+mas%a"le interrupt in the

8085
T'.0 is also automaticall! vectored

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The 8085 Interrupts
Interrupt name $as%a"le ,ectored
I*T' <es *o
'3T 5.5 <es <es
'3T :.5 <es <es
'3T ;.5 <es <es
T'.0 *o <es
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8085 Interrupts
8085
T'.0
'3T;.5
'3T:.5
'3T 5.5
I*T'
I*T.
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Interrupt ,ectors and the ,ector Ta"le
.n interrupt vector is a pointer to where the I3'
is stored in memor!.
.ll interrupts &vectored or otherwise) are mapped
onto a memor! area called the Interrupt ,ector
Ta"le &I,T).
The I,T is usuall! located in memor! page 00

&0000> + 00??>).
The purpose of the I,T is to hold the vectors that

redirect the microprocessor to the right place when
an interrupt arrives.
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4xample# @et 2 a device interrupts the
$icroprocessor using the '3T ;.5 interrupt line.
Aecause the '3T ;.5 interrupt is vectored2

$icroprocessor %nows 2 in which memor! location
it has to go using a call instruction to get the I3'
address. '3T;.5 is %nows as Call 00-Ch to
$icroprocessor. $icroprocessor goes to 00-C
location and will get a B$0 instruction to the actual
I3' address. The $icroprocessor will then2 (ump
to the I3' location
The process is illustrated in the next slide..

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1. The interrupt process should "e ena"led using the 4I
instruction.
2. The 8085 chec%s for an interrupt during the execution of
ever! instruction.
-. If I*T' is high2 $0 completes current instruction2 disa"les
the interrupt and sends I*T. &Interrupt ac%nowledge) signal
to the device that interrupted
5. I*T. allows the I/ device to send a '3T instruction
through data "us.
5. Cpon receiving the I*T. signal2 $0 saves the memor!
location of the next instruction on the stac% and the program
is transferred to 7call8 location &I3' Call) specified "! the
'3T instruction
The 8085 *on+,ectored Interrupt 0rocess
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:. $icroprocessor 0erforms the I3'.
;. I3' must include the 74I8 instruction to ena"le the
further interrupt within the program.
8. '4T instruction at the end of the I3' allows the
$0 to retrieve the return address from the stac%
and the program is transferred "ac% to where the
program was interrupted.
DD 3ee the example of the Class that showed how
interrupt process wor%s for this 8 steps DD
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The 8085 recogniEes 8 '43T.'T instructions#
'3T0 + '3T;.
each of these would send the execution to a

predetermined hard+wired memor! location#
Restart
Instruction
Equivalent
to
'3T0 C.@@ 0000>
'3T1 C.@@ 0008>
'3T2 C.@@ 0010>
'3T- C.@@ 0018>
'3T5 C.@@ 0020>
'3T5 C.@@ 0028>
'3T: C.@@ 00-0>
'3T; C.@@ 00-8>
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'estart 3e6uence
The restart se6uence is made up of three
machine c!cles
In the 1st machine c!cle#
The microprocessor sends the I*T. signal.
/hile I*T. is active the microprocessor reads the data

lines expecting to receive2 from the interrupting device2
the opcode for the specific '3T instruction.
In the 2nd and -rd machine c!cles#
the 1:+"it address of the next instruction is saved on the

stac%.
Then the microprocessor (umps to the address

associated with the specified '3T instruction.
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Timing 9iagram of 'estart 3e6uence
3ee the 0age -802 ?igure 12.22 of !our Text
Aoo% for the Timing 9iagram of the '3T
instruction
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>ardware Feneration of '3T pcode
>ow does the external device produce the
opcode for the appropriate '3T instruction1
The opcode is simpl! a collection of "its.
3o2 the device needs to set the "its of the data "us
to the appropriate value in response to an I*T.
signal.
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The following is an example of
generating '3T 5#
'3T 58s opcode is 4? G
9 9
;:55-210
11101111
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9uring the interrupt ac%nowledge machine c!cle2
&the 1st machine c!cle of the '3T operation)#
The $icroprocessor activates the I*T. signal.
This signal will ena"le the Tri+state "uffers2 which

will place the value 4?> on the data "us.
Therefore2 sending the $icroprocessor the '3T 5

instruction.
The '3T 5 instruction is exactl! e6uivalent to
C.@@ 0028>
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Issues in Implementing I*T' Interrupts
>ow long must I*T' remain high1
The microprocessor chec%s the I*T' line one cloc% c!cle

"efore the last T+state of each instruction.
The I*T' must remain active long enough to allow for the
longest instruction.
The longest instruction for the 8085 is the conditional C.@@

instruction which re6uires 18 T+states.
Therefore2 the I*T' must remain active for 1;.5 T+
states.
If fG -$>H then TG1/f and so2 I*T' must remain active
for I &1/-$>H) D 1;.5 J 5.8 micro secondsK.
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>ow long can the I*T' remain high1
The I*T' line must "e deactivated "efore the 4I is

executed. therwise2 the microprocessor will "e
interrupted again.
nce the microprocessor starts to respond to an

I*T' interrupt2 I*T. "ecomes active &G0).
Therefore2 I*T' should "e turned off as soon as
the I*T. signal is received.
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Can the microprocessor "e interrupted again
"efore the completion of the I3'1
.s soon as the 1st interrupt arrives2 all mas%a"le

interrupts are disa"led.
The! will onl! "e ena"led after the execution of

the 4I instruction.
Therefore2 the answer is# Lonl! if we allow it toM.
If the 4I instruction is placed earl! in the I3'2 other
interrupt ma! occur "efore the I3' is done.
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$ultiple Interrupts N 0riorities
>ow do we allow multiple devices to interrupt
using the I*T' line1
The microprocessor can onl! respond to one

signal on I*T' at a time.
Therefore2 we must allow the signal from onl! one

of the devices to reach the microprocessor.
/e must assign some priorit! to the different

devices and allow their signals to reach the
microprocessor according to the priorit!.
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The 0riorit! 4ncoder
The solution is to use a circuit called the priorit!
encoder &;5@3158).
This circuit has 8 inputs and - outputs.
The inputs are assigned increasing priorities

according to the increasing index of the input.
Input ; has highest priorit! and input 0 has the lowest.
The - outputs carr! the index of the highest

priorit! active input.
?igure 12.5 in the "oo% shows how this circuit can

"e used with a Tri+state "uffer to implement an
interrupt priorit! scheme.
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$ultiple Interrupts N 0riorities
*ote that the opcodes for the different '3T
instructions follow a set pattern.
Ait 952 95 and 9- of the opcodes change in a "inar!

se6uence from '3T ; down to '3T 0.
The other "its are alwa!s 1.
This allows the code generated "! the ;5-:: to "e used
directl! to choose the appropriate '3T instruction.
The one draw "ac% to this scheme is that the
onl! wa! to change the priorit! of the devices
connected to the ;5-:: is to reconnect the
hardware.
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$ultiple Interrupts and 0riorit!
3ee the Text Aoo%2 0age -85+-85 for the
detailed explanation of the $ultiple
interrupt process
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The 8085 $as%a"le/,ectored Interrupts
The 8085 has 5 $as%ed/,ectored interrupt
inputs.
'3T 5.52 '3T :.52 '3T ;.5
The! are all mas%a"le.
The! are automaticall! vectored according to the

following ta"le#
The vectors for these interrupt fall in "etween the vectors

for the '3T instructions. That8s wh! the! have names li%e
'3T 5.5 &'3T 5 and a half).
Interrupt Vector
'3T 5.5 002C>
'3T :.5 00-5>
'3T ;.5 00-C>
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$as%ing '3T 5.52 '3T :.5 and '3T ;.5
These three interrupts are mas%ed at two levels#
Through the Interrupt 4na"le flip flop and the 4I/9I

instructions.
The Interrupt 4na"le flip flop controls the whole

mas%a"le interrupt process.
Through individual mas% flip flops that control the

availa"ilit! of the individual interrupts.
These flip flops control the interrupts individuall!.

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$as%a"le Interrupts and vector locations
Interrupt
4na"le
?lip ?lop
I*T'
'3T 5.5
'3T :.5
'3T ;.5
$ 5.5
$ :.5
$ ;.5
'3T;.5 $emor!
** See Fig 12.5 of the
Text oo! for a
"etaile" loo!
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The 8085 $as%a"le/,ectored Interrupt 0rocess
1. The interrupt process should "e ena"led using the
4I instruction.
2. The 8085 chec%s for an interrupt during the
execution of ever! instruction.
-. If there is an interrupt2 and if the interrupt is
ena"led using the interrupt mas%2 the
microprocessor will complete the executing
instruction2 and reset the interrupt flip flop.
5. The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector ta"le.
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The 8085 $as%a"le/,ectored Interrupt 0rocess
5. /hen the microprocessor executes the call
instruction2 it saves the address of the next
instruction on the stac%.
:. The microprocessor (umps to the specific service
routine.
;. The service routine must include the instruction 4I
to re+ena"le the interrupt process.
8. .t the end of the service routine2 the '4T
instruction returns the execution to where the
program was interrupted.
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$anipulating the $as%s
The Interrupt 4na"le flip flop is manipulated
using the 4I/9I instructions.
The individual mas%s for '3T 5.52 '3T :.5 and
'3T ;.5 are manipulated using the 3I$
instruction.
This instruction ta%es the "it pattern in the

.ccumulator and applies it to the interrupt mas%
ena"ling and disa"ling the specific interrupts.
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>ow 3I$ Interprets the .ccumulator
3
9
3
9
4
O
O
O
'
;
.
5
$
3
4
$
;
.
5
$
:
.
5
$
5
.
5
0 1 2 - 5 5 : ;
'3T5.5 $as%
'3T:.5 $as%
'3T;.5 $as%
P
0 + .vaila"le
1 + $as%ed
$as% 3et 4na"le
0 + Ignore "its 0+2
1 + 3et the mas%s according
to "its 0+2
?orce '3T;.5 ?lip ?lop to reset
*ot Csed
4na"le 3erial 9ata
0 + Ignore "it ;
1 + 3end "it ; to 39 pin
3erial 9ata ut
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3I$ and the Interrupt $as%
Ait 0 is the mas% for '3T 5.52 "it 1 is the mas% for '3T :.5
and "it 2 is the mas% for '3T ;.5.
If the mas% "it is 02 the interrupt is availa"le.
If the mas% "it is 12 the interrupt is mas%ed.

Ait - &$as% 3et 4na"le + $34) is an ena"le for setting the
mas%.
If it is set to 0 the mas% is ignored and the old settings remain.
If it is set to 12 the new setting are applied.
The 3I$ instruction is used for multiple purposes and not onl!
for setting interrupt mas%s.
It is also used to control functionalit! such as 3erial 9ata

Transmission.
Therefore2 "it - is necessar! to tell the microprocessor whether or

not the interrupt mas%s should "e modified
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3I$ and the Interrupt $as%
The '3T ;.5 interrupt is the onl! 8085 interrupt that has
memor!.
If a signal on '3T;.5 arrives while it is mas%ed2 a flip flop

will remem"er the signal.
/hen '3T;.5 is unmas%ed2 the microprocessor will "e

interrupted even if the device has removed the interrupt
signal.
This flip flop will "e automaticall! reset when the

microprocessor responds to an '3T ;.5 interrupt.
Ait 5 of the accumulator in the 3I$ instruction allows
explicitl! resetting the '3T ;.5 memor! even if the
microprocessor did not respond to it.
Ait 5 is not used "! the 3I$ instruction
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Csing the 3I$ Instruction to $odif! the Interrupt $as%s
4xample# 3et the interrupt mas%s so that '3T5.5
is ena"led2 '3T:.5 is mas%ed2 and '3T;.5 is
ena"led.
?irst2 determine the contents of the accumulator

3
9
3
9
4
O
O
O
'
;
.
5
$
3
4
$
;
.
5
$
:
.
5
$
5
.
5
+ 4na"le 5.5 "it 0 G 0
+ 9isa"le :.5 "it 1 G 1
+ 4na"le ;.5 "it 2 G 0
+ .llow setting the mas%s "it - G 1
+ 9on8t reset the flip flop "it 5 G 0
+ Ait 5 is not used "it 5 G 0
+ 9on8t use serial data "it : G 0
+ 3erial data is ignored "it ; G 0
0 1 0 0 0 0 0 1
Contents of accumulator are# 0.>
4I Q 4na"le interrupts including I*T'
$,I .2 0. Q 0repare the mas% to ena"le '3T ;.52 and 5.52 disa"le :.5
3I$ Q .ppl! the settings '3T mas%s
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Triggering @evels
'3T ;.5 is positive edge sensitive.
/hen a positive edge appears on the '3T;.5 line2 a

logic 1 is stored in the flip+flop as a LpendingM interrupt.
3ince the value has "een stored in the flip flop2 the line
does not have to "e high when the microprocessor
chec%s for the interrupt to "e recogniEed.
The line must go to Eero and "ac% to one "efore a new

interrupt is recogniEed.
'3T :.5 and '3T 5.5 are level sensitive.
The interrupting signal must remain present until the

microprocessor chec%s for interrupts.
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9etermining the Current $as% 3ettings
'I$ instruction# 'ead Interrupt $as%
@oad the accumulator with an 8+"it pattern

showing the status of each interrupt pin and mas%.
Interrupt 4na"le
?lip ?lop
'3T 5.5
'3T :.5
'3T ;.5
$ 5.5
$ :.5
$ ;.5
'3T;.5 $emor!
3
9
I
0
;
.
5
0
:
.
5
0
5
.
5
I
4
$
;
.
5
$
:
.
5
$
5
.
5
0 1 2 - 5 5 : ;
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>ow 'I$ sets the .ccumulator8s different "its
3
9
I
0
;
.
5
0
:
.
5
0
5
.
5
I
4
$
;
.
5
$
:
.
5
$
5
.
5
0 1 2 - 5 5 : ;
'3T5.5 $as%
'3T:.5 $as%
'3T;.5 $as%
P
0 + .vaila"le
1 + $as%ed
Interrupt 4na"le
,alue of the Interrupt 4na"le
?lip ?lop
3erial 9ata In
'3T5.5 Interrupt 0ending
'3T:.5 Interrupt 0ending
'3T;.5 Interrupt 0ending
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The 'I$ Instruction and the $as%s
Aits 0+2 show the current setting of the mas% for
each of '3T ;.52 '3T :.5 and '3T 5.5
The! return the contents of the three mas% flip flops.
The! can "e used "! a program to read the mas%

settings in order to modif! onl! the right mas%.
Ait - shows whether the mas%a"le interrupt
process is ena"led or not.
It returns the contents of the Interrupt 4na"le ?lip ?lop.
It can "e used "! a program to determine whether or not

interrupts are ena"led.
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The 'I$ Instruction and the $as%s
Aits 5+: show whether or not there are pending
interrupts on '3T ;.52 '3T :.52 and '3T 5.5
Aits 5 and 5 return the current value of the '3T5.5 and

'3T:.5 pins.
Ait : returns the current value of the '3T;.5 memor! flip

flop.
Ait ; is used for 3erial 9ata Input.
The 'I$ instruction reads the value of the 3I9 pin on the
microprocessor and returns it in this "it.
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0ending Interrupts
3ince the 8085 has five interrupt lines2 interrupts
ma! occur during an I3' and remain pending.
Csing the 'I$ instruction2 it is possi"le to can read

the status of the interrupt lines and find if there are
an! pending interrupts.
3ee the example of the class

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T'.0
T'.0 is the onl! non+mas%a"le interrupt.
It does not need to "e ena"led "ecause it cannot

"e disa"led.
It has the highest priorit! amongst interrupts.
It is edge and level sensitive.
It needs to "e high and sta! high to "e recogniEed.
nce it is recogniEed2 it won8t "e recogniEed again

until it goes low2 then high again.
T'.0 is usuall! used for power failure and
emergenc! shutoff.
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The 8085 Interrupts
Interrupt
*ame
$as%a"le
$as%ing
$ethod
,ectored $emor!
Triggering
$ethod
I*T' <es 9I / 4I *o *o
@evel
3ensitive
'3T 5.5 /
'3T :.5
<es
9I / 4I
3I$
<es *o
@evel
3ensitive
'3T ;.5 <es
9I / 4I
3I$
<es <es
4dge
3ensitive
T'.0 *o *one <es *o
@evel N
4dge
3ensitive

8085 Interrupts

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8085 Interrupts

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Diwakar Yagyasen , AP,

The process starts from the I/ device

The process is as!nchronous.

Interrupts can "e classified into two t!pes#

$as%a"le Interrupts &Can "e dela!ed or 'e(ected)

*on+$as%a"le Interrupts &Can not "e dela!ed or

,ectored &the address of the service routine is hard+wired)

*on+vectored &the address of the service routine needs to

The $icroprocessor ma! respond to it as soon as

/hen the $icroprocessor receives an interrupt

4ach interrupt will most pro"a"l! have its own

,ectored# The address of the su"routine is alread!

*on ,ectored# The device will have to suppl! the

The non+mas%a"le interrupt is not affected "! the

The I*T' input.

The I*T' input is the onl! non+vectored interrupt.

I*T' is mas%a"le using the 4I/9I instruction pair.

'3T 5.52 '3T :.52 '3T ;.5 are all automaticall!

T'.0 is the onl! non+mas%a"le interrupt in the

T'.0 is also automaticall! vectored

The I,T is usuall! located in memor! page 00

The purpose of the I,T is to hold the vectors that

Aecause the '3T ;.5 interrupt is vectored2

The process is illustrated in the next slide..

each of these would send the execution to a

In the 1st machine c!cle#

The microprocessor sends the I*T. signal.

/hile I*T. is active the microprocessor reads the data

In the 2nd and -rd machine c!cles#

the 1:+"it address of the next instruction is saved on the

Then the microprocessor (umps to the address

The opcode is simpl! a collection of "its.

The $icroprocessor activates the I*T. signal.

This signal will ena"le the Tri+state "uffers2 which

Therefore2 sending the $icroprocessor the '3T 5

The microprocessor chec%s the I*T' line one cloc% c!cle

The longest instruction for the 8085 is the conditional C.@@

The I*T' line must "e deactivated "efore the 4I is

nce the microprocessor starts to respond to an

.s soon as the 1st interrupt arrives2 all mas%a"le

The! will onl! "e ena"led after the execution of

The microprocessor can onl! respond to one

Therefore2 we must allow the signal from onl! one

/e must assign some priorit! to the different

This circuit has 8 inputs and - outputs.

The inputs are assigned increasing priorities

Input ; has highest priorit! and input 0 has the lowest.

The - outputs carr! the index of the highest

?igure 12.5 in the "oo% shows how this circuit can

Ait 952 95 and 9- of the opcodes change in a "inar!

The other "its are alwa!s 1.

'3T 5.52 '3T :.52 '3T ;.5

The! are all mas%a"le.

The! are automaticall! vectored according to the

The vectors for these interrupt fall in "etween the vectors

Through the Interrupt 4na"le flip flop and the 4I/9I

The Interrupt 4na"le flip flop controls the whole

Through individual mas% flip flops that control the

These flip flops control the interrupts individuall!.

This instruction ta%es the "it pattern in the

If the mas% "it is 02 the interrupt is availa"le.

If the mas% "it is 12 the interrupt is mas%ed.

If it is set to 0 the mas% is ignored and the old settings remain.

If it is set to 12 the new setting are applied.