DESIGN AND SIMULATION OF 8 BIT MICROPROCESSOR USING VHDL

This project deals with the design and simulation of 8 bit microprocessor using VHDL for general computation purpose. The top level architecture iSs modeled with five components !L"# $!%# &' &rogram 'ounter(# )$ )nstruction Decoder $egister(. T)% Timing and 'ontrol "nit(. The &' has the address of instruction. !fter the instruction fetching# the )$ decodes the instruction as opcode and data. Depending upon the opcode the T)% unit generate the control signals. The corresponding operation is performed in !L" and $!% as per the instruction. The functionalit* of the processor is tested with various programs and simulations. The hardware e+uivalent code for microprocessor is developed in VHDL. The simulation is performed in the ,D! ,lectronic Design !utomation( Tool !ctive VHDL.

PC Load-pc
Sbus-pc0

Sbus-alu-0 Sbus-RAMProg $

PC-bus

Inc-pc

$ Load-mdr Load-mar CS r-nw $

RAM
Load-Ir

IR

Sbus-pcO $ OP $

TIM
Load-Acc ALU-acc ALU-add ALU-sub ALU-and ALU-or Zflag Cloc R!s! HLT Zflag

ACC
Sbus-ir-0

ALU

Sbus-alu-0

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