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BVM01. VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System
BVM01. VLSI Implementation of Fast Addition Using Quaternary Signed Digit Number System
TECH LIST
BVM01. VLSI implementation of Fast Addition using Quaternary Signed Digit Number System 2013 BVM02. Dramatically Low-Transistor- ount !ig"-Speed Ternary Adders 2013 BVM03. !ig" #erformance and #ower $fficient %&-bit
arry Select Adder using !ybrid #TL' ()S Logic Style 2013
BVM04. A #arallel (ultiplier - Accumulator *ased )n +adi, - . (odified *oot" Algorit"ms by /sing Spurious #ower
Suppression Tec"ni0ue2013
BVM05. Transistor Le1el Design And Analysis )f Vedic Algorit"m *ased Low #ower (A - 2013 BVM06. !ig" speed (odified *oot" $ncoder multiplier for signed and unsigned numbers2 2 BVM07. Design and Implementation of /A+T Design wit" *IST BVM08. Design and Implementation of #S&
2013
apability2 2013
ontroller 2013
BVM09. Design and implementation of two 1ariable multiplier using 3 ( and Vedic mat"ematics 2013 BVM010. A new Approac" to implement #arallel #refi, adder in F#4A BVM011. An efficient implementation of floating point multiplier 2013 BVM012. Design 5 Implementation )f %&-*it +isc 6(I#S7 #rocessor 2013 BVM013. A #ico *la8e-*ased $mbedded System for (onitoring Applications 2013 BVM014. Design and Implementation of *#S3 BVM015.
ommunication (odulation2013
BVM016. Design and Implementation of Vedic (ultipliers 2013 BVM017. Design of FI+ Filter on F#4As using I# cores2013 BVM018. !ig" Speed ASI
BVM019. Design of low power T#4 using L#-LFS+ 2012 BVM020. Design of low power "ig" speed 1lsi adder sub system 2012 BVM021. A "ybrid low power adder for "ig"-performance processor 2012 BVM022. A 1ery fast and low power carry select adder circuit 2012 BVM023. Nonlinear (ulti-$rror
BVM026. F#4A implementation of binary coded Decimal digit adders and multipliers 2012 BVM027. )n (odulo &n ; < = Adder Design- 2012 BVM028. $fficient Implementation )f =>-*it (ultiplier-Accumulator /sing +adi, (odified *oot" Algorit"m And Spst Adder
bus ommunication
BVM033. A !ig" Speed :allace Tree (ultiplier /sing (odified *oot" Algorit"m for Fast Arit"metic BVM034. A Fast !ybrid
BVM035. Design and Implementation of an $ig"t *it (ultiplier /sing Twin #recision Tec"ni0ue and *aug"-:oolley
Algorit"m- 2012
BVM036. A New Arc"itecture for Signed +adi,-&N #ure Array (ultipliers2012 BVM037. !ig" Speed Truncation- $rror -Tolerant Adder 2012 BVM038. Implementation of AT$ for digital integrated circuits 2012 BVM039. Design and Implementation of INI/A+T BVM040. Design and Implementation of /A+T BVM041. Design and Implementation of I&
ontroller2 2012
ontroller2012
ontroller2012
BVM042. Design and Implementation of +eed Solomon $ncoder 2012 BVM043. F#4A Implementation of
BVM044. Design and Implementation of Double #recision F#/ #rocessor 2012 BVM045. Design and Implementation of F(A >. bit for SI(D processors 2012 BVM046. Design and Implementation of !uffman encoder for @#$4
ompression 2012
BVM047. VLSI Implementation of Data $ncryption Standard Algorit"m 2012 BVM048. Design and Implementation of S#I
BVM050. An
of
Dynamically
+econfigurable
3-Nearest
Neig"bour
BVM051. Implementation of #ipelined &D-D T and Quanti8ation Arc"itecture for @#$4 Image BVM052. F#4A #rototyping of !ardware Implementation of BVM053. Impro1ement of t"e )rt"ogonal
ompression 2012
ode on1olution
BVM054. A!* Interface :it" S#I (aster *y /sing Verilog2012 BVM055. Design of low power column bypass multiplier using F#4A- 2011 BVM056. Low #ower (A BVM057. Single
BVM058. A New +e1ersible Design of * D Adder- 2011 BVM059. Low #ower Design Tec"ni0ues Applied to #ipelined #arallel and Iterati1e BVM060. Design and Implementation of A$S Algorit"m2011 BVM061. Design and Implementation of SD +A(2011 BVM062. Design of Discrete
)+DI Design-2011
BVM063. Fast Di1ision Algorit"m wit" a small Loo? /p table2011 BVM064. Design and VLSI Implementation of DD+ SD+A(
BVM065. V!DL Design and F#4A Implementation of :eig"ted (a9ority Logic Decoders 2010 BVM066. Design
and
Implementation
of
multi
serial
S)
for
Aero
space
communication
2010
BVM067. F#4A-based for Implementation of (ulti-Serials to $t"ernet 4ateway 2010 BVM068. Design and Implementation of *egerAs $ncoder and Decoder 2010 BVM069. Implementation )f
"aotic ellular Automaton wit" *inary Sync"roni8ation #roperty 2010 on1erter For Flow (easurement 2010
BVM070. Fpga-*ased Smart Sensor Implementation :it" #recise Fre0uency to Digital BVM071. A !ig" T"roug"put A(*A A!* #rotocol 2010 BVM072. Low
omple,ity digit Serial (ontgomery (ultipliers for special class of 4F6n7 2010
BVM073. Implementation of a Self-(oti1ated Arbitration Sc"eme for t"e (ultilaye A!* *us matri, 2010 BVM074.
BVM076. Implementation (odular $,ponentiation /sing Sliding :indow (et"od 2007 BVM077. Design and Implementation of single precision F#/ #rocessor 2006 BVM078. Design and Implementation of F(A %& bit for SI(D processors 2006 BVM079. $fficient Iterati1e Tec"ni0ues for Soft Decision Decoding of +eed-Solomon BVM080. Design and Implementation of BVM081. T"e
odes 2005
AN ontroller 2005
BVM082. (easurement and $1aluation of #ower Analysis Attac?s on Async"ronous S-*o, BVM083. Tec"ni0ue of LFS+ *ased Test 4enerator Synt"esis for Deterministic and #seudorandom BVM084. $fficient *uilt-in Self-+epair Strategy for $mbedded S+A( wit" Selectable +edundancy BVM085. Design and Implementation of !amming code algorit"m for S) BVM086. De1elopment of # I bus arbiter multi processor en1ironment BVM087. Design and Implement of FFT #rocessor for )FD(A System /sing F#4A BVM088. +eal Time Simulation of a F#4A *ased Space Vector #:( BVM089. V"dl Simulation of #ea? DetectorB >.-*it * D
Testing2
bus ommunication
F#4A
BVM090. Design and Implementation of Viterbi Algorit"m BVM091.
BVM094. CDE= (icro controller Synt"esi8able model and implementation on F#4A BVM095. De1elopment of intellectual property for local interconnect networ? for automobile sensor interface application BVM096. Design and implementation of Finite impulse response filters BVM097. De1elopment of !uffman encoder for (#$4-&1ideo encoding applications BVM098. De1elopment of Video display processor on F#4A BVM099. Design and analysis of low density parity c"ec? encoder for fi,ed mobile communication systems BVM0100. BVM0101. BVM0102.
Design analysis of =-4I4A*IT $t"ernet (edia acess controller64$(A 7 ore for Full-duple, operations Design of turbo con1olutional ode decoder for %4## :ireless mobile communication systems
Design and implementation of ort"ogonal fre0uency di1ision multiple access modem on F#4A
BVM0103. BVM0104. BVM0105. BVM0106. BVM0107. BVM0108. BVM0109. BVM0110. BVM0111. BVM0112. BVM0113. BVM0114.
De1elopment of 3eyboard controller for single board computer based on F#4A F#4A Implementation of an Ad1anced Traffic Lig"t ontroller using Verilog !DL A(*A */S *AS$D A#* -I& #rotocol A!* - (aster to Sla1e onfiguration VLSI arc"itecture of elimination undesirable cross tal? Dual (et"odology "ig" performance (ultiplier !ig" T"roug"put D T /sing #arallel processing and pipelining Design of =>- *it +IS processor A +obust and $fficient met"od for $rror Detection and orrection in (emories *us $ncoder For rosstal? A1oidance In +L (odeled Interconnects Design and Implementation of (A unit $fficient Iterati1e Tec"ni0ues for Soft Decision Decoding