Encoder - Using if-else Statement

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//----------------------------------------------------// Design Name : encoder_using_if

// File Name : encoder_using_if.v
// Function
: Encoder using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
// Enable for the encoder
);
//-----------Output Ports--------------output [3:0] binary_out ;
//-----------Input Ports--------------input enable ;
input [15:0] encoder_in ;
//------------Internal Variables-------reg [3:0] binary_out ;
//-------------Code Start----------------always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end

58 endmodule
You could download file encoder_using_if.v here
Encoder - Using case Statement
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//----------------------------------------------------// Design Name : encoder_using_case

// File Name : encoder_using_case.v
// Function
: Encoder using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable
// Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end
endmodule

Priority Encoders

Pri-Encoder - Using if-else Statement

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//----------------------------------------------------// Design Name : pri_encoder_using_if

// File Name : pri_encoder_using_if.v
// Function
: Pri Encoder using If

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// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_if (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
// Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in[0] == 1) begin
binary_out = 1;
end else if (encoder_in[1] == 1) begin
binary_out = 2;
end else if (encoder_in[2] == 1) begin
binary_out = 3;
end else if (encoder_in[3] == 1) begin
binary_out = 4;
end else if (encoder_in[4] == 1) begin
binary_out = 5;
end else if (encoder_in[5] == 1) begin
binary_out = 6;
end else if (encoder_in[6] == 1) begin
binary_out = 7;
end else if (encoder_in[7] == 1) begin
binary_out = 8;
end else if (encoder_in[8] == 1) begin
binary_out = 9;
end else if (encoder_in[9] == 1) begin
binary_out = 10;
end else if (encoder_in[10] == 1) begin
binary_out = 11;
end else if (encoder_in[11] == 1) begin
binary_out = 12;
end else if (encoder_in[12] == 1) begin
binary_out = 13;
end else if (encoder_in[13] == 1) begin
binary_out = 14;
end else if (encoder_in[14] == 1) begin
binary_out = 15;
end
end
end
endmodule
could download file pri_encoder_using_if.v here
Encoder - Using assign Statement

1 //----------------------------------------------------2 // Design Name : pri_encoder_using_assign

3 // File Name : pri_encoder_using_assign.v

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// Function
: Pri Encoder using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_assign (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
// Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
wire [3:0] binary_out ;
assign binary_out = ( !
(encoder_in[0]) ? 0 :
(encoder_in[1]) ? 1 :
(encoder_in[2]) ? 2 :
(encoder_in[3]) ? 3 :
(encoder_in[4]) ? 4 :
(encoder_in[5]) ? 5 :
(encoder_in[6]) ? 6 :
(encoder_in[7]) ? 7 :
(encoder_in[8]) ? 8 :
(encoder_in[9]) ? 9 :
(encoder_in[10]) ? 10
(encoder_in[11]) ? 11
(encoder_in[12]) ? 12
(encoder_in[13]) ? 13
(encoder_in[14]) ? 14

enable) ? 0 : (

:
:
:
:
: 15);

endmodule

Decoder - Using case Statement

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//----------------------------------------------------// Design Name : decoder_using_case

// File Name : decoder_using_case.v
// Function
: decoder using case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module decoder_using_case (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable
// Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;
reg [15:0] decoder_out ;
always @ (enable or binary_in)
begin
decoder_out = 0;
if (enable) begin
case (binary_in)

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4'h0 : decoder_out = 16'h0001;
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4'h1 : decoder_out = 16'h0002;
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4'h2 : decoder_out = 16'h0004;
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4'h3 : decoder_out = 16'h0008;
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4'h4 : decoder_out = 16'h0010;
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4'h5 : decoder_out = 16'h0020;
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4'h6 : decoder_out = 16'h0040;
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4'h7 : decoder_out = 16'h0080;
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4'h8 : decoder_out = 16'h0100;
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4'h9 : decoder_out = 16'h0200;
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4'hA : decoder_out = 16'h0400;
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4'hB : decoder_out = 16'h0800;
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4'hC : decoder_out = 16'h1000;
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4'hD : decoder_out = 16'h2000;
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4'hE : decoder_out = 16'h4000;
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4'hF : decoder_out = 16'h8000;
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endcase
40 end
41 end
42
43 endmodule
You could download file decoder_using_case.v here
Decoder - Using assign Statement
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//----------------------------------------------------// Design Name : decoder_using_assign

// File Name : decoder_using_assign.v
// Function
: decoder using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module decoder_using_assign (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable
// Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;
wire [15:0] decoder_out ;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule

Mux : Using assign Statement

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//----------------------------------------------------// Design Name : mux_using_assign

// File Name : mux_using_assign.v
// Function
: 2:1 Mux using Assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_assign(
din_0
, // Mux first input
din_1
, // Mux Second input
sel
, // Select input

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mux_out
// Mux output
);
//-----------Input Ports--------------input din_0, din_1, sel ;
//-----------Output Ports--------------output mux_out;
//------------Internal Variables-------wire mux_out;
//-------------Code Start----------------assign mux_out = (sel) ? din_1 : din_0;
endmodule //End Of Module mux
could download file mux_using_assign.v here

Mux : Using if Statement

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You

//----------------------------------------------------// Design Name : mux_using_if

// File Name : mux_using_if.v
// Function
: 2:1 Mux using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_if(
din_0
, // Mux first input
din_1
, // Mux Second input
sel
, // Select input
mux_out
// Mux output
);
//-----------Input Ports--------------input din_0, din_1, sel ;
//-----------Output Ports--------------output mux_out;
//------------Internal Variables-------reg mux_out;
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
endmodule //End Of Module mux
could download file mux_using_if.v here
Mux : Using case Statement

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//----------------------------------------------------// Design Name : mux_using_case

// File Name : mux_using_case.v
// Function
: 2:1 Mux using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_case(

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din_0
, // Mux first input
din_1
, // Mux Second input
sel
, // Select input
mux_out // Mux output
);
//-----------Input Ports--------------input din_0, din_1, sel ;
//-----------Output Ports--------------output mux_out;
//------------Internal Variables-------reg mux_out;
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)
begin : MUX
case(sel )
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
end
endmodule //End Of Module mux

Asynchronous reset D- FF
1 //----------------------------------------------------2 // Design Name : dff_async_reset
3 // File Name : dff_async_reset.v
4 // Function
: D flip-flop async reset
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module dff_async_reset (
8 data , // Data Input
9 clk
, // Clock Input
10 reset , // Reset input
11 q
// Q output
12 );
13 //-----------Input Ports--------------14 input data, clk, reset ;
15
16 //-----------Output Ports--------------17 output q;
18
19 //------------Internal Variables-------20 reg q;
21
22 //-------------Code Starts Here--------23 always @ ( posedge clk or negedge reset)
24 if (~reset) begin
25 q <= 1'b0;
26 end else begin
27 q <= data;
28 end
29
30 endmodule //End Of Module dff_async_reset
Synchronous reset D- FF
1 //----------------------------------------------------2 // Design Name : dff_sync_reset

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// File Name : dff_sync_reset.v

// Function
: D flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dff_sync_reset (
data , // Data Input
clk
, // Clock Input
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset

Asynchronous reset T - FF
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-

//----------------------------------------------------// Design Name : tff_async_reset

// File Name : tff_async_reset.v
// Function
: T flip-flop async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= ! q;
end
endmodule //End Of Module tff_async_reset

Synchronous reset T - FF
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//----------------------------------------------------// Design Name : tff_sync_reset

// File Name : tff_sync_reset.v
// Function
: T flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= ! q;
end
endmodule //End Of Module tff_async_reset

Regular D Latch
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//----------------------------------------------------// Design Name : dlatch_reset

// File Name : dlatch_reset.v
// Function
: DLATCH async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dlatch_reset (
data , // Data Input
en
, // LatchInput
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, en, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin

27 q <= data;
28 end
29
30 endmodule //End Of Module dlatch_reset
8-Bit Simple Up Counter
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//----------------------------------------------------// Design Name : up_counter

// File Name : up_counter.v
// Function
: Up counter
// Coder?
: Deepak
//----------------------------------------------------module up_counter
(
out
, // Output of the counter
enable , // enable for counter
clk
, // clock Input
reset
// reset Input
);
//----------Output Ports-------------output [7:0] out;
//------------Input Ports-------------input enable, clk, reset;
//------------Internal Variables-------reg [7:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule

8-Bit Up Counter With Load

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//----------------------------------------------------// Design Name : up_counter_load

// File Name : up_counter_load.v
// Function
: Up counter with load
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module up_counter_load
(
out
, // Output of the counter
data
, // Parallel load for the counter
load
, // Parallel load enable
enable , // Enable counting
clk
, // clock input
reset
// reset input
);
//----------Output Ports-------------output [7:0] out;
//------------Input Ports-------------input [7:0] data;
input load, enable, clk, reset;
//------------Internal Variables--------

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reg [7:0] out;

//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (load) begin
out <= data;
end else if (enable) begin
out <= out + 1;
end
endmodule