COMPUTER ORGANIZATION

KCS 302
By
SHIVANI AGARWAL
Department of Computer Science & Engineering
IMS Engineering College, Ghaziabad
 BUS
 A bus is a communication pathway connecting two or more devices.
A key characteristic of a bus is that it is a shared transmission
medium.

a b c
 Multiple devices connect to the bus, and a signal transmitted by any
one device is available for reception by all other devices attached to
the bus. so that create garble(destroyed),so for that solution we use
arbitration.
 A bus is a subsystem that is used to connect computer components
and transfer data between them. For example, an internal bus
connects computer internals to the motherboard.
 A bus may be parallel or serial. Parallel buses transmit data across
multiple wires. Serial buses transmit data in bit-serial format.
 Data is transmitted from one part of a computer to another,
connecting all major internal components to the CPU and memory,
by the means of Buses.
 Types of Buses
 Data Bus: It carries data among the memory unit, the I/O devices, and the
processor. the number of lines in data bus is known as width of data bus for ex :-
16,32,64 that means 16 bits data transfer at a time. each line carries one bit at a
time parallel.
 Address Bus: It carries the address of data (not the actual data) between
memory and processor. The address lines are used to designate the source or
destination of the data on the data bus.
 For example, on an 8-bit address bus, address 01111111 and below might
reference locations in a memory module (module 0) with 128 words of memory,
• For example:- 23 = 8 i.e. 3 address line is required to select 8 location, In general

2x = n

where x number of address lines (address bit) and n is number of

location
 Types of Buses
1. Control Bus: It carries control commands from the CPU
(and status signals from other devices) in order to control
and coordinate all the activities within the computer.
System bus:- a bus consists of multiple communication
pathways, or lines. Each line is capable of transmitting
signals representing binary 1 and binary 0. An 8-bit unit of
data can be transmitted over eight bus lines. A bus that
connects major computer components (processor, memory,
I/O) is called a system bus.
BUS INTERCONNECTION STRUCTURE

The operation of the bus is as follows. If one module wishes to send data to
another, it must do two things:
(1) obtain the use of the bus, and (2) transfer data via the bus.
If one module wishes to request data from another module, it must (1) obtain the
use of the bus, and (2) transfer a request to the other module over the
appropriate control and address lines. It must then wait for that second module
to send the data.
 Basic bus types
1. Dedicated – assigned to a single function (e.g. address bus)
or a physical subset of components (e.g. I/O bus connects all
I/O modules).
1.1 Functional dedication:- means a separate bus for each
different function. For example transferring data in to another
bus, address in to another and control is also an another bus.
1.2 Physical Dedication:-Use of separate buses connecting
different system components that means each component
needs different buses .(for example:- address needs by two
components so both needs different address buses.)
Advantage of dedicated bus:- High Throughput, less waiting
time.
Disadvantage of dedicated bus:- High cost(larger bus circuitry)
Basic bus types
Multiplexed:- a common bus can be used for both
addresses and data for transmission.
In this case, an address valid control line(that means first
we validate the address then data) is needed to determine
whether the data is an address or data. Time multiplexing
is using the same lines for multiple purposes.
Example if we have three devices A,B,C those are
connected with common bus system and buses have
address signal activate then devices find out which device
address received ,when address validates then it
deactivates and data bus activate on this common bus
system.
Advantage:- due to few lines (less cost and space)
Disadvantage:- high complex circuitry.
 Bus & Memory Transfer
A conventional digital computer system has many
registers and many number of wires used to transfer
information from one register to another.
The number of wires will be accessible if separate lines
are used. so to solve this problem defined a efficient
scheme known as common bus system.
A bus structure consist of common lines 1 for each bit of
a register, through which binary information is transferred
one at a time.
There are two ways of common bus system:-
1) Multiplexer 2) Decoder
 Multiplexer
Consider an integer ‘m’, which is
constrained by the following relation:
m = 2n ,
where m and n are both integers.
 A m-to-1 Multiplexer has
 m Inputs: I0, I1, I2, ................ I(m-1)
 one Output: Y
 n Control inputs: S0, S1, S2, ...... S(n-1)
 One (or more) Enable input(s)

such that Y may be equal to one of the inputs, depending upon

the control inputs.
Multiplexer

2n * 1
2n MUX
Y

E-enable input
 Example: A 4-to-1 Multiplexer

A 4-to-1 Multiplexer:

I0

22 inputs I1 Y
I2
1 output
I3

Enable (G) S0 S1
n control inputs
 Characteristic Table of a Multiplexer
If the MUX is enabled,
s0 s1
0 0 Y I0
0 1 Y I1
1 0 Y I2
1 1 Y I3

Putting the above information in the form of a Boolean equation,

Y =E. I0. S’1. S’0 + E. I1. S’1. S0 + E. I2. S1. S’0 +E. I3. S1. S0
COMMON BUS SYSTEM BY USING MUX

A bus system with K registers of n bits. Each to

produce n line common bus system, the number
of MUX needed to construct the bus is n. The
size of each MUX must be K * 1.
 Question:-
Design a common bus system by using multiplexer
if we have 4 registers and each register has 4 bits. Also
find out :-
a) How many MUX required?
b) Find out the size of MUX.
The following block diagram shows a common Bus system for 4(K)
registers. It is constructed with the help of (K*1) 4 * 1 Multiplexers
each having n=4 inputs (0 through 3) and 2 selection inputs (S1 and
S2).
We have used labels to make it more convenient for you to
understand the input-output configuration of a Bus system for four
registers. For instance, output 1 of register A is connected to input 0
of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs
of all four multiplexers. The selection lines choose the four bits of one
register and transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0
data inputs of all four multiplexers are selected and applied to the
outputs that forms the bus. This, in turn, causes the bus lines to
receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines
will receive the content provided by register B.
The following function table shows the register that is selected by the
bus for each of the four possible binary values of the Selection lines.
 Question
Design a common bus system by using multiplexer if
we have 8 registers and each register has 16 bits.
Also find out :-
a) How many MUX required?
b)Find out the size of MUX.
 COMMON BUS SYSTEM BY USING
DECODER
• A bus system can also be constructed using tri-state gates instead of
multiplexers.
• The Tri state gates can be considered as a digital circuit that has
three state, two of which are signals equivalent to logic 1 and 0 as
input. However, the third state exhibits as a control logic. That is
defined open or closed circuit.
•If it is open then the output is high Impedance and if it is closed then
output is same as input.
The graphical symbol of a :three-state buffer gate can be represented
as:

Control Input Output

0 0 Z
0 1 Z
1 0 0
1 1 1
 Decoder

 A 2x4 Decoder is like:

Digital Logic Design

•The outputs generated by the four buffers are connected to form a
single bus line.
•Only one buffer can be in active state at a given point of time.
•The control inputs to the buffers determine which of the four normal
inputs will communicate with the bus line.
•A 2 * 4 decoder ensures that no more than one control input is
active at any given point of time.
Memory Transfer
Memory Transfer
Memory Transfer
Memory Write
 Register Transfer language
A digital computer system exhibits an interconnection of
digital modules such as registers, decoders, arithmetic
elements, and Control logic.
These digital modules are interconnected with some
common data and control paths to form a complete digital
system.
Moreover, digital modules are best defined by the registers
and the operations that are performed on the data stored in
them.
The operations performed on the data stored in registers
are called Micro-operations.
MICROINSTRUCTIONS &
OPERATIONS
 R1: A+B
 R1 M[A] + M[B] MICRO OPERATION
 R1 M[A] + M[B] ,R2  R1 MICRO
INSTRUCTION

A micro-operation is an elementary operation performed

on the information stored in one or more registers, the
result of the operation may replace the previous binary
information or may be transfer to another registers.
Examples of micro operations are:-
shift ,count, clear and load
 Register Transfer language
The Register Transfer Language is the symbolic representation
of notations used to specify the sequence of micro-operations
and transfer the result of the operation to the same or another
register.
The internal hardware organization of a digital system is best
defined by specifying:
The set of registers and the flow of data between them.
The sequence of micro-operations performed on the data which
are stored in the registers.
The control paths that initiates the sequence of micro-operation
Computer registers are designated by capital letters:-
MAR ,MBR IR
In a computer system, data transfer takes place between
processor registers and memory and between processor
registers and input-output systems. These data transfer can
be represented by standard notations given below:
Notations R0, R1, R2..., and so on represent processor
registers.
The addresses of memory locations are represented by
names such as LOC, PLACE, MEM, etc.
Input-output registers are represented by names such as
DATA IN, DATA OUT and so on.
The content of register or memory location is denoted by
placing square brackets around the name of the register or
memory location.
Types of instruction
Data transfer instruction
Data manipulation instruction
Program control instruction
 Data transfer instruction
The data transfer instructions are used to transfer data from
one location to another. This transfer of data can be either
from register to register, register to memory or memory to
register. It is important to note here that the memory to
memory transfer of data directly is not possible.
Following are some instructions that are used for data
transfer purpose:
MOV LOAD
PUSH XCHG
POP IN OUT
 STORE
 Data manipulation instruction

Data manipulation have arithmetic operations, logical operations

and shift operations.
Arithmetic operations :-
1. ADD 5. INC
2. SUB 6. DEC
3. MUL 7. ADD With Carry
4. DIV 8. Subtract with borrow 9. Negate
Logical Operations:-
1. Compliment (COM) 4. Ex-OR 7. Set carry
2. CLEAR(CLR) 5. Clear Carry 8. Compliment carry
3. Logical AND 6. Logical OR 9.Enable Interrupt/Disable
Data manipulation instruction

Shift operations:-
1. Logical Shift left
2. Logical shift right
3. Arithmetic shift left
4. Arithmetic shift right
5. Rotate left
6. Rotate right
7. Rotate left with carry
8. Rotate right with carry
Program Control Instructions
When CPU process the data from consecutive memory
locations so each time one instruction is fetched from
memory and the program counter is incremented.
It has two types of instructions:-
1) Unconditional
2) Conditional
Unconditional:- An unconditional branch instruction
means control proceeds the next instruction in
sequence.
Conditional:- A conditional branch instruction means
control proceeds the next instruction when the
condition met .
Program Control Instructions
JUMP
SKIP
BRANCH
CALL
RETURN
COMPARE
VON NEUMANN
ARCHITECHURE
Von Neumann architecture was first published by
John von Neumann in 1945. Von Neumann
architecture is based on the stored-program computer
concept, where instruction data and program data are
stored in the same memory.
VON NEUMANN
ARCHITECHURE

MAIN MEMORY

Program
Data
or
A=10;
instructio
B=5
n
C=A+B
 VON NEUMANN
ARCHITECHURE
Central processing Unit:- These have many components:-
1) ALU:- perform logical operations, speed is very fast
2) Registers:- it is a set of flip-flop, it has very small in
size but speed is very high so that it's as temporary
storing memory, that is used to store intermediate results.
There are many registers:-
Types of Registers
Accumulator: Stores the results of calculations made by ALU.
Program Counter (PC): A program counter is one of the register used in
computer architecture and OS. It holds the address of next instruction to be
executed. After instruction is executed, it will incremented by one,(PC =PC
+1) moreover program counter will be point to the next instruction. The
PC then passes this next address to Memory Address Register (MAR).
Memory Address Register (MAR): It stores the memory locations of
instructions that need to be fetched from memory or stored into memory.
Memory Data Register (MDR): The Memory Buffer Register stores
information that is being sent to, or received from, the memory along the
bidirectional data bus.
Current Instruction Register (CIR): It stores the most recently fetched
instructions while it is waiting to be coded and executed.
Instruction Buffer Register (IBR): The instruction that is not to be
executed immediately is placed in the instruction buffer register IBR.