GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

IV B.Tech (EEE) I sem supplementary Examination June 2023
MICROPROCESSORS AND MICROCONTROLLERS

Course Code: 18EC4110 Reg: AR18

PART A: Answer all questions

1 a) size of segment -64KB and

list of segments: Data Segment, Extra Segment, Code Segment, Stack Segment

b) MN/MX’ is the signal which is used to differentiate signal in 8086.

If MN/MX’=0 works in Max mode
If MN/MX’=1 works in Min mode

c) LEA: Load Effective Address

This instruction determines the offset of the variable or memory location named as the source
and puts this offset in the indicated 16-bit register.
Example:
str1 db 'My first string. $'
ptr_str1 dd str1
lea SI, str1

LDS: Load Data Segment

lds means Load pointer using DS
lds SI, ptr_str1

d) Any Four Assembler Directives List:

ASSUME, DB, DT, DD, EQU, SEGMENT & END DIRECTIVES,

ORIGIN,PUBLIC,OFFSET

e) Port C bits in Simple IO and Handshake IO modes of 8255

Simple IO: Mode 0 – Simple or basic I/O mode: Port A, B and C can work either as input
function or as output function. The outputs are latched but the inputs are not latched. It has
interrupt handling capability.
Mode 1 – Handshake or strobed I/O: In this either port A or B can work and port C bits are
used to provide handshaking. The outputs as well as inputs are latched. It has interrupt
handling capability. Before actual data transfer there is transmission of signal to match speed
of CPU and printer. Example: When CPU wants to send data to slow peripheral device like
printer, it will send handshaking signal to printer to tell whether it is ready or not to transfer the
data. When printer will be ready it will send one acknowledgement to CPU then there will be
transfer of data through data bus.

Strobe, Acknowledgement signals acts as handshaking signals

f) Arrange the following instructions inorder

DIV ZERO, NMI, INTR

g) Memory types used with 8051

Program Memory and Data Memory.

The 8051 microcontroller's memory is divided into Program Memory and Data Memory.
Program Memory (ROM) is used for permanent saving program being executed, while Data
Memory (RAM) is used for temporarily storing and keeping intermediate results and variables.

h) CALL instructions in 8051

LCALL –long CALL
ACALL – Absolute CALL

i) Timers and size: 2 timers Timer 0 and Timer 1 of 16bit each

j) Simplex and Full Duplex serial transfer modes:

It is a mode of transmission in which the flow of data is unidirectional. It means that the participant can
do only one task at a time in a single direction. The receiver can only receive data and not send it (and
vice versa).

It is a mode of transmission in which the flow of data is bi-directional. But here, the devices can send as
well as receive data simultaneously at the same time. It means that the receiver can receive as well as
send data at the very same time with no hitch.
PART B:

8086 Architecture with neat diagram:

FUNCTIONAL BLOCK DIAGRAM: (Block Diagram / Architecture) 8086 Microprocessor

consists of two parts : EU (Execution unit) and BIU (Bus Interface Unit).BIU interfaces with
the computer Bus and performs data transfer with the Memory. EU executes instructions
from the instruction system byte queue.Both units operate asynchronously to give the 8086
an overlapping instruction fetch and execution mechanism whichis called as Pipelining. This
results in efficient use of the system bus and system performance.BIU contains Instruction queue
(six bytes), Segment registers, Instruction pointer, and Address adder to generate the physical
address of the memory from thelogical address in the program.EU contains Control circuitry,
Instruction decoder, ALU, Pointer and Index register and Flag register.BUS INTERFACR
UNIT:❖It provides a full 16 bit bidirectional data bus and 20 bit address bus.❖The bus
interface unit is responsible for performing all external bus operations.Specifically it has the
following functions:
Geethanjali College of Engineering & Technology –ECE Department MPMC
Course File48❖Instruction fetch, Instruction queuing, Operand fetch and storage, Address
relocation and Bus control.❖The BIU uses a mechanism known as an instruction stream queue
to implement apipeline architecture.❖This queue permits prefetch of up to six bytes of
instruction code. Whenever the queue of the BIU is not full, it has room for at least two more
bytes and at the same time the EU is not requesting it to read or write operands from memory,
the BIU is free to look ahead in the program by prefetching the next sequential
instruction.❖These prefetching instructions are held in its FIFO queue. With its 16 bit
data bus, the BIU fetches two instruction bytes in a single memory cycle.❖After a byte is
loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty
location nearest the output.❖The EU accesses the queue from the output end. It reads one
instruction byte after the other from the output of the queue. ❖These intervals of no bus activity,
which may occur between bus cycles are known as Idle state.❖If the BIU is already in the
process of fetching an instruction when the EU request it to read or write operands from memory
or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read /
write cycle.❖The BIU also contains a dedicated adder which is used to generate the 20 bit
physical address that is output on the address bus. This address is formed by combining
the current contents of the code segment CS register and the current contents of the
instruction pointer IP register.❖The BIU is also responsible for generating bus control
signals such as those for memory read or write and I/O read or write.❖It has internally B-Bus
and C-Bus.EXECUTION UNITThe Execution unit is responsible for decoding and executing all
instructions.❖The EU extracts instructions from the top of the queue in the BIU,
decodes them, generates operands if necessary, passes them to the BIU and requests it to
perform the read or write bys cycles to memory or I/O and perform the operation
specified by the instruction on the operands.❖During the execution of the instruction, the EU
tests the status and control flags and updates them based on the results of executing the
instruction.❖If the queue is empty, the EU waits for the next instruction byte to be
fetched and shifted to top of the queue.❖When the EU executes a branch or jump
instruction, it transfers control to a location corresponding to another set of sequential
instructions.