COMMON BUS SYSTEM DCS114/SSS114

DSE114/CSE114

LECTURE 5

BY
Mr. Bagaiga Richard
Email: bbagaiga@gmail.com
1
 COMMON BUS SYSTEM
■ BUS: A wire or a collection of wires that carry some multi-bit information is known as
bus. Main purpose of bus is to transfer information form one system to another
DESCRIPTION:
■ The basic computer has eight registers (AC, PC, DR, AC, IR, TR, INPR, OUTR), a
memory unit and a control unit. Path must be provided to transfer information from
one register to another and between memory and registers.
■ The number of wires will be excessive if connections are made between the output
of each register and input of other registers. A more efficient scheme is to use a
common bus.
■ Thus common bus provides a path between memory unit and registers.
BUS AND MEMORY TRANSFERS
.
■ A more efficient scheme for transferring information between registers in a multiple-
register configuration is a common bus system.
■ A bus structure consists of a set of common lines, one for each bit of a register,
through which binary information is transferred one at a time. Control signals
determine which register is selected by the onus during each particular register
transfer
The basic computer has 8 registers. The registers with their
names, size and functions are listed below:
Five registers have three control inputs: LD (load), INR
(increment) and CLR (clear). Two registers have only a LD input

Load (LD):
■ The lines from the common bus are connected to the inputs of each register and the
data inputs of the memory. The particular register whose LD input is enabled
receives the data from the bus.
Increment (INR)) and Clear (CLR):
■ The contents of the particular register are incremented when its INR signal is
enabled and cleared when its CLR signal is enabled.
CIRCUIT OPERATION DESCRIPTION

■ Memory Unit:
The memory receives the 16-bit information from the bus when its write input is enabled
and the memory places its 16-bit information onto the bus when its read input is
activated and S2S1S0 = 111.

■ Address Register (AR):

This register specifies the address in memory for next read or writes operations. The
address register consists of 12 bits.
When selection inputs S2S1S0 =001 is applied to the bus, the address register AR
receives or transfers address from or to the bus when its LD input is enable. The
address is incremented or clear by the inputs INR or CLR.
 CIRCUIT OPERATION DESCRIPTION
■ Program Counter (PC):
Program counter has 12 bits and it holds the address of the next instruction to be read from
memory after the current execution is executed.
When selection inputs S2S1S0 = 010 is applied to the bus, the program counter (PC)
receives or transfers address from or to the bus when its LD input is enable. The address is
incremented or clear by the inputs INR or CLR.
■ Data Register (DR):
The register DR consists of 16-bits and memory operands (data). This register contains the
data to be written into memory or receives the data read from memory.
When selection inputs S2S1S0 = 011 is applied to the bus, the data register DR receives or
transfers data from or to the bus when its LD input is enable. The data is incremented or
clear by the inputs INR or CLR.
CIRCUIT OPERATION DESCRIPTION

■ Accumulator (AC):
The processor register AC consists of 16 bits. The 16-bit inputs to the Adder / logic
circuit come from the outputs of AC. They are used to implement register micro
operation such as complement and shift the contents of AC.
The results of these micro operations are again transferred to AC. So an accumulator is
a register in which intermediate arithmetic and logic results are stored.
When selection inputs S2S1S0 = 100 is applied to the bus, the processor register AC
receives or transfers its data to the bus by enabling the LD input of DR, it transfers the
contents of DR through the adder / logic circuit into AC when its LD input is enable. The
data of AC is incremented or clear by the inputs INR or CLR.
CIRCUIT OPERATION DESCRIPTION
■ Instruction Register (IR):
The instruction register consists of 16-bits. The purpose of the instruction register is to
hold a copy of the instruction which the processor is to execute. The instruction read
from memory is placed in the IR.
When selection inputs S2S1S0 = 101 is applied to the bus, the instruction register IR
receives or transfers instruction code from or to the bus when its LD input is enable.
■ Temporary Register (TR):
Temporary registers have 16 bits. It provides temporary storage of variables or results.
When selection inputs S2S1S0 = 111 is applied to the bus, the temporary register TR
receives or transfers temporary data from or to the bus when its LD input is enable. The
data is incremented or clear by the inputs INR or CLR.
CIRCUIT OPERATION DESCRIPTION

■ Input Register (INPR):

The Input Register INPR consists of 8-bits and hold alphanumeric input information. The
serial information from the input device is shifted into input of 8-bit register INPR.
When LD input of AC is enable, the 8-bit information of INPR is transferred to the AC via
Adder/logic circuit.
■ Output Register (OUTR):
The output OUTR receives information from AC and transfers it to the output device.
BUS AND MEMORY TRANSFERS

A bus structure consist a set of common lines each for each register, through which
binary information can transfer one at time. Control signal determine that which register
is connected with a bus line at time to transfer the information.
Here we will see two ways to construct the bus :
■ By using multiplexers.
■ By three state buffer
Common bus using multiplexers

■ One way of constructing bus system is by using multiplexers. The multiplexer select
the one register who ‘s information is transfer to another one destination register.
■ In a bus system, multiplex K register of n bits each to produce an n lines common
bus .
■ The number of multiplexers needed to construct the bus is equal to n.
14
The construction of bus system for four bit, four register is given below
■ As we know that for n bit we require n multiplexer, for k register transfer we require k-1
size of multiplexer.
■ Here we have n=4 and k=4 hence here we use four multiplexer each having 4-1 size.
■ Here each register have 4 positive triggered flip flop set. because each mux is 4-1 each
multiplexer have 2 selection inputs in the bus

■ we denote it by S0 and S1. This selection input select the one line output from 0 to 3
available in the each multiplexer, and applied to the output that form a bus system.
■ To avoid the complicated figure we just write output and input at the connection. For
example output A1 of register A is connected with the input line 0 of mux(1) because
that input is labeled as A1
construction of bus system

■ The two selection lines S and S are connected to the selection inputs of all four
multiplexers.
■ The selection lines choose the four bits of one register and transfer them into the
four-line common bus.
■ When S1S0 =00, the 0 data inputs of all four multiplexers are selected and applied
to the outputs that form the bus.
■ This causes the bus lines to receive the content of register A since the outputs of
this register are connected to the 0 data inputs of the multiplexers.
■ Similarly, register B is selected if S1S0= 0 1, and so on.
Function Table for Bus
General state representation of transferring data
between registers using bus

■ The transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all destination registers
and activating the load control of the particular destination register selected.
■ The symbolic statement for a bus transfer may mention the bus or its presence may
be implied in the statement. When the bus is includes in the statement, the register
transfer is symbolized as follows.

BUS ← C, R1 ← BUS
THREE-STATE BUS BUFFERS
■ An inverter is called a NOT gate, and it looks like:

■ The inverter is a triangle, followed by a circle/bubble. That circle sometimes appears

by itself, and means negation.
■ What if we remove the circle? What kind of gate would we have? We'd have a buffer

■ The output of buffer input is exactly same. Thus, if the input, x is 0, the output, z is 0.
If the input, x is 1, the output, z is 1.
Common bus using three state bus
buffer
■ One way of constructing bus system is by using multiplexers. The multiplexer select
the one register who ‘s information is transfer to another one destination register.
■ In a bus system, multiplex K register of n bits each to produce an n lines common
bus .
■ The number of multiplexers needed to construct the bus is equal to n.
Common bus using three state bus
buffer
■ A bus system can be constructed with three-state gates instead of multiplexes. A
three-state gate is a digital circuit that exhibits three states. Two of the states are
signals equivalent to logic 1 and 0 as in a conventional gate.
■ The third state is a high-impedance state. The high-impedance state behaves like an
open circuit which means that the output is disconnected and does not have a logic
significance.
■ Three-state gates may perform any conventional logic, such as AND or NAND.
However, the one most commonly used in the design of a bus system is the buffer
gate
tri-state buffer
■ A tri-state buffer is a useful device that allows us to control when current passes
through the device, and when it doesn't.
■ A tri-state buffer has two inputs: a data input x and a control input c.
■ When the control input is active, the output is the input. That is, it behaves just like a
normal buffer.
■ When the control input is not active, the output is "Z", and no electrical current flows
through. Thus, even if x is 0 or 1, that value does not flow through
■ Because of this feature a large number of three state gate output can be connected with
wires to form a common bus line. Function table for three state bus is:

■ In this case, when the output is Z, that means it's high impedance, neither 0, nor 1, i.e.,
no current.
Why Tri-State Buffers?

■ A common way for many devices to communicate with one another is on a bus, and
that a bus should only have one device writing to it, although it can have many
devices reading from it.
■ Since many devices always produce output (such as registers) and these devices are
hooked to a bus, we need a way to control what gets on the bus, and what doesn't.
■ A tri state buffer is good for that.
 Here's an example:

■ There are three devices, each of which output 32 bits. These devices have their
outputs hooked to a 32 bit bus.
Construct a Common Bus Line with three
state buffer
■ The construction of a bus system have four buffers. The output of the four buffers
are connected together to form a single bus line.
■ At a particular time only one buffer is in active state. The connected buffers must be
controlled so that only one tri state buffer has access to the bus line while other
buffers are maintained in a high impedance
■ Decoder will decodes the codes in set of signals and it ensures that no more than
one control input is active.
■ When the Enable input of the decoder is 0, all of its four outputs are zero and the
bus line is in high impedance state because all four buffers are disabled.
■ When the enable input is active, one of the tri state buffer is active.
There are 3 parts to a bus
 data bus
for data and program instructions
 control bus
control signals from the CU to the devices, and feedback lines for ack that
they are ready or for interrupting the CPU
 address bus
the address of the memory location or I/O device that is to perform the
given operation
The Bus
 Additionally, computers may have multiple buses
 Local bus
 connects registers, ALU and CU together
 System bus
 connects CPU to main memory
 Expansion or I/O bus
 connects System bus to I/O devices
More on Buses
■ Buses connect two types of devices
– Masters
■ Devices that can initiate requests
– CPU
– some I/O devices
– Slaves
■ Devices that only respond to requests from masters
– Memory
– some I/O devices
More on Buses
Point-to-point
Buses
■ Some buses are dedicated
– The bus directly connects two
devices (point-to-point bus) Multipoint
network
■ Most buses connect multiple
components
– multipoint

Multipoint
Expansion bus
 The System Bus

■ Main memory connects to this bus through pins

■ The I/O subsystem connects to this bus through the expansion bus
■ The bus carries three types of information
– The address from the CPU of the intended item to be accessed
– The control information (read versus write, or status information like “are you
available?”)
– The data, either being sent to the device, or from the device to CPU
Expansion bus
■ The expansion bus
– is the collection of expansion slots and what gets plugged into them
– Here we see interface cards (or expansion cards), each with the logic to interface
between the CPU and the I/O device (e.g., printer, MODEM, disk drive)
Who gets to use the bus?
■ In a point-to-point buses this is not a problem
■ In the expansion bus where multiple I/O devices may want to communicate
between themselves and the CPU or memory at the same time – we need a
form of Bus Arbitration

– Daisy chain arbitration

■ Each device has a bus request line on the control bus
■ When a device wants to use the bus, it places its request and the
highest priority device is selected (this is an unfair approach)
Who gets to use the bus?
– Centralized parallel arbitration
■ The bus itself contains an arbiter (a processor) that decides
■ The arbiter might become a bottleneck, and this is also slightly more
expensive

– Distributed arbitration
■ Devices themselves to determine who gets to use the bus, usually
based on a priority scheme, possibly unfair

– Distributed arbitration using collision detection

■ It’s a free-for-all, but if a device detects that another device is using the
bus, this device waits a short amount of time before trying again
THE END