Subject Name: Computer Organization

Subject Code: PCC-CS302

Teacher Detail’s
Sheuli Chakraborty
Assistant Professor
Dept of IT
Asansol Engineering College
Class 4
Recap (Class 3):

From the last class we learnt

 Sequential Circuits
 Register
 Buffer register
 Load Control Register
 Right Shift Register
 Left Shift Register
 This Class Covers

Micro Operations
Register Transfer Micro Operation
Special Purpose Register
Common Bus System Using Multiplexer
Common Bus System Using Tri-state Buffer
Memory Transfer
 Micro Operations

ALU is the main part of the CPU (Central Processing Unit) in

processing the instructions.

Other parts of the CPU are Control Unit (CU) and Register unit.

ALU executes the instructions in the order as dictated by the

CU on the operand data stored in registers.

A CPU with many registers reduces the no of main memory

references.
 Classifications of Micro Operations

Register Transfer Micro Operations

Arithmetic Micro Operations
Logical Micro Operations
Shift Micro Operations
 Register Transfer Micro Operations
Computer contain some registers within CPU for faster
executions
No of register differ from Processor to Processor
A register is nothing but a group of flip-flops capable of
storing one bit of information.

e.g.
a)Accumulator
b)General Purpose Register
c)Special Purpose Register
(A computer contain a no of Special Purpose Registers)
 Special Purpose Register
 Program Counter (PC)

 Instruction Register (IR )

 Stack Pointer (SP)

 Base Register (BR)

 Memory Address Register (MAR)

 Memory Buffer Register (MBR) or Data Register (DR)

 Status Register (SR) or Program Status Word (PSW)

 Register Transfer

 Information transfer from one register to another is

designated as: R2 R1.

 Normally we want the transfer to occur under a

predetermined condition as
If(P=1) then (R2 R1. )

 P is the control signal. Generally control function in

included in the statement as follows:
P: R2 R1

 Every statement in RTL need hardware for above

RTL hardware will be as:
Transfer from R1 to R2
 Bus and Memory Transfer
 Digital computer have many registers and paths must be
provided to transfer information.

 No. of wires will be excessive if we connect each register with

the other one.

 A more efficient scheme for transferring information in

multiple register system is by the use of the common bus
system.

 Control signals are used to select the register

 One way of constructing a common bus system is by the use

of multiplexer.

 Figure below show the 4 register common bus system.

 It consist of Multiplexer and selection lines

Common Bus System using Multiplexer
Function Table for Common Bus
 In general, a bus system will multiplex k registers of n bits each to produce
an n-line common bus.

 Common bus for 8 registers of 16 bits requires, 16 multiplexer having 8 data

input lines.

 The transfer of information from bus to one of many register can be

accomplished by connecting bus lines to the inputs of all register and
activating the load signal of required one.
 If we need to transfer the content of register C to register
R1, it can be represented as:

 It is convenient to show the direct transfer as

 Common Bus using Tri-state Buffer

 A bus system can also be constructed using three state gate.

 Three state gate has 3 outputs one low and other high as like other
gates.

 The third output is the high impedance state which behave like the
open circuit and does not have any logic significance.

 The most commonly used gate in bus design is the is 3 state buffer
gate.
Tri-State Buffer
Single Line of Common Bus
 Memory Transfer
 Transfer of information from memory word to outside environment is
read operation.

 Transfer of new information to be stored into the memory is called

write operation.

 Memory word is symbolized by M and address by enclosing in the

square bracket.

 Read and write operation can be stated as:

Read: DR  M[AR]
Write: M[AR]  R1
Thank You