Asynchronous and Synchronous

data transfer using 8251A

 INTRODUCTION
 8251A is a USART (Universal Synchronous Asynchronous
Receiver Transmitter) for serial data communication.
 It is a programmable peripheral interface designed for synchronous
/asynchronous serial data communication.
 Serial data transmission is widely used in communications over long
distances. Parallel communication requires many wires to be laid between
the two communicating points. Hence, usually data is converted to serial
format and sent over fewer number of wires to the destination.
 Receives parallel data from the microprocessor & transmits serial data
after conversion of parallel data to serial data.
 Also receives serial data from the outside & transmits parallel data to the
microprocessor after conversion of serial data into parallel data.
BASICS OF SERIAL COMMUNICATION
• The process of sending data bit by bit sequentially, over a single
channel between sender and receiver is known as serial transmission
of data.
• It requires only one communication line rather than n lines to transmit
data from sender to receiver.
• For correct data transmission, there has to be some form of
synchronization between transmitter and receiver.
• Serial communication reduce the cost of an IC package by reducing
the number of pins used for communication between different IC’s,
instead of using parallel communication.
BASICS OF SERIAL COMMUNICATION
• Bit rate: - Number of bits sent every second (BPS)
• Baud rate: - Number of symbols sent every second, where
every symbol can represent more than one bit.
• The sender and receiver must agree on a set of rules (Protocol) on :
1. When data transmission begins and ends.
2. The used bit rate and data packaging format.
SYNCHRONOUS VS ASYNCHRONOUS
• Synchronous data transfer:
• Sender and receiver use the same clock signal
• Supports high data transfer rate
• Needs clock signal between the sender and the receiver
• A master (or one of the senders) should provide the clock signal to all the receivers in
the synchronous data transfer.

• Asynchronous data transfer:

• For asynchronous data transfer, there is no common clock signal between the sender
and receivers.
• Sender provides a synchronization signal to the receiver before starting the transfer
of each message
• The sender and the receiver first need to agree on a data transfer speed.
• slower data transfer rate
Definition of Serial Synchronous Transmission
• Synchronous Transmission is efficient, reliable and is used for transferring a
large amount of data.
• Communication is performed is based on a synchronization signal added to
each bit from the sending side.
• Synchronization between the source and target is required so that the
source knows where the new byte begins since there is no space between
the data.
• It provides real-time communication between connected devices. Chat
Rooms, Video Conferencing, telephonic conversations, as well as face to
face interactions, are some of the examples of Synchronous Transmission.
Definition of Asynchronous Transmission
• In Asynchronous Transmission data flows as1 byte or a character at a time.
• For asynchronous transmission, a start bit is used to identify the beginning of each
character and at least one stop bit is used to identify end of data character, this is known as
bit synchronization.
• Effectively, the sender and receiver are synchronized on a character by character basis.
• Asynchronous serial data communication is widely used for character-oriented
transmissions, while block-oriented data transfers use the synchronous method.
• In the asynchronous method, each character is placed between start and stop bits. This is
called framing.
DATA TRANSMISSION TYPES
• Simplex:
- Communication is possible in one direction only.
Ex.TV

• Half duplex:
- Communication is possible in both directions, but only one TX and one RX at a
time. Ex. Police radio
DATA TRANSMISSION TYPES
• Full duplex: -
Communication is possible in both directions, both sides can transmit and
receive in the same time.
 USART
• The USART module is a full duplex, serial I/O
communication peripheral.
• It is packed in a 28 pin DIP.
• It contains all shift registers, clock generators and data buffers needed
for serial communication.
• It can work in synchronous mode, or in asynchronous mode.
• The USART uses two I/O pins to transmit and receive serial data. Both
transmission and reception can occur at the same time i.e. ‘full
duplex’ operation.
 USAR
T
• To send a byte, the application writes the byte to the transmit buffer.
The USART then sends the data, bit by bit in the
requested format, adding Stop, Start, and parity bits as needed.
• In a similar way, the USART stores received bytes in the
receiver buffer.
Then the USART can generate an interrupt to notify
the processor to find out if data has arrived.
Block diagram of the 8251 USART
 Sections of 8251
• Data Bus buffer
• Read/Write Control Logic
• Modem Control
• Transmitter
• Receiver
1. Data Bus Buffer:
• This is bidirectional 8-bit buffer used to interface internal data bus of 8251 to
the microprocessor’s data bus. The direction of data transfer through the data
bus is decided by RD and WR signal. This buffer transfers control word, status
word and data to transfer.
 2. Read/Write Control logic
• Itcontrols the operation of the peripherals depending upon
the operation initiated by CPU.
• The control signals RD, WR, C/D, CTS, CLK and RESET are
given to this block to generate control signals for this device.
• Itincludes a control logic, six input control signals & three
buffer registers:
(a) TWO 8-bit data buffer registers : one is for transmitter and other is for
receiver.
(b) One 16-bit control word register, named as two separate registers: mode
word register and command word register.
(c) One 8-bit status register.
 Contd.

• Control logic : Interfaces the chip with MPU, determines the

functions of the chip according to the control word in the control
register & monitors the data flow.
• Control Register: 16-bit register for a control word consist of two
independent bytes namely mode word & command word.
• Mode word : Specifies the general characteristics of operation such as baud
rate, parity, number of bits etc.
• Command word : Enables the data transmission and reception.
 Contd.
Status register:
• Checks the ready status of the peripheral.
•Status word in the status register provides the information
concerning register status and transmission errors.
Data register
Used as an input and output port when the C/D is low
 3. Transmitter section
• Accepts parallel data from MPU & converts them into serial data.
• Has two registers:
• Buffer register : To hold eight bits
• Output register : To convert eight bits into a stream of serial bits.
• The MPU writes a byte in the buffer register.
• Whenever the output register is empty; the contents of buffer
register are transferred to output register.
• Whenever we want to transmit a character, that character must be
placed inside the transmitter buffer, which is to be shifted to output
register, from where it transmit the data bit by bit using TxD pin.
• Transmitter section consists of three output & one input signals
• TxD - Transmitted Data Output : Output signal to transmit the data to
peripherals
• TxC - Transmitter Clock Input : Input signal, controls the rate
of transmission.
• TxRDY - Transmitter Ready : Output signal, indicates the
buffer register is empty and the USART is ready to accept the next
data byte.
• TxE - Transmitter Empty : Output signal to indicate the output register
is empty and the USART is ready to accept the next data byte.
 5. Receiver Section
• Accepts serial data on the RxD pin and converts them to parallel data.
• Has two registers :
• Receiver input register
• Buffer register
 Contd.

• Receiver section receives data bit by bit on RxD line in the input
register and at the rate determined by receiver clock.
• The input register converts the serial data into parallel data and
transferred to the receiver buffer register.
• When the data byte is transferred from the input register to receiver
buffer register, the control logic generates a signal RxRDY to signal
processor about the availability of data byte to be read by processor.
 Control signals of Receiver section
 When RxD goes low, the control logic assumes it is a start bit, waits for
half bit time, and samples the line again. If the line is still low, the input
register accepts the following data, and loads it into buffer register at the
rate determined by the receiver clock.
 RxRDY - Receiver Ready Output: Output signal, goes high when the USART
has a character in the buffer register & is ready to transfer it to the MPU.
 RxD - Receive Data Input : Bits are received serially on this line
& converted into a parallel byte in the receiver input register.
 RxC - Receiver Clock Input : Clock signal that controls the rate at which
bits are received by the USART.
 5. Modem Control
The Pin Diagram of 8251 Microcontroller has a set of control inputs and outputs that
can be used to simplify the interface to almost MODEM. The MODEM control unit
allows to interface a MODEM to 8251 and to establish data communication though
MODEM over telephone lines. This unit take care of handshaking signals for MODEM
interface.

 DSR (Data Set Ready) : Checks if the Data Set is ready when communicating with a
modem.
 DTR (Data Terminal Ready) : Indicates that the device is ready to accept data when
the 8251 is communicating with a modem
 RTS (Request to Send ) : Low signal indicates the modem that the receiver is ready to
receive a data byte from the modem.
 CTS (Clear to Send) : A low on this input enables the 8251A to transmit serial data if
the TxE bit in the command byte is set to a “one”.
 Pin diagram of 8251
D0 – D7: This is an 8-bit bidirectional data bus used to read or write status,
command word or data from or to the 8251A
RD: This active-low input to 8251A is used to inform it that the CPU is reading
either data or status information from its internal registers
WR: . This active-low input to 8251A is used to inform it that the CPU is writing
data or control word to 8251A.
C / D: (Control Word/Data): This input pin, together with RD and WR inputs,
informs the 8251A that the word on the data bus is either a data or control
word/status information. If this pin is 1, control / status is on the bus, otherwise
data is on the bus.
CLK: This input is used to generate internal device timings and is normally
connected to clock generator output.
RESET: A high on this input forces the 8251A into an idle state.
CS : (Chip Select)When signal goes low, the 8251A is selected by the MPU for
communication.
 Pin diagram of 8251
• TxD-(Transmit Data):-This is an output line for transmitting serial bits
out on the falling edge of TxC, which transmitter clock.
• TxC-(Transmitter clock):-This input signal controls the rate at which the
bits are transmitted by the USART. In synchronous mode, the baud rate
will be the same as the frequency of TxC. In asynchronous mode, it is
possible to select the baud rate factor by mode instruction.
• TxRDY-transmitter Ready: This is the output signal. When it is high, it
indicates the buffer register is empty and USART is ready to accept a
byte. It can be used either to interrupt the MPU or to indicate the
status. This signal is reset when a data byte is loaded into the buffer.
• TxE-Transmitter Empty: This is an output signal. Logic 1 on this
indicates the output register is empty after transmitting all the
characters. This signal is reset when a byte is transferred from the
buffer to the output register.
 Pin diagram of 8251
• RxD-Receive Data: Bits are received serially on this line and
converted into a parallel byte in the receiver input register.
• RxC-Receiver clock: This is a clock signal that controls the
rate at which bits are received by the USART. In the
asynchronous mode, the clock can be set to 1,16 or 64
times the baud.
• RxRDY-Receiver Ready: This is an output signal. It goes high
when the USART has a character in the buffer register and is
ready to transfer into the MPU. This line can be used either
to indicate the status or to interrupt the MPU. When MPU
reads a data character, RxRDY will be reset by the leading
edge of RD signal.
 Pin Diagram of 8251
• SYNDET/BD (Input or output terminal)
• This pin is used in synchronous mode as SYNDET for detection of
synchronous characters and may be used as either input or output.
• When used as an input (external sync detect mode) a positive signal on
syndet/bd will cause the 8251A to start receiving data characters on the
rising edge of the next RXC.
• When used as output (internal sync detect mode) then syndet pin go high
to indicate that the 8251 has located the sync character.
• In asynchronous mode this pin goes high if receiver line stays low for more
than 2 character times. It then indicates a break in the data stream, so used
as BD.
8251 mode register
 7  6  5  4  3  2  1  0 Mode register

 Number of
 Baud Rate
 Parity enable
 Stop bits
 0: disable  00: Syn. Mode
 00: invalid  1: enable  01: x1 clock
 01: 1 bit  10: x16 clock
 10: 1.5 bits  Character length  11: x64 clock
 11: 2 bits
 00: 5 bits
 01: 6 bits
 Parity  10: 7 bits
 0: odd  11: 8 bits
 1: even
Serial Port
Stop bit 1: One stop bit is transmitted to indicate the end of a byte.
Stop bit 1.5: The stop bit is transferred for 150% of the normal time used to
transfer one bit.
Stop bit 2: Two stop bits are transmitted to indicate the end of a byte.
8251 command register
 EH  IR  RTS  ER  SBRK  RxE  DTR  TxE

 TxE: transmit enable

 DTR: data terminal ready
 RxE: receiver enable
 SBPRK: send break character
 ER: error reset
 RTS: request to send
 IR: internal reset
 EH: enter hunt mode
8251 status register
 DSR  SYNDET  FE  OE  PE  TxEMPTY  RxRDY  TxRDY

 TxRDY: transmit ready

 RxRDY: receiver ready
 TxEMPTY: transmitter empty
 PE: parity error
 OE: overrun error
 FE: framing error
 SYNDET: sync. character detected
 DSR: data set ready