5/2/2024

Project Title: Universal Asynchronous Transmitter

and Receiver using FPGA development board

Prepared by:
Khevana Purohit(92000133026)

Guided by:
Prof. Rakesh Oza

Department of Information and Communication Technology

Outline

• Project Overview
• Block diagram
• Flow chart
• UART explanation
• Terminologies
• Module explanation
• Board Overview
• Workflow
• Completion
• Conclusion
• References
Project Overview

• The purpose of this project is to implement the UART (Universal Asynchronous Receiver/Transmitter)
communication interface on the Nexys 4 FPGA board.

• UART communication allows for serial data transfer between the FPGA and external devices, enabling a wide
range of applications such as interfacing with sensors, microcontrollers, and other embedded systems.

• The expected outcomes are:

• Successful implementation of UART communication on the Nexys 4 FPGA.

• Reliable data transfer between the FPGA and external devices using UART.

• Demonstrated understanding of hardware description languages, FSM, clock management, and FPGA pin
configuration.
Block Diagram
Flow Chart
UART Protocol Overview

• UART stands for Universal Asynchronous Receiver Transmitter which is a serial communication interface
protocol. UART sends and receives data in the form of chunks or packets which are known as “transmission
characters”.
• There are two types of communications in UART, half duplex and full duplex communication. In a full duplex
communication, both ends can communicate with each other simultaneously. For example, Telephone; users at
both ends can speak and listen to each other simultaneously.
• Concerning UART, in full duplex communication one end can transmit as well as receive the bits.
• In a half-duplex system, both ends communicate with each other but one user at a time. For example, walkie-
talkie; in which one user speaks and another only listens and vice-versa. Half duplex is used to conserve
bandwidth. In UART at a time one end can be active either the transmitting or receiving end.
• In synchronous transmission, data is transmitted in form of packets or frames. Synchronous transmission follows
full-duplex type of communication. There is synchronization between the transmitter and the receiver. In
synchronous transmission, there is no gap between two data frames. It is more efficient and trustworthy to send
large data. The transmission is coordinated with one or more clock signals in synchronous transmission. In
asynchronous transmission, data is transmitted in form of byte or characters.
• Asynchronous transmission follows half duplex type of communication. Synchronization is not required. In this
transmission, start bit and stop bit is added to the data frame. Therefore, there is some gap between two data
frames. The transmission is coordinated with no clock signal, asynchronous transmission does not depend on any
clock signal.
Important terminologies and requirements

• Baud rate is defined as the number of signal units per second. Whereas the bit rate is the number of bits transmitted per second.
• The formula that relates both terms is given below:
• Bit rate = Baud rate x the number of bits per baud
• The tool required for the project is Vivado Design Suite and Nexys-4 development board.
• Top level diagram of UART is:
Continue

• The pin description for the project is described below.

• UART architecture consists of three main blocks Transmitter, Receiver and Baud rate generator.

• The data is taken from the computer or the peripheral devices. Below are the block level micro-
architecture and working of the modules.
Explanation of each module

• In the transmitter operation, all processes are synchronized with a clock running at multiple baud rates. The 8-bit parallel data is
initially loaded into the Transmitter Hold Register (THR) through the d_in pin. Once all the data is loaded into the THR, it is then
transferred in parallel to the Transmitter Shift Register (TSR), which has a size of 10 bits. In the TSR, a start bit is appended at the
beginning of the data frame, followed by the 8 data bits, and finally, a stop bit is added at the end of the frame.

• The TSR is responsible for converting the parallel data into a serial format. The data is transmitted bit by bit through the tx_out pin.
During the transmission, the least significant bit (LSB) of the data is sent first, followed by the remaining bits, and the transmission
concludes with the transmission of the stop bit. The clock provided to the transmitter block is the baud clock (bclk), which determines
the baud rate for the communication.

• To ensure proper transmission, a counter is employed within the TSR to keep track of the data bits being sent. Until all the data is
successfully transmitted, no new data can be loaded into the hold register. This process ensures a systematic and controlled
serialization of data for reliable communication.

• The transmitter Finite State Machine (FSM) comprises four states: Idle State, Start State, Data State, and Stop State.

• The transmitter FSM undergoes state transitions based on the detection of start and stop bits. It ensures a controlled and accurate
sequence of operations for serial data transmission.

• The FSM is designed to handle valid inputs, respond to errors, and facilitate the continuous transmission of data as per the specified
frame sequence.
Continue

• The receiver module operates at a speed four times faster than the transmitter and receives serial data via the rx_data pin,
processing one bit at a time. The initiation of a data frame is indicated by a transition from logic 1 to logic 0 on the rx_data pin.
The start bit is identified by a change from a high to a low level, and the stop bit is identified by a change from a low to a high
level.

• Upon detecting the start bit, the receiver employs a bit counter synchronized with positive clock edges to sample and count the
data bits. The counter increments with each rising clock edge, counting up to 8 to indicate the reception of all bits. The received
data is then stored in an 8-bit Receiver Shift Register (RSR), where the data bits are converted into parallel form.

• Subsequently, the parallel data is transferred to the Receiver Hold Register (RHR), an 8-bit register. The RSR selectively
transmits only the data bits to the RHR, excluding the start and stop bits. Finally, the parallel data stored in the RHR is sent to
the data bus or peripheral device for further processing. The receiver's intricate process ensures accurate reception,
parallelization of data, and transmission to the designated destination.

• The receiver Finite State Machine (FSM) shares the same four states as the transmitter: Idle State, Start State, Data State, and
Stop State.

• Both the transmitter and receiver operate as Mealy machines, where the output depends on both the current state and the input.
Output changes occur whenever there is a change in either the state or the input. This design ensures a dynamic response to
input conditions, enabling accurate and controlled communication between the transmitter and receiver in the UART
implementation.
Continue

• The baud rate generator plays a crucial role in dividing the frequency to match the desired baud rate for UART communication.
It takes the system clock, typically 50 MHz in our project, as its input. The process involves dividing the clock frequency by 8
using a clock divider, ensuring data bits are sampled at the positive edge of the clock.

• A parameterized counter is then employed to count the data bits, running on the divided clock. The counter's output is divided
into various divisors corresponding to different baud rates. The divisor is calculated using the formula:

• Divisor = sys. Clock / (8 x baud rate)​

• To determine the appropriate baud rate, a specific value is chosen from a 4x1 multiplexer based on select lines. The output of
this multiplexer is then directed to both the transmitter and receiver modules, allowing them to operate at the selected baud rate.
Notably, the receiver baud clock is 8 times faster than the transmitter baud clock.

• To achieve this speed difference, the multiplexer's output is initially fed into a "divide by 8" block. Subsequently, the divided
output is connected to the transmitter block. Simultaneously, the original output of the multiplexer is directly linked to the
receiver, ensuring the required variation in clock speeds between the transmitter and receiver in the UART communication
system.
Board Overview

• The Nexys 4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable
Gate Array (FPGA) from Xilinx. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external
memories, and collection of USB, Ethernet, and other ports, the Nexys 4 can host designs ranging from introductory combinational
circuits to powerful embedded processors.

• Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and a lot
of I/O devices allow the Nexys 4 to be used for a wide range of designs without needing any other components.

• The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than
earlier designs.

• Artix-7 100T features include:

• 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops
• 4,860 Kbits of fast block RAM
• Six clock management tiles, each with phase-locked loop (PLL)
• 240 DSP slices
• Internal clock speeds exceeding 450MHz
• On-chip analog-to-digital converter (XADC)
Workflow

• The Vivado Project consists of the following processes:

• Generate the .v file that is Verilog code.

• Change the constraints file that is the file with extension. xdc.

• This file is used for pin configurations.

• Now, once the pins are configured we can start simulation, synthesis, and implementation.

• In synthesis we are going to generate the debug probes file.

• Then after all these processes we will be able to generate the bitstream that is .bit file.

• After that we will be able to open the hardware manager and upload these bitstream file and debug probes file.

• The last step is to debug and test.

• These are the common steps for all the modules of this project.
Work completed

• In the initial steps of the project after the literature survey I implemented the slow clock that is configured my Nexys4 clock using the
Blink-led Verilog code.

• In this step I have generated the clock using the clock frequency 100MHz.

• The wave will be generated 0-50MHz and 50MHz to 0.

• I have also completed an important module called debouncing pushbutton as I will be using the pushbuttons in my project.

• I have also understood the 3 main modules of my project which are transmitter, Receiver and baud Rate generation and have tried to
write the codes for them.

• The next work is to successfully generate pin configurations and implement everything on the board.
Conclusion

• This project aims to fulfill the serial communication using the baud rate generation.

• I have tried to use the Nexys4 FPGA development board because the Artix 7 series of Xilinx is suitable FPGA part for the protocol
implementation.

• The series is user-friendly and even incorporates the higher suitable standards of the implementation.

• Its speed and reliability are the main advantages that I have used to fulfill the requirements of my project.

• In the later stages I will try to make the project fulfill the adaptive baud rate requirements in Serial communication.
References

1. Design and Implementation of UART Using FPGA Board by Anchal Govil, Anmol Karnwal, Govinda Sindhu, Ayush Singh, Dr.
Shubham Shukla, KIET Group of Institution and Guide- Sir (Assistant Professor)

2. PIC32MX Family Reference Manual by Microchip

3. Nexys FPGA Board Reference manual by Diligent

4. Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector by D.
Haripriya ,Keshav Kumar, Anurag Shrivastava, Hamza Mohammed Ridha Al-Khafaji, Vishal Moyal, and Sitesh Kumar Singh

5. Basics of UART Communication From Circuit Basics

6. UART Implementation using FPGA by Mukul Lokhande and Rohit Prabhakar Mate Shri Guru Gobind Singhji Institute of Engineering
and Technology

7. 7 Series FPGAs Configuration User Guide by Xilinx