COMPUTER ORGANIZATION

COURSE: CYBER SECURITY

I/O Organisation
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 BUS

• Interconnection network used to transfer data among the processor, memory, and I/O
devices is known as BUS.
• Only one source/destination pair of units can use this bus to transfer data at any one
time.

• Each I/O device is assigned a unique set of addresses for the registers in its interface.
• Address on the address lines, it is examined by the address decoders of all IO devices
and matched device will respond based on the control signal
• When I/O devices and the memory share the same address space, the arrangement is
called memory-mapped I/O
• Instructions for memory operations can be applied to IO operations too
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 Bus Operation
• A bus requires a set of rules, called a bus protocol, to govern how the bus is used
by various devices.
• The bus protocol determines when a device may place information on the bus,
when it may load the data on the bus and into one of its registers, and so on.
• There are two key bus protocols ie Synchronous and Asynchronous.
• These rules are implemented by control signals that indicate what and when
actions are to be taken.
• Typical Control signals are
• R/W bit Normally labelled as
• When several data sizes are possible, such as byte, halfword, or word, the required
size is indicated by other control lines
• Timing information. They specify the times at which the processor and the I/O
devices may place data on or receive data from the data lines.
• In any data transfer operation, one device plays the role of a master.
• Master initiates data transfers by issuing Read or Write commands on the bus.
Normally, the processor acts as the master, but other devices may also become
masters.
• The device addressed by the master is referred to as a slave.
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https://www.youtube.com/watch?v=TgYAj7mlRT8

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 Timing Schemes
• Synchronous
• all devices get timing information from a control line called the bus clock
• Clock signal has two phases: a high level followed by a low level. The two
phases constitute a clock cycle. The first half of the cycle between the low-to-
high and high-to-low transitions is often referred to as a clock pulse.

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Consider the sequence of signal events during an input (Read) operation.
• At time t0, the master places the device address on the address lines and sends a command on the control
lines indicating a Read operation.
• Information travels over the bus at a speed determined by its physical and electrical characteristics.
• The clock pulse width, t1 − t0, must be longer than the maximum propagation delay over the bus and it
must be long enough to allow all devices to decode the address and control signals, so that the addressed
device (the slave) can respond at time t1 by placing the requested input data on the data lines.
• At the end of the clock cycle, at time t1, the master loads the data on the data lines into one of its
registers.
• To be loaded correctly into a register, data must be available for a period greater than the setup time of
the register. Hence, the period t2 − t1 must be greater than the maximum propagation time on the bus plus
the setup time of the master’s register.
• This is a theoretical simplified representation.
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Advantages.
• This bus protocol results in a simple design for the I/O interface.
Disadvantages
• Since the data transfer has to be completed in one clock cycle, t2-t0 must be long enough to
accommodate all data transfer delays and slowest I/O interface. This forces all devices to operate at
the speed of the slowest device.
• Processor or master has no confirmation to say that the slave has completed its action at the end of
clock cycle. Hence in case of a I/O malfunction, there is no way to detect errors.
• How to overcome the disadvantages
• Incorporate “Slave_Ready” signal to inform master

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Input transfer with multiple clock
cycles and “Salve-ready” signal

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 “Slave-ready” signal

• This signal is an acknowledgment from the slave to the master.

• Confirms that the requested data have been placed on the bus.
• It also allows the duration of a bus transfer to change from one
device to another.
• In the previous timing diagram, the slave responds in cycle 3.
• A different device may respond in an earlier or a later cycle.
• If the addressed device does not respond at all, the master waits
for some predefined maximum number of clock cycles, then
aborts the operation.
• This could be the result of an incorrect address or a device
malfunction

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 Timing Schemes
• Asynchronous
• An alternative scheme for controlling data transfers on a bus is based on the use
of a handshake protocol between the master and the slave.
• Handshake is an exchange of command and response signals.
• It is a generalization of the “Slave-ready” signal used in previous slide
• Below diagram depicts the sequence of signals in this “full handshake” protocol
• It does not use a clock signal

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 Timing Schemes
A data transfer controlled by a handshake protocol proceeds as follows.
1. The master places the address and command information on the bus.
2. Then it indicates to all devices that it has done so by activating the Master-ready line.
3. This causes all devices to decode the address.
4. The selected slave performs the required operation and informs the processor that it has
done so by activating the Slave-ready line.
5. The master waits for Slave-ready to become asserted before it removes its signals from
the bus.
6. In the case of a Read operation, it also loads the data into one of its registers

https://www.youtube.com/
watch?v=VSoqiGwCd-
Q&t=2s

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Handshake Protocol in Output Operation

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 Commercial Implementations of
Handshake Protocol

Many variations of the bus handshake protocols are found in

commercial computers.
The choice of a particular design involves factors such as:
• Simplicity of the device interface
• Ability to accommodate device interfaces that introduce
different amounts of delay
• Total time required for a bus transfer
• Ability to detect errors resulting from addressing a nonexistent
device or from an interface malfunction

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 Comparison of Synchronous and Asynchronous
Bus
Synchronous
Clock signal is used to coordinate data
transfer
When a clock signal is used, complex
circuitry is need to ensure reach of clock
signal almost simultaneously to all devices.
Clock timing Delays introduced in IO
interfaces and propagation delays
Speeds of devices should be within a certain
range for efficient operation.
On synchronous buses, the clock period
need only accommodate one round trip
delay. Hence, faster transfer rates can
be achieved. Most of today’s high-speed
buses use the synchronous approach.
Asynchronous
Handshake protocol eliminates the need for
clock.
This simplifies the timing circuit design.
Delays introduced are accommodated in the
protocol
Can introduce devices of different speeds
The rate of data transfer on asynchronous
bus controlled by the handshake protocol is
limited by the fact that each transfer
involves two round-trip delays (four end-to-
end delays.
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 Bus Arbitration

• Arbitration is needed when two devices need to access a slave

at the same time
• Eg. When the printer wants to send its ready signal to screen, &
Keyboard wants to display a text typed.
• In such a situation, to avoid a deadlock, decision has to be made
to on who gets the slave access first.
• Decision is usually made in an arbitration process using arbiter
circuit.
• The arbitration process starts by each device sending a request
to use the shared resource.
• In bus arbitration, shared resource become the system bus.
• The arbiter associates priorities with individual requests.
• If it receives two requests at the same time, it grants the use of
the slave to the device having the higher priority first.
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 Bus Arbitration

• Two masters (Master1 and Master 2) sending Bus Request

signals to Arbiter circuit which decides the priority if the two
request happen at the same time.
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Bus Arbitration with 3 bus masters

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 Exercise: Draw the BG timing diagrams for
each of the following BR signals.

Time
BR1

BG1

BR2

BG2

BR3

BG3

Assume priority R1>R2>R3

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 I/O Organisation
• One of the main functional units of computer
• Computers I/O architecture is its interface to the outside world.
• It provides a systematic means of controlling external interactions.

• Input/Output Problems

• Wide variety of peripherals

• Delivering different amounts of data at different speeds
• In different formats
• Almost all are slower than CPU and RAM

• Need I/O modules to

• Interface to CPU and Memory
• Interface to one or more peripherals

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 Generic Model of I/O Module

I/O devices are

connected to
system via I/O
module

Question- Name few IO modules in a laptop/PC 20

 Types of IO devices

• Human readable
—Screen, printer, keyboard, Mouse
• Machine readable
—Monitoring and control (Bar code reader)
• Communication
—Modem
—Network Interface Card (NIC)

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External Device Block Diagram

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 I/O Module Functions

•Control & Timing

•CPU Communication
•Device Communication
•Data Buffering
•Error Detection

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 Steps when CPU wants to get data
from I/O module

•CPU checks I/O module device status

•I/O module returns status
•If ready, CPU requests data transfer
•I/O module gets data from device
•I/O module transfers data to CPU
•Variations for output, DMA, etc.

Ref. Course Text

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IO Module Diagram

Port

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 Types of Ports

Serial Ports
• Sends and receives data one bit at a time

Parallel Ports
• transfers multiple bits of data simultaneously to or from the device

Whilst I/O devices connect serially or parallelly, other end of IO module

which connect to the system bus the same way

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 Main functions of IO module/interface

1. Provides a register for temporary storage of data

2. Includes a status register containing status information that can be
accessed by the processor
3. Includes a control register that holds the information governing the
behavior of the interface
4. Contains address-decoding circuitry to determine when it is being
addressed by the processor
5. Generates the required timing signals
6. Performs any format conversion that may be necessary to transfer
data between the processor and the I/O device, such as parallel-to-
serial conversion in the case of a serial port

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 Example Input Parallel Interface

The output of the encoder consists of one byte of data representing the
encoded character and one control signal called Valid. When a key is pressed, the Valid
signal changes from 0 to 1, causing the ASCII code of the corresponding character to be
loaded into the KBD_DATA register and the status flag KBD_STATUS to be set to 1. The status flag is
cleared to 0 when the processor reads the contents of theKBD_DATA register.

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 Example Output Parallel Interface

Assumed that the display uses two handshake signals, New-data and Ready,
When the display is ready to accept a character,
it asserts its Ready signal, which causes the DOUT flag in the DISP_STATUS register to be
set to 1.
When the I/O routine checks DOUT and finds it equal to 1, it sends a character to
DISP_DATA. This clears the DOUTflag to 0 the New-data signal to 1. In response,
the display returns Ready to 0 and accepts and displays the character in DISP_DATA. When it
is ready to receive another character, it asserts Ready again, and the cycle repeats
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Serial Interface

Data are transferred in a bit-serial

fashion on the device side and in a bit-
parallel fashion on the processor side.
The transformation between the
parallel and serial formats
is achieved with shift registers that
have parallel access capability.
A block diagram of a typical serial
interface is shown.

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 Interconnection Standards

• USB
• Fire-wire
• PCI bus
• SCSI bus

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 Input Output Techniques

•Programmed
•Interrupt driven
•Direct Memory Access (DMA)

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 Input Output Techniques

•Programmed
•Interrupt driven
•Direct Memory Access (DMA)

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 Input Output Techniques

•Programmed
•Interrupt driven
•Direct Memory Access (DMA)

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 Suggested References

https://www.youtube.com/watch?v=TgYAj7mlRT8

https://www.youtube.com/watch?v=Yp_3OrDhUkQ

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THANK YOU

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