XILINX ISE 9.1/9.

2
By courtesy of Xilinx

EEP201: Digital Electronics Indian Institute of Technology, Delhi

FPGA Environment

How to start an FPGA project? How to describe logic circuit using schematic? How to simulate and check for errors?

simulation

Source Pane

Editor Pane

Process Pane

Transcript Pane

CONTINUE.

SELECT SCHEMATIC

USEFUL S M!OLS

ADD WIRE I/O MARKER

HALF A""E# SCHEMATIC

HALF A""E# SCHEMATIC

ATT#I!UTE THE IO MA#$E#

HALF A""E# SCHEMATIC

CHEC$ SCHEMATIC

FIN" TOOL OPTION F#OM MAIN MENU

Tools > Symbol Wizard

C#EATING A MAC#O

PIN POSITION

CONTINUE %ITH MAC#O

MAC#O LOO$S LI$E THIS

HERE WE ARE CREATING A NEW SCHEMATIC

& !IT #IPPLE A""E#

"EFINING THE SIGNALS' T!

"EFINE INPUT TEST PATTE#N

SA(E TEST !ENCH

PRESS THE PROCESS TAB

DOUBLE CLICK SIMULATE BEHAVIOUR MODEL

SIMULATION #ESULTS

#e)eren*e+ '

http://ece-www.colorado.edu/~ecen3100/lab/9.1_ http://ece-www.colorado.edu/~ecen3100/lab/9.1_