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Introduction To Cmos Vlsi Design: David Harris
Introduction To Cmos Vlsi Design: David Harris
Outline
q Memory Arrays q SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports q Serial Access Memories
13: SRAM
Slide 2
Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Queues
Shift Registers
Mask ROM
Flash ROM
13: SRAM
Slide 3
Array Architecture
q 2n words of 2m bits each q If n >> m, fold by 2k into fewer rows of more columns
wordlines bitline conditioning bitlines row decoder memory cells: 2n-k rows x 2m+k columns
q Good regularity easy to design q Very high density if good cells are used
13: SRAM CMOS VLSI Design Slide 4
13: SRAM
Slide 5
6T SRAM Cell
q Cell size accounts for most of array size Reduce cell size at expense of complexity q 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters q Read: bit Precharge bit, bit_b word Raise wordline q Write: Drive data onto bit, bit_b Raise wordline
13: SRAM CMOS VLSI Design
bit_b
Slide 6
SRAM Read
Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly q Read stability A must not flip
bit bit_b word N2 P1 P2 N4 A A_b N1 N3
A_b bit_b
1.5 1.0
q q q q
word
bit
0.5
A
0.0 0 100 200 300 time (ps) 400 500 600
13: SRAM
Slide 7
SRAM Read
Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly q Read stability A must not flip N1 >> N2
bit bit_b word N2 P1 P2 N4 A A_b N1 N3
A_b bit_b
1.5 1.0
q q q q
word
bit
0.5
A
0.0 0 100 200 300 time (ps) 400 500 600
13: SRAM
Slide 8
SRAM Write
Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high q Writability Must overpower feedback inverter q q q q
bit_b
N4
A_b
1.5
A bit_b
1.0
0.5
word
0.0 0 100 200 300 400 500 600 700 time (ps)
13: SRAM
Slide 9
SRAM Write
Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high q Writability Must overpower feedback inverter N2 >> P1 q q q q
bit_b
N4
A_b
1.5
A bit_b
1.0
0.5
word
0.0 0 100 200 300 400 500 600 700 time (ps)
13: SRAM
Slide 10
SRAM Sizing
q High bitlines must not overpower inverters during reads q But low bitlines must write new value into cell
bit word weak med A strong A_b med bit_b
13: SRAM
Slide 11
Write
Bitline Conditioning 2 More Cells word_q1
bit_b_v1f
bit_b_v1f
bit_v1f H
bit_v1f
SRAM Cell
SRAM Cell
H out_v1r
write_q1
data_s1
13: SRAM
Slide 12
SRAM Layout
q Cell size is critical q Tile cells sharing VDD, GND, bitline contacts
GND VDD
WORD
Cell boundary
13: SRAM
Slide 13
Decoders
q n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS
A1 A0 A1
Pseudo-nMOS
A0
1 1 1
8 4
word0
word
1/2 A0 A1 1 1
4 2
16 8
word
13: SRAM
Slide 14
Decoder Layout
q Decoders must be pitch-matched to SRAM cell Requires very skinny gates
A3 VDD A3 A2 A2 A1 A1 A0 A0
word
13: SRAM
Slide 15
Large Decoders
q For n > 4, NAND gates become slow Break large gates into multiple smaller gates
A3 A2 A1 A0
word0
word1
word2
word3
word15
13: SRAM
Slide 16
Predecoding
q Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort
A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1
word2 word3
word15
13: SRAM
Slide 17
Column Circuitry
q Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing
13: SRAM
Slide 18
Bitline Conditioning
q Precharge bitlines high before reads
bit bit_b
13: SRAM
Slide 19
Sense Amplifiers
q Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline q tpd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) q Sense amplifiers are triggered on small voltage swing (reduce V)
13: SRAM CMOS VLSI Design Slide 20
sense_b bit
P1 N1
P2 N2 N3 sense bit_b
13: SRAM
Slide 21
regenerative feedback
sense
sense_b
13: SRAM
Slide 22
Twisted Bitlines
q Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
13: SRAM
Slide 23
Column Multiplexing
q Recall that array may be folded for good aspect ratio q Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers
13: SRAM
Slide 24
13: SRAM
Slide 25
B0 B1
B2 B3
13: SRAM
Slide 26
A0 A0 write0_q1 2 write1_q1
data_v1
13: SRAM
Slide 27
Multiple Ports
q We have considered single-ported SRAM One read or one write on each cycle q Multiported SRAM are needed for register files q Examples: Multicycle MIPS must read two sources or write a result on some cycles Pipelined MIPS must read two sources and write a third result each cycle Superscalar MIPS must read and write many sources and results each cycle
13: SRAM CMOS VLSI Design Slide 28
Dual-Ported SRAM
q Simple dual-ported SRAM Two independent single-ended reads Or one differential write
bit wordA wordB bit_b
q Do two reads and one write by time multiplexing Read during ph1, write during ph2
13: SRAM CMOS VLSI Design Slide 29
Multi-Ported SRAM
q Adding more access transistors hurts read stability q Multiported SRAM isolates reads from state node q Single-ended design minimizes number of bitlines
bA bB bC wordA wordB wordC wordD wordE wordF wordG bD bE bF bG
write circuits
read circuits
13: SRAM
Slide 30
13: SRAM
Slide 31
Shift Register
q Shift registers store and delay data q Simple design: cascade of registers Watch your hold times!
clk Din 8 Dout
13: SRAM
Slide 32
00...00 11...11
Dout
CMOS VLSI Design Slide 33
13: SRAM
delay4
delay3
delay2
delay1
delay0
13: SRAM
Slide 34
clk Sin P0 P1 P2 P3
13: SRAM
Slide 35
P0 shift/load clk
P1
P2
P3
Sout
13: SRAM
Slide 36
Queues
q Queues allow data to be read and written at different rates. q Read and write each use their own clock, data q Queue indicates whether it is full or empty q Build with SRAM and read/write counters (pointers)
13: SRAM
Slide 37
13: SRAM
Slide 38