SEMICONDUCTOR TECHNICAL DATA


 
L SUFFIX
CERAMIC
CASE 620

The MC14017B is a fivestage Johnson decade counter with builtin code

converter. High speed operation and spikefree outputs are obtained by use
of a Johnson decade counter design. The ten decoded outputs are normally
low, and go high only at their appropriate decimal time period. The output
changes occur on the positivegoing edge of the clock pulse. This part can
be used in frequency division applications as well as decade counter or
decimal decode display applications.

Fully Static Operation

DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
DividebyN Counting
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4017B
Triple Diode Protection on All Inputs

D SUFFIX
SOIC
CASE 751B

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol

Parameter

VDD

DC Supply Voltage

Value

Unit

0.5 to + 18.0

Vin, Vout

Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

lin, lout

Input or Output Current (DC or Transient),

per Pin

10

mA

PD

Power Dissipation, per Package

500

mW

Tstg

Storage Temperature

65 to + 150

_C

260

_C

TL

Lead Temperature (8Second Soldering)

P SUFFIX
PLASTIC
CASE 648

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C To 125_C

ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Plastic
Ceramic
SOIC

TA = 55 to 125C for all packages.

FUNCTIONAL TRUTH TABLE

(Positive Logic)
Clock

Clock
Enable

0
X
X

X
1
X
0
X

X
1

Reset

Decode
Output=n

0
0
1
0
0
0
0

n
n
Q0
n+1
n
n
n+1

X = Dont Care. If n < 5 Carry = 1,

Otherwise = 0.

LOGIC DIAGRAM
Q5
1

Q1
2

Q7
6

Q3
7

Q9

BLOCK DIAGRAM

11

CLOCK 14
14
CLOCK
CLOCK
ENABLE
RESET

12
13
15

C
C
D
R

Q
R

C
D
R

Q
R

C
D
R

Q
R

C
D
R

Q
R

C
D
R

Q
R

CARRY

CLOCK
13
ENABLE

RESET 15

5
Q0

4
Q6

9
Q2

Cout

3
2
4
7
10
1
5
6
9
11
12

VDD = PIN 16
VSS = PIN 8

10
Q3

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9

Q4

REV 3
1/94

MC14017B
Motorola, Inc. 1995
74

MOTOROLA CMOS LOGIC DATA

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Output Voltage
Vin = VDD or 0

Symbol

55_C

25_C

125_C

VDD
Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

5.0
10
15

1.5
3.0
4.0

2.25
4.50
6.75

1.5
3.0
4.0

1.5
3.0
4.0

5.0
10
15

3.5
7.0
11

3.5
7.0
11

2.75
5.50
8.25

3.5
7.0
11

5.0
5.0
10
15

3.0
0.64
1.6
4.2

2.4
0.51
1.3
3.4

4.2
0.88
2.25
8.8

1.7
0.36
0.9
2.4

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

5.0
10
20

0.005
0.010
0.015

5.0
10
20

150
300
600

Adc

IT

5.0
10
15

Vin = 0 or VDD

Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL

1 Level

VIH

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

Output Drive Current

(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Vdc

Vdc

IOH

Source

Sink

Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

mAdc

IT = (0.27 A/kHz) f + IDD

IT = (0.55 A/kHz) f + IDD
IT = (0.83 A/kHz) f + IDD

Adc

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

** The formulas given are for the typical characteristics only at 25_C.
To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.0011.

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA

PIN ASSIGNMENT
Q5

16

VDD

Q1

15

RESET

Q0

14

CLOCK

Q2

13

CE

Q6

12

Cout

Q7

11

Q9

Q3

10

Q4

VSS

Q8

MC14017B
75

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic

Symbol

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,
tTHL

Propagation Delay Time

Reset to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns

tPLH,
tPHL

Propagation Delay Time

Clock to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

tPLH,
tPHL

Propagation Delay Time

Clock to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns

tPLH,
tPHL

TurnOff Delay Time

Reset to Cout
tPLH = (1.7 ns/pF) CL + 315 ns
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH = (0.5 ns/pF) CL + 100 ns

tPLH

Clock Pulse Width

VDD
Vdc

Min

Typ #

Max

5.0
10
15

100
50
40

200
100
80

Unit
ns

ns

5.0
10
15

500
230
175

1000
460
350

ns

5.0
10
15

400
175
125

800
350
250

ns

5.0
10
15

500
230
175

1000
460
350

ns

5.0
10
15

400
175
125

800
350
250

tw(H)

5.0
10
15

250
100
75

125
50
35

ns

fcl

5.0
10
15

5.0
12
16

2.0
5.0
6.7

MHz

Reset Pulse Width

tw(H)

5.0
10
15

500
250
190

250
125
95

ns

Reset Removal Time

trem

5.0
10
15

750
275
210

375
135
105

ns

Clock Input Rise and Fall Time

tTLH,
tTHL

5.0
10
15

tsu

5.0
10
15

350
150
115

175
75
52

ns

trem

5.0
10
15

420
200
140

260
100
70

ns

Clock Frequency

Clock Enable Setup Time

Clock Enable Removal Time

No Limit

* The formulas given are for the typical characteristics only at 25_C.
#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

MC14017B
76

MOTOROLA CMOS LOGIC DATA

VDD

VDD
VSS

A
B

Vout

CLOCK Q0
ENABLE
Q1
Q2
Q3
Q4
RESET Q5
Q6
Q7
Q8
Q9
CLOCK Cout

VSS

S1
S1

Output
Sink Drive

Output
Source Drive

Decode
Outputs

(S1 to A)

Clock to
desired
outputs
(S1 to B)

Carry

Clock to 5
thru 9
(S1 to B)

S1 to A

VGS =

VDD

VDD

VDS =

Vout

Vout VDD

ID

EXTERNAL
POWER
SUPPLY

VSS

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 F

0.01 F
CERAMIC

ID

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9

CLOCK
ENABLE
RESET
PULSE
GENERATOR

fc

CLOCK

Cout
VSS

CL

CL

CL

CL

CL

CL

CL

CL

CL

CL

CL

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).

RESET
CLOCK
CE MC14017B

RESET
CLOCK
CE MC14017B

Q0 Q1 Q8 Q9

Q0Q1 Q8 Q9

9 DECODED
OUTPUTS

8 DECODED
OUTPUTS

RESET
CLOCK
CE MC14017B
Q1 Q8 Q9

8 DECODED
OUTPUTS

CLOCK
FIRST STAGE

INTERMEDIATE STAGES

LAST STAGE

Figure 3. Counter Expansion

MOTOROLA CMOS LOGIC DATA

MC14017B
77

Pcp

Ncp

90%

CLOCK

50%

CLOCK
ENABLE
trem
RESET
20 ns
Q0

Q2

Q3

Q4

tsu

20 ns

20 ns

20 ns

20 ns

20 ns
tPLH

tPLH
tPHL
90%
10%
tPHL

tPLH

50%
tTHL

tTLH
tPHL

tPLH

VOH
V
OL
tTLH
VOH
VOL
VOH
VOL

tTHL

tTLH
tPHL

VOH
VOL

tPHL

tPLH

tTHL

tTLH
tTLH

Q5
tPLH
Q6

VDD
VSS

50%
tPLH

10%
tTHL
tPLH

tPHL
tTLH

tPHL
90%

VOH
VOL

tTHL

tTHL

Q8

tTHL
tPHL

VOH
VOL
VOH
VOL

tPLH
tTLH

tTHL
tPLH

tPHL

Q9
Cout

tPHL

VOH
VOL
VOH
VOL

Q7
tTHL

VDD
VSS
VDD
VSS

tPHL

tPLH
Q1

trem

10%

tTLH

tPLH

tPHL

tTHL

tTLH

tTHL

VOH
VOL
VOH
VOL

Figure 4. AC Measurement Definition and Functional Waveforms

MC14017B
78

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 62010
ISSUE V
A
16

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

B
C

DIM
A
B
C
D
E
F
G
H
K
L
M
N

T
K

SEATING
PLANE

E
F

G
D

16 PL

0.25 (0.010)

16 PL

0.25 (0.010)

T A

T B

INCHES
MIN
MAX
0.750
0.785
0.240
0.295

0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040

MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49

5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
16

S
T

SEATING
PLANE

H
G

16 PL

0.25 (0.010)

MOTOROLA CMOS LOGIC DATA

T A

DIM
A
B
C
D
F
G
H
J
K
L
M
S

INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040

MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01

MC14017B
79

OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
A

16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

B
1

8 PL

0.25 (0.010)

X 45 _

C
T

SEATING
PLANE

M
D

16 PL

0.25 (0.010)

T B

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MC14017B
80

*MC14017B/D*

MOTOROLA CMOS LOGIC

DATA
MC14017B/D