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GiaoTiep RS232
GiaoTiep RS232
Chng 4
Cc thit b ghp ni chia thnh 2 loi: DTE (Data Terminal Equipment) v DCE (Data Communication Equipment). DCE l cc thit b trung gian nh MODEM cn DTE l cc thit b tip nhn hay truyn d liu nh my tnh, PLC, vi iu khin, Vic trao i tn hiu thng thng qua 2 chn RxD (nhn) v TxD (truyn). Cc tn hiu cn li c chc nng h tr thit lp v iu khin qu trnh truyn, c gi l cc tn hiu bt tay (handshake). u im ca qu trnh truyn dng tn hiu bt tay l c th kim sot ng truyn. Tn hiu truyn theo chun RS-232 ca EIA (Electronics Industry Associations). Chun RS-232 quy nh mc logic 1 ng vi in p t -3V n -25V (mark), mc logic 0 ng vi in p t 3V n 25V (space) v c kh nng cung cp dng t 10 mA n 20 mA. Ngoi ra, tt c cc ng ra u c c tnh chng chp mch. Chun RS-232 cho php truyn tn hiu vi tc n 20.000 bps nhng nu cp truyn ngn c th ln n 115.200 bps. Cc phng thc ni gia DTE v DCE: - n cng (simplex connection): d liu ch c truyn theo 1 hng. - Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi thi im ch c truyn theo 1 hng. - Song cng (full-duplex): s liu c truyn ng thi theo 2 hng. nh dng ca khung truyn d liu theo chun RS-232 nh sau: Start 0 D0 D1 D2 D3 D4 D5 D6 D7 P Stop 1
Khi khng truyn d liu, ng truyn s trng thi mark (in p -10V). Khi bt u truyn, DTE s a ra xung Start (space: 10V) v sau ln lt truyn t D0 n D7
Phm Hng Kim Khnh Trang 75
Chng 4
v Parity, cui cng l xung Stop (mark: -10V) khi phc trng thi ng truyn. Dng tn hiu truyn m t nh sau (truyn k t A):
Hnh 4.1 Tn hiu truyn ca k t A Cc c tnh k thut ca chun RS-232 nh sau: Chiu di cable cc i Tc d liu cc i in p ng ra cc i in p ng ra c ti Tr khng ti in p ng vo nhy ng vo Tr khng ng vo 15m 20 Kbps 25V 5V n 15V 3K n 7K 15V 3V 3K n 7K
Cc tc truyn d liu thng dng trong cng ni tip l: 1200 bps, 4800 bps, 9600 bps v 19200 bps. S chn:
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Chng 4
Hnh 4.2 S chn cng ni tip Cng COM c hai dng: u ni DB25 (25 chn) v u ni DB9 (9 chn) m t nh hnh 4.2. ngha ca cc chn m t nh sau: D25 D9 1 2 3 4 5 6 7 8 20 22 23 24 15 17 18 21 14 16 19 13 12 25 9 10 11 3 2 7 8 6 5 1 4 9 Tn hiu TxD RxD RTS CTS DSR GND DCD DTR RI DSRD TSET TSET RSET LL RL STxD SRxD SRTS SCTS SDSRD TM Hng truyn DTE DCE DCE DTE DTE DCE DCE DTE DCE DTE DCE DTE DTE DCE DCE DTE DCE DTE DTE DCE DCE DTE DCE DTE DCE DTE DTE DCE DCE DTE DTE DCE DCE DTE DCE DTE M t Protected ground: ni t bo v Transmitted data: d liu truyn Received data: d liu nhn Request to send: DTE yu cu truyn d liu Clear to send: DCE sn sng nhn d liu Data set ready: DCE sn sng lm vic Ground: ni t (0V) Data carier detect: DCE pht hin sng mang Data terminal ready: DTE sn sng lm vic Ring indicator: bo chung Data signal rate detector: d tc truyn Transmit Signal Element Timing: tn hiu nh thi truyn i t DTE Transmitter Signal Element Timing: tn hiu nh thi truyn t DCE truyn d liu Receiver Signal Element Timing: tn hiu nh thi truyn t DCE truyn d liu Local Loopback: kim tra cng Remote Loopback: To ra bi DCE khi tn hiu nhn t DCE li Secondary Transmitted Data Secondary Received Data Secondary Request To Send Secondary Clear To Send Secondary Received Line Signal Detector Test Mode Dnh ring cho ch test Dnh ring cho ch test Khng dng
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Chng 4
Hnh 4.3 Kt ni n gin trong truyn thng ni tip Khi thc hin kt ni nh trn, qu trnh truyn phi bo m tc u pht v thu ging nhau. Khi c d liu n DTE, d liu ny s c a vo b m v to ngt. Ngoi ra, khi thc hin kt ni gia hai DTE, ta cn dng s sau:
TxD RxD GND RTS CTS DSR DCD DTR DTE1 TxD RxD GND RTS CTS DSR DCD DTR DTE2
Hnh 4.4 Kt ni trong truyn thng ni tip dng tn hiu bt tay Khi DTE1 cn truyn d liu th cho DTR tch cc tc ng ln DSR ca DTE2 cho bit sn sng nhn d liu v cho bit nhn c sng mang ca MODEM (o). Sau , DTE1 tch cc chn RTS tc ng n chn CTS ca DTE2 cho bit DTE1 c th nhn d liu. Khi thc hin kt ni gia DTE v DCE, do tc truyn khc nhau nn phi thc hin iu khin lu lng. Qu trinh iu khin ny c th thc hin bng phn mm hay phn cng. Qu trnh iu khin bng phn mm thc hin bng hai k t Xon v Xoff. K t Xon c DCE gi i khi rnh (c th nhn d liu). Nu DCE bn th s gi k t Xoff. Qu trnh iu khin bng phn cng dng hai chn RTS v CTS. Nu DTE mun truyn d liu th s gi RTS yu cu truyn, DCE nu c kh nng nhn d liu (ang rnh) th gi li CTS.
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Chng 4
Ngt 4 3 4 3
Giao tip ni tip trong my tnh s dng vi mch UART vi cc thanh ghi cho trong bng sau: Offset DLAB 0 0 0 1 0 1 1 2 3 4 5 6 7 R/W Tn Chc nng W THR Transmitter Holding Register (m truyn) R RBR Receiver Buffer Register (m thu) R/W BRDL Baud Rate Divisor Latch (s chia byte thp) R/W IER Interrupt Enable Register (cho php ngt) R/W BRDH S chia byte cao R IIR Interrupt Identification Register (nhn dng ngt) W FCR FIFO Control Register R/W LCR Line Control Register (iu khin ng dy) R/W MCR Modem Control Register (iu khin MODEM) R LSR Line Status Register (trng thi ng dy) R MSR Modem Status Register (trng thi MODEM) R/W Scratch Register (thanh ghi tm)
Cc thanh ghi ny c th truy xut trc tip kt hp vi a ch cng (v d nh thanh ghi cho php ngt ca COM1 c a ch l BACOM1 + 1 = 3F9h. IIR (Interrupt Identification): IIR xc nh mc u tin v ngun gc ca yu cu ngt m UART ang ch phc v. Khi cn x l ngt, CPU thc hin c cc bit tng ng xc nh ngun gc ca ngt. nh dng ca IIR nh sau: D7 D6 D5 D4 D3 D2 D1 00: khng c Cho php FIFO 64 1: ngt time-out Xc nh ngun FIFO byte (trong 16750) (trong 16550) gc ngt 11: cho php FIFO D0 0: c ngt 1: khng ngt
D2 D1 0 0 1 0 1 0 4 3 2
u tin
Ngun Li khung, thu , li parity, gin on khi thu m thu y m pht rng CTS, DSR, RI, RLSD
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