Nhp mn ARM Cortex M3 Lp c bn

BUI 6 : ADC DAC DMA 1 ADC

1.1. ADC l g?

2012

ADC (Analog-to-digital converter): l b chuyn i tn hiu dng tng t sang dng s. Qu trnh chuyn i gm 2 bc: ly mu v chuyn i. ADC c ng dng ph bin trong lnh vc o lng v iu khin, v d : c m bin nhit , m, p sut, nh sng 1.2. ADC ca STM32 B ADC trong STM32 c phn gii 12-bit, v c ti 18 knh tn hiu vo, trong 16 knh tn hiu ngoi v 2 knh tn hiu ni l cm bin nhit v in th. Cc tnh nng ca b ADC gm c: Hot ng 2 ch Single (Access line) hoc Dual (Performance) Tc chuyn i 1Mhz v phn gii 12-bit in p cung cp: t 2.4V n 3..6V Tn hiu u vo: VREF- VIN VREF+ H tr 18 knh tn hiu u vo gm c: + + 16 knh tn hiu ngoi 2 knh tn hiu ni : c m bin nhit v in th

H tr 2 nhm knh l Regular v Injected C 2 ch chuyn i single hoc continuous. Ch qut, c tn hiu tun t, v s dng cc ngun kch ngo i cho c hai nhm

knh Regular v Injected. C th ci t thi gian ly mu khc cho cc knh Canh l d liu v ch xt du +/- cho nhm knh Injected Ch Analog Watchdog Ch ngt c to ra sau khi kt thc qu trnh chuyn i (regular), kt thc qu trnh

injected hoc watchdog. Kt hp vi DMA lu d liu.

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Nhp mn ARM Cortex M3 Lp c bn

2012

ADC Regular conversion group H tr ti 16 knh. C th lp trnh thi gian ly mu (sample time) v th t ly mu cc knh. Qu trnh chuyn i c th bt u bng phn mm (start bit) hoc ngun kch ngoi. Interrupt/DMA xy ra khi kt thc qu trnh chuyn i. ADC Injected conversion group H tr ti 4 knh. C th lp trnh thi gian ly mu (sample time) v th t ly mu cc knh. Qu trnh chuyn i c th bt u bng: + Phn mm (Start bit) + T ng chuyn i khi nhm Regular thc hin xong (JAUTO) + Ngun kch ngoi C th iu chnh c im 0, xt du cho kt qu chuyn i. Interrupt/DMA xy ra khi kt thc qu trnh chuyn i.

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Nhp mn ARM Cortex M3 Lp c bn

ADC conversion mode Single & Continuous mode

2012

Analog sample time ADCCLK h tr ti a 14MHz v nhn clock t PCLK2 Thi gian l y mu cho mi knh:

Total conversion = Sample time + 12.5 cycles Vi clock 14MHz, thi gian l y mu 1.5cycles, total conversion time = 1s (14 cycles)

ADC data alignment 1 bit xc inh canh l data: tri hay phi Bit du m rng cho nhm knh Injected

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Nhp mn ARM Cortex M3 Lp c bn

ADC analog watchdog Analog watchdog vi 2 ngng high v low (12-bit). C th h tr cho 1 hoc ton b knh 2 nhm Regular v Injected. Interrupt c to ra khi 2 ngng high v low c pht hin.

2012

1.3. Cu hnh ADC trong STM32 Cu hnh Clock ngoi vi: /* Configure clocks for ADC and GPIO PORT */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

Cu hnh port IO /* Configure PA.01 (ADC Channel1) as analog input -----*/ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; GPIO_Init(GPIOA, &GPIO_InitStructure);

Cu hnh b ADC /* ADCx configuration -------------------------------------------*/ ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; ADC_InitStructure.ADC_ScanConvMode = DISABLE; Robotech INC ARM VN - STMicroelectronics Bui 6 - Page 4

Nhp mn ARM Cortex M3 Lp c bn

ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;

2012

ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; ADC_InitStructure.ADC_NbrOfChannel = 1; ADC_Init(ADC1, &ADC_InitStructure); /* ADC1 Regular Channel 1 Configuration */ ADC_RegularChannelConfig(ADC1,ADC_Channel_1,1,ADC_SampleTime_55Cycles5); /* Enable ADC1 */ ADC_Cmd(ADC1, ENABLE); /*Enable Vrefint channel enable temperature sensor for ADC module*/ ADC_TempSensorVrefintCmd(ENABLE); /* Enable ADC1 reset calibaration register */ ADC_ResetCalibration(ADC1); /* Check the end of ADC1 reset calibration register */ while(ADC_GetResetCalibrationStatus(ADC1)); /* Start ADC1 calibaration */ ADC_StartCalibration(ADC1); /* Check the end of ADC1 calibration */ while(ADC_GetCalibrationStatus(ADC1)); /* Start ADC1 Software Conversion */ ADC_SoftwareStartConvCmd(ADC1, ENABLE); c d liu t b ADC adc_value = ADC_GetConversionValue(ADC1); 1.4. Bi tp c tn hiu in th ti bin tr, s dng pin PA0.1 v hin th gi tr in th (s thp phn v nh phn) ln LCD.

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2 DAC
1.1. DAC l g?

2012

DAC (Digital-to-analog converter): l b chuyn i tn hiu dng s sang dng tng t, thng c ng dng trong lnh vc tiu dng. V d : audio player. Chuyn i s sang tng t l tin trnh ly mt gi tr c biu din di dng m s ( digital code ) v chuyn i n thnh mc in th hoc dng in t l vi gi tr s 1.2. DAC ca STM32 STM32 c 2 b DAC, v mi b c 1 knh output tng ng. Cc tnh nng ca b DAC gm c: D liu 12-bit, canh l tri hoc phi. Kh nng ng b update. Sinh ra tn hiu Noise-wave & triangular-wave. Dual DAC (Independent/simultaneous) H tr DMA cho mi knh H tr cc ngun kch ngoi in th tham chiu Vref+

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DAC data format: - Single mode

2012

Dual mode

DAC conversion: - D liu DAC khng th ghi trc tip vo thanh ghi DOR m phi np d liu vo thanh ghi DHR. D liu trong DHR s c t ng chuyn qua thanh ghi DOR trong 1 chu k APB1 clock, nu khng c ngun trigger no c kch hot, tuy nhin nu c ngun trigger c chn, s tn 3 chu k thc hin.

DAC output voltage:

DMA request: - Mi knh DAC u c kh nng s dng b DMA. 2 knh DMA s dng cho b DAC. Mt yu cu DAC DMA c to ra khi c mt ngun kch ngoi, gi tr ca thanh ghi

DHR s c chuyn qua thanh ghi DOR

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1.3. Cu hnh DAC ca STM32 Cu hnh Clock ngoi vi: /* GPIOA Periph clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); /* DAC Periph clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); Cu hnh port IO: GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; GPIO_Init(GPIOA, &GPIO_InitStructure);

2012

Cu hnh b DAC: /* DAC channel1 Configuration */ DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable; DAC_Init(DAC_Channel_1, &DAC_InitStructure); DAC_Cmd(DAC_Channel_1, ENABLE);

Set gi tr cho thanh ghi DHR: DAC_SetChannel1Data(DAC_Align_12b_R, DAC_data_output); 1.4. Bi tp c tn hiu in th ti bin tr t pin PA.1, v xut gi tr in th c c ra chn PA.4 (DAC channel 1). Hin th gi tr in th ln LCD. Dng VOM o gi tr in th xut ra ti chn PA.4 so snh.

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Nhp mn ARM Cortex M3 Lp c bn

3 DMA
1.1. DMA l g?

2012

DMA (Direct memory access): l mt c ch truyn d liu tc cao t ngoi vi ti b nh cng nh t b nh ti b nh. D liu c th c di chuyn mt cch nhanh chng m khng c n ti tc v t CPU, tit kim ti nguyn CPU cho cc hot ng khc. 1.2. DMA ca STM32 STM32 c 2 b DMA vi 12 knh (7 knh DMA1 v 5 knh DMA2), mi b qun l vic truy cp b nh t mt hoc nhiu ngoi vi. DMA cng c chc nng phn x u tin gia cc DMA request. - 12 knh DMA c lp, c th thit lp c. 7 knh DMA1 v 5 knh DMA2 Software trigger c h tr cho mi knh, v c lp trnh bi phn mm. u tin gia cc knh DMA c th lp trnh bi ph n mm (c 4 cp u tin l very

high, high, medium, low) hoc phn cng. Ph thuc vo kch thc gia ngun v ch (byte, half word, word). ac ch

ngun/ch ph i ph hp vi kch thc d liu. H tr truyn ti gia: + Memory to memory + Peripheral to memory + Memory to peripheral + Peripheral to peripheral C th truy cp vo Flash, Sram, APB1, APB2 v AHB nh ngun v ch. D liu truyn nhn h tr ti 65536.

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1.3. Cu hnh DMA DMA_InitTypeDef - DMA_BuferSize DMA_DIR + DMA_DIR_PeripheralDST + DMA_DIR_PeripheralSRC DMA_M2M + DMA_M2M_Disable + DMA_M2M_Enable DMA_MemoryBaseAddr DMA_MemoryDataSize + DMA_MemoryDataSize_Byte + DMA_MemoryDataSize_HalfWord + DMA_MemoryDataSize_Word DMA_MemoryInc + DMA_MemoryInc_Disable + DMA_MemoryInc_Enable DMA_Mode + DMA_Mode_Circular + DMA_Mode_Normal DMA_PeripheralBaseAddr DMA_PeripheralDataSize + DMA_PeripheralDataSize_Byte + DMA_PeripheralDataSize_HalfWord + DMA_PeripheralDataSize_Word DMA_PeripheralInc + DMA_PeripheralInc_Disable + DMA_PeripheralInc_Enable DMA_Priority + + + + DMA_Priority_High DMA_Priority_Low DMA_Priority_Medium DMA_Priority_VeryHigh

2012

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