Chapter3 LM4F120 BasicPeripheralProgramming

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BÙI QUỐC BẢO

ARM Processor families
BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 2

ARM Processor families

ARM-cortex M3
 Là vi điều khiển 32 bit.
 Cấu trúc Havard
 Công suất thấp.
 Chuyên dùng cho các ứng dụng nhúng.
 Giá rẻ
 Đáp ứng interrupt nhanh (low interrupt
latency).
 Chỉ hỗ trợ tập lệnh Thumb-2

Cấu trúc Von Neumann
Code và data chứa trong cùng không gian địa chỉ.
•Chỉ có 1 bus giao tiếp bộ nhớ.

•Tận dụng được không gian nhớ.
•Chương trình có thể thiết kế mềm dẻo hơn.
•Data có thể bị chép đè lên chương trình.
•Bị bottle neck trong quá trình truyền data và dữ liệu

Cấu trúc Harvard
Dùng 2 bus riêng để truy cập code và data
Code và data có thể nằm chung trong 1 không gian nhớ
Truycập code và data cùng lúc

Cho phép độ dài code và data khác nhau
Code không bị ghi đè bởi data
Phần cứng CPU phức tạp hơn

Pipeline
Cấu trúc pipeline cho phép một lệnh được

thực thi trong lúc nạp và giải mã các lệnh
khác.
Với cấu trúc này, một lệnh có thể được thực
thi trong 1 chu kỳ clock

ARM Cortex M3 block diagram

Tiva™ TM4C123G Microcontroller

M4 Core and Floating-Point Unit
 32-bit ARM® Cortex™-M4 core
 Thumb2 16/32-bit code: 26% less memory & 25 % faster than pure 32-bit
 System clock frequency up to 80 MHz
 100 DMIPS @ 80MHz
 Flexible clocking system
 Internal precision oscillator
 External main oscillator with PLL support
 Internal low frequency oscillator
 Real-time-clock through Hibernation module
 Saturated math for signal processing
 Atomic bit manipulation. Read-Modify-Write using bit-banding
 Single Cycle multiply and hardware divider
 Unaligned data access for more efficient memory usage
 IEEE754 compliant single-precision floating-point unit
 JTW and Serial Wire Debug debugger access
 ETM (Embedded Trace Macrocell) available through Keil and IAR emulators

TM4C123GH6PM Memory
256KB Flash memory

 Single-cycle to 40MHz
 Pre-fetch buffer and speculative branch improves
performance above 40 MHz
32KB single-cycle SRAM with bit-banding
Internal ROM loaded with TivaWare software
 Peripheral Driver Library
 Boot Loader 0x00000000 Flash
 Advanced Encryption Standard (AES) cryptography tables 0x01000000 ROM
 Cyclic Redundancy Check (CRC) error
detection functionality 0x20000000 SRAM
2KB EEPROM (fast, saves board space) 0x22000000 Bit-banded SRAM
 Wear-leveled 500K program/erase cycles
 Thirty-two 16-word blocks
0x40000000 Peripherals & EEPROM
 Can be bulk or block erased 0x42000000 Bit-banded Peripherals
 10 year data retention
0xE0000000 Instrumentation, ETM, etc.
 4 clock cycle read time
TM4C123GH6PM Peripherals
Battery-backed Hibernation Module

 Internal and external power control (through external voltage regulator)
 Separate real-time clock (RTC) and power source
 VDD3ON mode retains GPIO states and settings
 Wake on RTC or Wake pin
 Sixteen 32-bit words of battery backed memory
 5 µA Hibernate current with GPIO retention. 1.7 µA without
Serial Connectivity
 USB 2.0 (OTG/Host/Device)
 8 - UART with IrDA, 9-bit and ISO7816 support
 6 - I2C
 4 - SPI, Microwire or TI synchronous serial interfaces
 2 - CAN

Two 1MSPS 12-bit SAR ADCs
 Twelve shared inputs
 Single ended and differential measurement
 Internal temperature sensor
 4 programmable sample sequencers
 Flexible trigger control: SW, Timers, Analog comparators, GPIO
 VDDA/GNDA voltage reference
 Optional hardware averaging
 3 analog and 16 digital comparators
 µDMA enabled
0 - 43 GPIO
 Any GPIO can be an external edge or level triggered
interrupt
 Can initiate an ADC sample sequence or µDMA transfer
directly
 Toggle rate up to the CPU clock speed on the Advanced
High-Performance Bus
 5-V-tolerant in input configuration
(except for PB0/1 and USB data pins when configured as GPIO)
 Programmable Drive Strength (2, 4, 8 mA or 8 mA with slew rate control)
 Programmable weak pull-up, pull-down, and open drain

Memory Protection Unit (MPU)
 Generates a Memory Management Fault on incorrect access to region
Timers
 2 Watchdog timers with separate clocks
 SysTick timer. 24-bit high speed RTOS and other timer
 Six 32-bit and Six 64-bit general purpose timers
 PWM and CCP modes
 Daisy chaining
 User enabled stalling on CPU Halt flag from debugger for all timers
32 channel µDMA
 Basic, Ping-pong and scatter-gather modes
 Two priority levels
 8,16 and 32-bit data sizes
 Interrupt enabled

Nested-Vectored Interrupt Controller (NVIC)
 7 exceptions and 71 interrupts with 8 programmable priority levels
 Tail-chaining and other low-latency features
 Deterministic: always 12 cycles or 6 with tail-chaining
 Automatic system save and restore
Two Motion Control modules. Each with:

 8 high-resolution PWM outputs (4 pairs)
 H-bridge dead-band generators and hardware polarity control
 Fault input for low-latency shutdown
 Quadrature Encoder Inputs (QEI)
 Synchronization in and between the modules

Tiva™ EK-TM4C123GXL LaunchPad
 ARM® Cortex™-M4F
64-pin 80MHz TM4C123GH6PM
 On-board USB ICDI
(In-Circuit Debug Interface)
 Micro AB USB port
 Device/ICDI power switch
 BoosterPack XL pinout also supports
legacy BoosterPack pinout
 2 user pushbuttons
(SW2 is connected to the WAKE pin)
 Reset button
 3 user LEDs (1 tri-color device)
 Current measurement test points
 16MHz Main Oscillator crystal
 32kHz Real Time Clock crystal
 3.3V regulator
 Support for multiple IDEs:

Development Tools for Tiva C Series MCUs

Eval Kit 30-day full 32KB code size 32KB code size Full function.
License function. limited. limited. Onboard
Upgradeable Upgradeable Upgradeable emulation limited
Compiler GNU C/C++ IAR C/C++ RealView C/C++ TI C/C++
Debugger / C-SPY / CCS/Eclipse-

IDE gdb / Eclipse Embedded µVision based suite
Workbench
99 USD
personal MDK-Basic (256
Full Upgrade edition / 2700 USD KB) = €2000 445 USD
2800 USD (2895 USD)
full support
JTAG J-Link, 299 U-Link, 199 USD XDS100, 79 USD
Debugger USD

Cortex M4 Systick
System Bus Interface NVIC
GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
PC7
PC6
GPIO Port C GPIO Port D PD7
PD6
6 General-Purpose I/O
PC5
PC4
USB 2.0 Twelve
Timers
PD5
PD4
(GPIO) ports:
PC3/TDO/SWO PD3 • Four 8-bit ports (A, B,
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO
PC0/TCK/SWCLK
64-bit wide PD1
PD0
C, D)
• One 6-bit port (E)
GPIO Port E GPIO Port F • One 5-bit port (F)
PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0
Advanced High Performance Bus Advanced Peripheral Bus

System (CPU) Clock Sources
The CPU can be driven by any of the fundamental clocks …
 Internal 16 MHz
 Main
 Internal 30 kHz
 External Real-Time
- Plus -
 The internal PLL (400 MHz)
 The internal 16MHz oscillator divided by four (4MHz ± 3%)
Clock Source Drive PLL? Used as SysClk?

Internal 16MHz Yes Yes
Internal 16Mhz/4 No Yes
Main Oscillator Yes Yes
Internal 30 kHz No Yes
Hibernation Module No Yes
PLL - Yes
Tiva C Series Clock Tree
driverLib API SysCtlClockSet() selects:  SYSDIV divider setting

 OSC or PLL
 Main or Internal oscillator
 Crystal frequency
GPIO...
 I/O Pin Characteristics Set AFSEL to 0
 Can be employed as an n-bit parallel interface

 Pins also provide alternative functions:
 UART Universal asynchronous
receiver/transmitter
 SSI Synchronous serial interface
 I2C Inter-integrated circuit
 Timer Periodic interrupts, input capture, and
output compare
 PWM Pulse width modulation
 ADC Analog to digital converter, measure
analog signals
 Analog Compare two analog signals
Comparator
 QEI Quadrature encoderSet AFSEL to 1
interface
 USB Universal serial bus
 Ethernet High speed network
 CAN Controller
BM Kỹ Thuật Điện Tử area
- ĐH Bách Khoa network
TP.HCM 22
IO Ain 0 1 2 3 4 5 6 7 8 9 14
PA2 Port SSI0Clk
PA3 Port SSI0Fss
PA4 Port SSI0Rx
PA5 Port SSI0Tx
PA6 Port I2C1SCL M1PWM2
PA7 Port I2C1SDA M1PWM3
PB0 Port U1Rx T2CCP0
PB1 Port U1Tx T2CCP1
PB2 Port I2C0SCL T3CCP0
PB3 Port I2C0SDA T3CCP1
PB4 Ain10 Port SSI2Clk M0PWM2 T1CCP0 CAN0Rx
PB5 Ain11 Port SSI2Fss M0PWM3 T1CCP1 CAN0Tx
PB6 Port SSI2Rx M0PWM0 T0CCP0
PB7 Port SSI2Tx M0PWM1 T0CCP1
PC4 C1- Port U4Rx U1Rx M0PWM6 IDX1 WT0CCP0 U1RTS
PC5 C1+ Port U4Tx U1Tx M0PWM7 PhA1 WT0CCP1 U1CTS
PC6 C0+ Port U3Rx PhB1 WT1CCP0 USB0epen
PC7 C0- Port U3Tx WT1CCP1 USB0pflt
PD0 Ain7 Port SSI3Clk SSI1Clk I2C3SCL M0PWM6 M1PWM0 WT2CCP0
PD1 Ain6 Port SSI3Fss SSI1Fss I2C3SDA M0PWM7 M1PWM1 WT2CCP1
PD2 Ain5 Port SSI3Rx SSI1Rx M0Fault0 WT3CCP0 USB0epen
PD3 Ain4 Port SSI3Tx SSI1Tx IDX0 WT3CCP1 USB0pflt
PD6 Port U2Rx M0Fault0 PhA0 WT5CCP0
PD7 Port U2Tx PhB0 WT5CCP1 NMI
PE0 Ain3 Port U7Rx
PE1 Ain2 Port U7Tx
PE2 Ain1 Port
PE3 Ain0 Port
PE4 Ain9 Port U5Rx I2C2SCL M0PWM4 M1PWM2 CAN0Rx
PE5 Ain8 Port U5Tx I2C2SDA M0PWM5 M1PWM3 CAN0Tx
PF0 Port U1RTS SSI1Rx CAN0Rx M1PWM4 PhA0 T0CCP0 NMI C0o
PF1 Port U1CTS SSI1Tx M1PWM5 PhB0 T0CCP1 C1o TRD1
PF2 Port SSI1Clk M0Fault0 M1PWM6 T1CCP0 TRD0
PF3 Port SSI1Fss CAN0Tx M1PWM7 T1CCP1 TRCLK
PF4 Port M1Fault0 IDX0 T2CCP0 USB0epen 23
BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM
Read from port address
n n GPIO_PORTF_DATA_R
Processor
n n
DQ Input/Output Port
Write to port address GPIO_PORTF_DIR_R

Direction bits
n 1 means output
DQ 0 means input
Bus Write to port direction register
 Thanh ghi GPIO_PORTF_DIR_R , cấu hình

chân port la input hay output:
 0: input
 1: output

Address 7 6 5 4 3 2 1 0 Name
400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R
• Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGCGPIO_R
2. Wait two bus cycles (two NOP instructions)
3. Set DIR to 1 for output or 0 for input
4. Clear AFSEL bits to 0 to select regular I/O
5. Set DEN bits to 1 to enable data pins
• Input/output from pin
6. Read/write GPIO_PORTF_DATA_R

Address 7 6 5 4 3 2 1 0 Name
$400F.E608 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
$400F.EA08 GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_PRGPIO_R
$4005.8000 PORTA base address
$4005.9000 PORTB base address
$4005.A000 PORTC base address
$4005.B000 PORTD base address
$4005.C000 PORTE base address
$4005.D000 PORTF base address
base+$3FC DATA DATA DATA DATA DATA DATA DATA DATA GPIO_PORTx_DATA_R
base+$400 DIR DIR DIR DIR DIR DIR DIR DIR GPIO_PORTx_DIR_R
base+$420 AFSEL AFSEL AFSEL AFSEL AFSEL AFSEL AFSEL AFSEL GPIO_PORTx_AFSEL_R
base+$510 PUE PUE PUE PUE PUE PUE PUE PUE GPIO_PORTx_PUR_R
base+$51C DEN DEN DEN DEN DEN DEN DEN DEN GPIO_PORTx_DEN_R
base+$524 CR CR CR CR CR CR CR CR GPIO_PORTx_CR_R
base+$528 AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL AMSEL GPIO_PORTx_AMSEL_R
31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

base+$52C PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_PORTx_PCTL_R
base+$520 LOCK (32 bits) GPIO_PORTx_LOCK_R

negative – pressed = ‘0’ positive – pressed = ‘1’

+3.3V +3.3V
TM4C TM4C
10k
s Input port t Input port
10k
Negative logic Positive logic
Negative Logic s Positive Logic t

– pressed, 0V, false – pressed, 3.3V, true
– not pressed, 3.3V, true – not pressed, 0V, false
+3.3V +3.3V +3.3V +3.3V

TM4C TM4C TM4C TM4C
10k 10k
3.3V 0V
s Input port s Input port t Input port t Input port
0.0V 3.3V
10k 10k
Pressed Not pressed Pressed Not pressed

Current
high LM3S +3.3V
2 + a Out R
I I or 1mA
R 1mA TM4C
(mA) 1 - k LM3S LED
or
TM4C LED
voltage low
0 Out
1.5 1.6 1.7
V (volts)
(a) LED curve (b) Positive logic interface (c) Negative logic interface

R1 0
TM4C123 PF0
PF4
Serial PA1 R13 0 5V
PA0 Green
R29 Blue Red
+5 PB1
0
PD5 330 330 330
USB R12 SW1 SW2
R25 PD4 PF3
PB0 0
0
PD0 R11
R9 0
PB6 PF2
0
R10 0
PD1 R2 DTC114EET1G
PB7 PF1
0
 The switches on the LaunchPad
 Negative logic
 Require internal pull-up (set bits in PUR)
 The PF3-1 LEDs are positive logic

• Initialization (executed once at beginning)
1. Turn on Port F clock in SYSCTL_RCGCGPIO_R Wait two bus
cycles (two NOP)
2. Unlock PF0 (PD7 also needs unlocking)
3. Clear AMSEL to disable analog
4. Clear PCTL to select GPIO
5. Set DIR to 0 for input, 1 for output
6. Clear AFSEL bits to 0 to select regular I/O
7. Set PUE bits to 1 to enable internal pull-up
8. Set DEN bits to 1 to enable data pins
• Input from switches, output to LED
10. Read/write GPIO_PORTF_DATA_R

 I/O Port bit-specific
addressing is used to
access port data register
 Define address offset as
4*2b, where b is the
selected bit position
 256 possible bit Port F = 0x4002.5000
combinations (0-8)
0x4002.5000+0x0004+0x0040
 Add offsets for each bit = 0x4002.5044
selected to base address
for the port Provides friendly and atomic
 Example: PF4 and PF0 access to port pins

GPIO Address Masking
GPIO Port D (0x4005.8000)

The register we want to change is GPIO Port D (0x4005.8000) 0 00 11 101
Current contents of the register is:
Write Value (0xEB)
The value we will write is 0xEB:
11101 01 1
Instead of writing to GPIO Port D directly, write to

0x4005.8098. Bits 9:2 (shown here) become a bit-mask …0 0 0 0 0 1 0 0 1 1 0 0 0
for the value you write.
Only the bits marked as “1” in the bit-mask are

changed.
0 011101 1
New value in GPIO Port D (note
that only the red bits were written)
GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_1, 0xEB);

GPIOLOCK ...
GPIO Address Masking
 GPIOPinTypeGPIOOutput(GPIO_PORT
F_BASE, GPIO_PIN_3)
 GPIOPinWrite(GPIO_PORTF_BASE,
GPIO_PIN_3, 1 << 3)

Port Base address
PortA 0x40004000
PortB 0x40005000
PortC 0x40006000
PortD 0x40007000
PortE 0x40024000
PortF 0x40025000
#define PA5 (*((volatile unsigned long *)0x40004080))

//Để bật/xóa PA.5, ta ghi vào PA5. 7 bit còn lại không bị ảnh hưởng.
PA5 = 0x20; //bật PA5

Critical Function GPIO Protection
 Six pins on the device are protected against accidental
programming:
• PC3,2,1 & 0: JTAG/SWD
• PD7 & PF0: NMI
 Any write to the following registers for these pins will not be stored
unless the GPIOLOCK register has been unlocked:
• GPIO Alternate Function Select register
• GPIO Pull Up or Pull Down select registers
• GPIO Digital Enable register
 The following sequence will unlock the GPIOLOCK register for PF0
using direct register programming:
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;

HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= 0x01;
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = 0;
 Reading the GPIOLOCK register returns it to lock status
Lab...
External OSCSRC
crystal
Main BYPASS
Osc 00
Mux USESYSDIV
01 1
16 MHz
Internal Osc /4 10* * can't drive DIV400
Mux 0
30 kHz 11* the PLL
Mux
Internal Osc 1 0
Ref
Phase-Lock-Loop
/n 1
Clk Up Mux
Phase/
Freq Charge
Down Pump/ VCO /2 0 SYSDIV
Detector
LPF
400 MHz
/m 200 MHz
XTAL
 Bộ dao động nội giúp giảm giá thành, nhưng độ chính xác không cao
 LM4F120 được tích hợp bộ dao động 16 Mhz, tốc độ hoạt động tối đa là 80
MHz

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|
SYSCTL_XTAL_16MHZ| SYSCTL_OSC_MAIN);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF)

Example
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/sysctl.h"
#include "driverlib/gpio.h"
uint8_t ui8PinData=2;
int main(void)
{
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
while(1)
{
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3, ui8PinData);
SysCtlDelay(2000000);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0x00);
SysCtlDelay(2000000);
if(ui8PinData==8) {ui8PinData=2;} else {ui8PinData=ui8PinData*2;}
}
}

Nested Vectored Interrupt Controller (NVIC)
 Handles exceptions and interrupts
 8 programmable priority levels, priority grouping
 7 exceptions and 71 Interrupts
 Automatic state saving and restoring
 Automatic reading of the vector table entry
 Pre-emptive/Nested Interrupts
 Tail-chaining
 Deterministic: always 12 cycles or 6 with tail-chaining
Motor control ISRs (e.g. PWM, ADC)
Communication ISRs (e.g. CAN)
Main application (foreground)

t
Tail Chaining...
Interrupt Latency - Tail Chaining
Highest
Priority IRQ
1
IRQ
2
Typical processor PUSH ISR 1 POP PUSH ISR 2 POP
Tail-
chaining
Cortex-M4 PUSH ISR 1 ISR 2 POP
Interrupt handling in HW
12 6 12
Cycles Cycles Cycles

Interrupt Latency – Pre-emption
Highest
Priority IRQ1
IRQ2
Typical processor ISR 1 POP PUSH ISR 2 POP
Cortex-M4 ISR 1 POP ISR 2 POP

1- 6 12
12 Cycles
Cycles Cycles

Interrupt Latency – Late Arrival
Highest IRQ1
Priority
IRQ2
Typical processor PUSH PUSH ISR 1 POP PUSH ISR 2 POP
Cortex-M4 PUSH ISR 1 ISR 2 POP

6 12
Cycles Cycles

Cortex-M4® Interrupt Handling
Interrupt handling is automatic. No instruction overhead.
Entry
 Automatically pushes registers R0–R3, R12, LR, PSR, and PC onto the
stack
 In parallel, ISR is pre-fetched on the instruction bus. ISR ready to start
executing as soon as stack PUSH complete
Exit
 Processor state is automatically restored from the stack
 In parallel, interrupted instruction is pre-fetched ready for execution
upon completion of stack POP

Cortex-M4® Exception Types
Vector Exception Priority Vector Descriptions
Number Type address
1 Reset -3 0x04 Reset
2 NMI -2 0x08 Non-Maskable Interrupt
3 Hard Fault -1 0x0C Error during exception processing
4 Memory Programmable 0x10 MPU violation
Management
Fault
5 Bus Fault Programmable 0x14 Bus error (Prefetch or data abort)
6 Usage Fault Programmable 0x18 Exceptions due to program errors
7-10 Reserved - 0x1C - 0x28
11 SVCall Programmable 0x2C SVC instruction
12 Debug Monitor Programmable 0x30 Exception for debug
13 Reserved - 0x34
14 PendSV Programmable 0x38
15 SysTick Programmable 0x3C System Tick Timer
16 and above Interrupts Programmable 0x40 External interrupts (Peripherals)

Cortex-M4® Vector Table
 After reset, vector table is located at
address 0
 Each entry contains the address of the

function to be executed
 The value in address 0x00 is used as

starting address of the Main Stack
Pointer (MSP)
 Vector table can be relocated by writing

to the VTABLE register
(must be aligned on a 1KB boundary)
 Open startup_ccs.c to see vector table

coding

GPTM...
General Purpose Timer Module
 Six 16/32-bit and Six 32/64-bit general purpose timers
 Twelve 16/32-bit and Twelve 32/64-bit capture/compare/PWM pins
Timer modes:
• One-shot
• Periodic
• Input edge count or time capture with 16-bit prescaler
• PWM generation (separated only)
• Real-Time Clock (concatenated only)
Count up or down
Simple PWM (no deadband generation)
Support for timer synchronization, daisy-chains, and stalling during debugging
May trigger ADC samples or DMA transfers

Lab...
Timer interrupt example
#include <stdint.h>
#include "inc/tm4c123gh6pm.h"
#include "driverlib/interrupt.h"
#include "driverlib/timer.h"
int main(void)
{
uint32_t ui32Period;
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
ui32Period = (SysCtlClockGet() / 10) / 2;

TimerLoadSet(TIMER0_BASE, TIMER_A, ui32Period -1);
IntEnable(INT_TIMER0A);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
IntMasterEnable();
TimerEnable(TIMER0_BASE, TIMER_A);
while(1)
{
}
} 49
BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM
Timer interrupt example
void Timer0IntHandler(void)
{
// Clear the timer interrupt
TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
// Read the current state of the GPIO pin and

// write back the opposite state
if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_2))
{
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0);
}
else
{
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 4);
}
}

tm4c123gh6pm_startup_ccs.c

Systick Timer
Process Process Process Process
Systick Period
Address 31- 23- 16 15-3 2 1 0 Name

24 17
0xE000E010 0 0 COUNT 0 CLK_SRC INTEN ENABLE NVIC_ST_CTRL_R
0xE000E014 0 24-bit RELOAD value NVIC_ST_RELOAD_R
0xE000E018 0 24-bit CURRENT value of SysTick counter NVIC_ST_CURRENT_R
Address 31-29 28- 23-21 20-8 7-5 4-0 Name

24
0xE000ED20 TICK 0 PENDSV 0 DEBUG 0 NVIC_SYS_PRI3_R

 Timer/Counter operation
 24-bit counter decrements at bus clock
frequency
 With 50 MHz bus clock, decrements every 20 ns
 Counting is from n  0
 Setting n appropriately will make the counter a
modulo n+1 counter. That is:
 next_value = (current_value-1) mod (n+1)
 Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1…

 Các bước cấu hình SysTick Timer:
 Xóa ENABLE bit.
 Ghi giá trị nạp lại vào thanh ghi NVIC_ST_RELOAD_R. Nếu f là tần số xung
nhịp hệ thống, thì chu kỳ của Systick Timer sẽ là (NVIC_ST_RELOAD_R +1)/f.
 Cấu hình thanh ghi NVIC_ST_CTRL_R.
 Bit CLK_SRC: Bit này qui định nguồn xung nhịp cho Systick Timer.
 Nếu bằng 0, nguồn clock cho Systick Timer là xung nhịp 16 Mhz nội / 4
 Nếu bằng 1, nguồn clock cho Systick Timer là xung nhịp clock hệ thống
 Các nguồn xung nhịp có cấu trúc như ở Hình 5 ‑23.
 Bit INTEN:
 Bit này được set lên 1 để cho phép ngắt.
 Cấu hình mức ưu tiên của ngắt SysTick bằng cách ghi vào các bit TICK của
thanh ghi NVIC_SYS_PRI3_R.
 Set ENABLE bit để cho phép timer chạy.

#define NVIC_ST_CTRL_R(*((volatile unsigned long *)0xE000E010))
#define NVIC_ST_RELOAD_R(*((volatile unsigned long *)0xE000E014))
#define NVIC_ST_CURRENT_R(*((volatile unsigned long *)0xE000E018))
void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup
NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value
NVIC_ST_CURRENT_R = 0; // 3) any write to current clears it
NVIC_ST_CTRL_R = 0x00000005; // 4) enable SysTick with core clock
}
// The delay parameter is in units of the 50 MHz core clock(20 ns)
void SysTick_Wait(unsigned long delay){
unsigned long startTime = NVIC_ST_CURRENT_R;
while ((startTime-NVIC_ST_CURRENT_R)&0x00FFFFFF > Delay){}
}
// Call this routine to wait for delay*10ms
void SysTick_Wait10ms(unsigned long delay){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(500000); // wait 10ms
}

Systick interrupt handler
void
#include "inc/hw_types.h" SysTickIntHandler(void)
#include "driverlib/pin_map.h" {
#include "driverlib/systick.h"
//
#include "driverlib/interrupt.h" // Update the Systick interrupt counter.
#include "driverlib/sysctl.h" //
#include "driverlib/gpio.h" g_ulCounter++;
#include "utils/uartstdio.h" }
unsigned long g_ulCounter = 0;

Systick interrupt initialization
int
main(void)
unsigned long ulPrevCount = 0;
SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC
| SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
InitConsole();
UARTprintf("SysTick Firing Interrupt ->");
UARTprintf("\n Rate = 1sec\n\n");
g_ulCounter = 0;
SysTickPeriodSet(SysCtlClockGet());
IntMasterEnable();
SysTickIntEnable();
SysTickEnable();

Forever loop
while(1)
if(ulPrevCount != g_ulCounter)
UARTprintf("Number of interrupts:
%d\r",g_ulCounter);
ulPrevCount = g_ulCounter;

UART console initialization
void
InitConsole(void)
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 |
GPIO_PIN_1);
UARTStdioInit(0);

UART Features
 Separate 16x8 bit transmit and receive FIFOs
 Programmable baud rate generator
 Auto generation and stripping of start, stop, and parity bits
 Line break generation and detection
 Programmable serial interface
 5, 6, 7, or 8 data bits
 even, odd, stick, or no parity bits
 1 or 2 stop bits
 baud rate generation, from DC to processor clock/16
 Modem flow control on UART1 (RTS/CTS)
 IrDA and EIA-495 9-bit protocols
 µDMA support

Block Diagram

Basic Operation...
Basic Operation
 Initialize the UART
 Enable the UART peripheral, e.g.
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
 Set the Rx/Tx pins as UART pins
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
 Configure the UART baud rate, data configuration
ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
 Configure other UART features (e.g. interrupts, FIFO)
 Send/receive a character
 Single register used for transmit/receive
 Blocking/non-blocking functions in driverlib:

UARTCharPut(UART0_BASE, ‘a’);
newchar = UARTCharGet(UART0_BASE);
UARTCharPutNonBlocking(UART0_BASE, ‘a’);
newchar = UARTCharGetNonBlocking(UART0_BASE);

UART Interrupts
Single interrupt per module, cleared automatically
Interrupt conditions:
 Overrun error
 Break error
 Parity error
 Framing error
 Receive timeout – when FIFO is not empty and no further data is
received over a 32-bit period
 Transmit – generated when no data present (if FIFO enabled, see next
slide)
 Receive – generated when character is received (if FIFO enabled, see
next slide)
Interrupts on these conditions can be enabled individually
Your handler code must check to determine the source
of the UART interrupt and clear the flag(s)
Using the UART FIFOs
Transmit FIFO Level
FIFO Select
 Both FIFOs are accessed via the UART
Data register (UARTDR)
UART_FIFO_TX1_8
 After reset, the FIFOs are enabled*, you
UART_FIFO_TX2_8 can disable by resetting the FEN bit in
UARTLCRH, e.g.
UARTFIFODisable(UART0_BASE);
UART_FIFO_TX4_8
 Trigger points for FIFO interrupts
can be set at 1/8, 1/4, 1/2,3/4, 7/8
full, e.g.
UARTFIFOLevelSet(UART0_BASE,
UART_FIFO_TX6_8
UART_FIFO_TX4_8,
UART_FIFO_TX7_8 UART_FIFO_RX4_8);
* Note: the datasheet says FIFOs are disabled at reset

stdio Functions...
UART “stdio” Functions
 TivaWare “utils” folder contains functions for C stdio
console functions:
c:\TivaWare\utils\uartstdio.h
c:\TivaWare\utils\uartstdio.c
 Usage example:
UARTStdioInit(0); //use UART0, 115200
UARTprintf(“Enter text: “);
 See uartstdio.h for other functions
 Notes:
Use the provided interrupt handler UARTStdioIntHandler() code in
uartstdio.c
Buffering is provided if you define UART_BUFFERED symbol
 Receive buffer is 128 bytes
 Transmit buffer is 1024 bytes
#include <stdint.h>
#include "driverlib/pin_map.h"
#include "driverlib/uart.h"
int main(void) {
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200,

(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));

UARTCharPut(UART0_BASE, 'E');
UARTCharPut(UART0_BASE, 'n');
UARTCharPut(UART0_BASE, 't');
UARTCharPut(UART0_BASE, 'e');
UARTCharPut(UART0_BASE, 'r');
UARTCharPut(UART0_BASE, ' ');
UARTCharPut(UART0_BASE, 'T');
UARTCharPut(UART0_BASE, 'x');
UARTCharPut(UART0_BASE, ':');
while (1)
{
if (UARTCharsAvail(UART0_BASE)) UARTCharPut(UART0_BASE, UARTCharGet(UART0_BASE));
}

#include <stdint.h>
#include "inc/hw_ints.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin_map.h"
#include "driverlib/uart.h"
void UARTIntHandler(void)
{
uint32_t ui32Status;
ui32Status = UARTIntStatus(UART0_BASE, true); //get interrupt status
UARTIntClear(UART0_BASE, ui32Status); //clear the asserted interrupts
while(UARTCharsAvail(UART0_BASE)) //loop while there are chars

{
UARTCharPutNonBlocking(UART0_BASE, UARTCharGetNonBlocking(UART0_BASE)); //echo character
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, GPIO_PIN_2); //blink LED
SysCtlDelay(SysCtlClockGet() / (1000 * 3)); //delay ~1 msec
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 0); //turn off LED
}
}

int main(void) {
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); //enable GPIO port for LED

GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2); //enable pin for LED PF2
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200,

(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
IntMasterEnable(); //enable processor interrupts

IntEnable(INT_UART0); //enable the UART interrupt
UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT); //only enable RX and TX interrupts
UARTCharPut(UART0_BASE, 'E');
UARTCharPut(UART0_BASE, 'n');
UARTCharPut(UART0_BASE, 'r');
UARTCharPut(UART0_BASE, 'T');
UARTCharPut(UART0_BASE, 'x');
UARTCharPut(UART0_BASE, ':');
while (1) //let interrupt handler do the UART echo function

{
// if (UARTCharsAvail(UART0_BASE)) UARTCharPut(UART0_BASE, UARTCharGet(UART0_BASE));
}

What is Floating-Point?
 Floating-point is a way to represent real numbers on
computers
 IEEE floating-point formats:
 Half (16-bit) 
 Single (32-bit) 
 Double (64-bit) 
 Quadruple (128-bit) 

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X
Symbol Sign (s) Exponent (e) Fraction (f)
1 bit 8 bits 23 bits
Decimal Value = (-1)s (1+f) 2e-bias

where: f = ∑[(b-i)2-i] ∀ i ϵ (1,23)
bias = 127 for single precision floating-point
Symbol s e f
Example 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X
exponent = [10000110]2 = [134]10 fraction = [0.110100001000000000000000]2 = [0.814453]10

sign = (-1)0
= [1]10
Decimal Value = (-1)s x (1+f) x 2e-bias
= [1]10 x ([1]10 + [0.814453]10) x [2134-127]10
= [1. 814453]10 x 128
= [232.249]10

Floating-Point Unit (FPU)
 The FPU provides floating-point computation
functionality that is compliant with the IEEE 754
standard
 Enables conversions between fixed-point and
floating-point data formats, and floating-point
constant instructions
 The Cortex-M4F FPU fully supports single-
precision:
 Add
 Subtract
 Multiply
 Divide
 Single cycle multiply and accumulate (MAC)
 Square root

Modes of Operation...
Modes of Operation
 There are three different modes of operation for the FPU:
 Full-Compliance mode – In Full-Compliance mode, the FPU

processes all operations according to the IEEE 754 standard in
hardware. No support code is required.
 Flush-to-Zero mode – A result that is very small, as described in the

IEEE 754 standard, where the destination precision is smaller in
magnitude than the minimum normal value before rounding, is
replaced with a zero.
 Default NaN (not a number) mode – In this mode, the result of any
arithmetic data processing operation that involves an input NaN, or
that generates a NaN result, returns the default NaN. ( 0 / 0 = NaN )

FPU Registers
 Sixteen 64-bit double-word

registers, D0-D15
 Thirty-two 32-bit single-word
registers, S0-S31

FPU Usage
 The FPU is disabled from reset. You must enable it* before you can
use any floating-point instructions. The processor must be in
privileged mode to read from and write to the Coprocessor Access
Control (CPAC) register.
 Exceptions: The FPU sets the cumulative exception status flag in
the FPSCR register as required for each instruction. The FPU does
not support user-mode traps.
 The processor can reduce the exception latency by using lazy
stacking*. This means that the processor reserves space on the
stack for the FPU state, but does not save that state information to
the stack.
* with a TivaWare API function call

CMSIS...
#include <stdint.h>
#include <math.h>
#include "driverlib/fpu.h"
#include "driverlib/rom.h"
#ifndef M_PI
#define M_PI 3.14159265358979323846
#endif
#define SERIES_LENGTH 100

float gSeriesData[SERIES_LENGTH];
int32_t i32DataCount = 0;

int main(void)
{
float fRadians;
ROM_FPULazyStackingEnable();
ROM_FPUEnable();
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
fRadians = ((2 * M_PI) / SERIES_LENGTH);
while(i32DataCount < SERIES_LENGTH)

{
gSeriesData[i32DataCount] = sinf(fRadians * i32DataCount);
i32DataCount++;
}
while(1)
{
}
}

Chapter3 LM4F120 BasicPeripheralProgramming

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BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 5

Code và data chứa trong cùng không gian địa chỉ.

•Chỉ có 1 bus giao tiếp bộ nhớ.

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Truycập code và data cùng lúc

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 7

Cấu trúc pipeline cho phép một lệnh được

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 8

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 9

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256KB Flash memory

Battery-backed Hibernation Module

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Two Motion Control modules. Each with:

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 16

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 17

Compiler GNU C/C++ IAR C/C++ RealView C/C++ TI C/C++

Debugger / C-SPY / CCS/Eclipse-

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 18

GPIO Port A GPIO Port B

Advanced High Performance Bus Advanced Peripheral Bus

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 19

Clock Source Drive PLL? Used as SysClk?

driverLib API SysCtlClockSet() selects:  SYSDIV divider setting

 Can be employed as an n-bit parallel interface

Write to port address GPIO_PORTF_DIR_R

 Thanh ghi GPIO_PORTF_DIR_R , cấu hình

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 24

• Initialization (executed once at beginning)

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31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

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BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 27

Negative Logic s Positive Logic t

+3.3V +3.3V +3.3V +3.3V

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BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 29

 Require internal pull-up (set bits in PUR)

 The PF3-1 LEDs are positive logic

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 30

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 31

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 32

GPIO Port D (0x4005.8000)

Instead of writing to GPIO Port D directly, write to

Only the bits marked as “1” in the bit-mask are

GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_1, 0xEB);

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 33

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 34

#define PA5 (*((volatile unsigned long *)0x40004080))

BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 35

HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;

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BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM 40

Motor control ISRs (e.g. PWM, ADC)

#define PA5 (((volatile unsigned long )0x40004080))