2010 IEEE International Conference on Computational Intelligence and Computing Research

Phase-Locked Loop with High stability against process variation and GainBoosting Charge Pump for Current Matching characteristics
Prof.V.Sujatha,1 Professor&HEAD-Dept.of ECE, Vivekanandha college of Engineering for Women, Tiruchengode balkisujatha@gmail.com. Dr.R.S.D.Wahitha Banu2, Professor&HEAD-Dept.of ECE, Govt.College of Engineering, Salem drwahidabanu@gmail.com, Prof.R.Sakthivel3. Assistant Prof (Senior), rsakthivel@vit.ac.in, VIT University

Abstract
The charge pump (CP) circuit is a key element in a phaselocked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltagecontrolled-oscillator input and subsequently, a large phase noise on the PLL output signals. The primary purpose of this paper is to design a Charge pump phaselocked loop (CPLL) that can operate up to a frequency of 200 MHz using Gain-Boosting Charge Pump architecture. Good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.51.2 V on 0.18-um 1.8-V CMOS processes. The process variation and the frequency fluctuation can be eliminated by using the concept of Self Biasing; current mirror with error amplifier is used for providing the highest current matching in the charge pump. This CPLL is design in CADENCE VIRTUOSO Environment, simulated and verified by using SPECTRE with 0.18-um 1.8-V CMOS TSMC technology parameters.

frequency detector (PFD), a CP, a passive loop filter (LF), and a voltage controlled oscillator (VCO). The CPLL system is shown in Fig. 1.A divider is used in feedback, where the applications require the clock scaling. The PFD commonly generates a pair of digital pulses corresponding to the phase/frequency error between the reference clock and the VCO output by comparing the positive (or negative) edges of the two inputs. The CP then converts the digital pulses into an analog current that is converted to a voltage via the passive loop filter network. The resulting control voltage drives the VCO. The negative feedback loop forces the phase/frequency error to zero. A CPLL has to be designed with a proper consideration for stability [1] like any other feedback system.

Fig:1 Basic PLL structure Phase-locked loops (PLLs) consist of a phase/frequency detector (PFD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO), whose output is fed back to the PFD. The PFD compares an external reference signal and the VCO output signal and produces two digital signals (Up and Down), with the width of these two signals being determined by their frequency and phase. The CP converts the PFD output signal into a current that is fed into the LF, which determines the output LF voltage. The LF output voltage causes the VCO to generate a single frequency signal. Any fluctuation in the LF output voltage due to current mismatch in the CP causes a proportional variation in the VCO signal. The drainsource voltage of the n-channel MOS (nMOS) and p-channel MOS (pMOS) in the conventional CP can vary depending on the latter ones output voltage, thereby causing the magnitude of the currents in the pMOS (Up) and nMOS (Down) to differ. The LF output voltage

1. Introduction
CHARGE-PUMP based phase-locked loops (CPLL) are widely used as clock generators in a variety of applications including microprocessors, wireless receivers, serial link transceivers, and disk drive electronics. One of the main reasons for the widely adopted use of the CPLL in most PLL systems is because it provides the theoretical zero static phase offset, and arguably one of the simplest and most effective design. The CPLL also provides flexible design tradeoffs by decoupling various design parameters such as the loop bandwidth, damping factor, and lock range. A typical implementation of the CPLL consists of a phase

ISBN: 97881 8371 362 7

2010 IEEE International Conference on Computational Intelligence and Computing Research

fluctuates due to the current mismatch in the CP when the PLL is in the locking state; this causes the VCO output signal to have a large amount of phase noise with spurs [2]. .

2. Previous Works
The classical approach to CP employs a cascode [3], [4] and low-voltage cascode topology [5] to reduce the current mismatch by increasing its output resistance. This CP shows the current matching characteristics down to 2% of the sourcing/ sinking current difference. CPs with operational amplifiers shows good current matching characteristics of less than 1% of the sourcing/sinking current difference; however, these CP circuits require a large and oscillation-prone operational amplifier [6], [7]. A differential CP with an active LF and common-mode feedback scheme has been used to reduce the current mismatch [8]. However, it requires operational amplifiers, a reference voltage circuit, and an analog adder. A replica CP circuit and a bias generator are added to compensate the current mismatch down to 1% [9]. It makes the locking time longer and requires more complicated circuits. An additional CP with a modified PFD is included to compensate the current mismatch [10]. Fabrication mismatches between two CPs can cause the unexpected current mismatch in [10]. To reduce peak-to-peak jitter due to VCO noise, it is advantageous to keep as high a PLL bandwidth as possible. Traditional worst case design would keep the PLL bandwidth and damping factor sufficiently far away from stability limits under all variations of the input reference frequency, the manufacturing process, and the division ratio in the feedback Path N. For the conventional charge pumps, by enlarging the output impedance of the current source, the sourcing/sinking current matching is improved. This method, however, cannot produce perfect current matching characteristics because of the sizable output impedance of the practical devices used in the circuit 3.

compensation, leading to phase offset and loop filter ripple. A longer reset delay results in a longer period during which the VCO is running at a different frequency due to the compensation current. Therefore, the reset delay should be minimized under the constraint that it has to be longer than the response time of the PFD with some additional design margin to avoid a dead zone. Fig. 2 shows the diagram of a charge-pump PLL. The PFD checks the reference and feedback signals and controls the charge pump to produce a current Ip, which adjusts the control voltage Vc through a loop filter (LF). The voltage-controlled oscillator (VCO) oscillates at a frequency that varies with Vc. The feedback signal is the output of VCO, possibly reduced to a different frequency by a frequency divider. Assume that the PLLs nominal state is a locked state. At the nominal value of Vc , the VCO oscillates at N times the reference signal frequency. Fig. 3 shows the up and down signal generated from the Frequency/ Phase detector and fig.4 shows the amount of charge that has been pumped to the charge pump from the PFD. The charge pumped is given by the following equation.

Fig 2: Schematic diagram of a charge-pump PLL under study.

t T t

ref

I P ( )d

IP

Tref 2

IM

Q Tref

IP

IM

Q Tref

IP

2
---------------Eq (1)

Phase-Frequency Detector

Phase detectors may exhibit a dead zone, resulting in enlarged jitter. A common design technique to avoid a dead zone is to make sure that both Up and Down output signals are fully activated before shutting them both off. This is implemented by generating a reset signal with an AND operation of Up and Down output and introducing a delay before feeding back this signal to reset the phase detector. If the charge sharing in the charge pump is not perfectly cancelled or if there is a mismatch of up and down pulse and there will always be some current

2010 IEEE International Conference on Computational Intelligence and Computing Research

Fig 3: Up and Down signal generated from the PFD.

(a) (b) Fig: 5. (a) Concept of the gain-boosting circuit. (b) Simplified gain-boosting circuit.

Fig 4: Charge that is being pumped to the charge pump. 4. Gain-Boosting

Charge Pump
Fig: 6. Gain-boosting circuit. which is similar to the output resistance of a triplecascode circuit. By using this gain-boosting circuit, a new CP can be designed, in which the channel length modulation effect is lessened. In Fig. 7, which shows the proposed CP, MP4, and MN4, are the current sources for the single-transistor amplifiers MN3 and MP3, respectively. The output resistances of MN1 and MP1 are used as r01, as shown in Fig. 6. When the DN signal is active, MN2 and MN3 operate in conjunction with MN1 to provide a gain-boosting circuit. This increases the output resistance of the CP circuit and enhances the current matching characteristics. This gain-boosting CP circuit is suitable for a low power supply voltage because it does not require stacking more cascode devices to increase the output resistance. Since the transconductance and output resistance of the nMOS and pMOS are different, the enhancement of the output resistance of the two transistors in (1) cannot be the same, and this can result in current mismatch. Therefore, the Rout of both DN and UP circuits should be designed so that they are identical by carefully selecting the value of each component.

A current mismatch occurs due to the difference between the drainsource voltages of the pMOS and nMOS when dumping the charge to the LF. CP circuit with a gain-boosting circuit, which requires only a few more transistors than the conventional CP. Fig. 5(a) and (b) shows the concept of the gain-boosting circuit and the simplified gain-boosting circuit, respectively. The idea is to drive the gate of M2 by an amplifier that forces Vx to be equal to Vb. Thus voltage variations at the drain of M2 affect Vx to a lesser extent because A3 regulates this voltage. Due to the smaller variations at node X, the current through ro1and hence the output current remain more constant, thereby yielding higher output impedance. The output resistance of the gain-boosting circuit is given as follows: ---------Eq (2) Therefore Rout, can be boosted substantially without the need to stack more cascode devices on top of M2. The circuit can be implemented with the single transistor amplifier (M3) shown in Fig. 6, exhibiting an output resistance equal to

------Eq (3)

2010 IEEE International Conference on Computational Intelligence and Computing Research

damping factor without endangering stability. This can be done by setting the charge pump current to

------Eq (5) where I ref is a fixed reference current. This is realized by the current multiplier in Fig. 8, which generates the charge-pump current Ip by letting the individual bits of N control binary weighted current sources. The simulated jitter transfer function of a standard PLL in Fig. 9(a) demonstrates the change of loop parameters as is altered. The damping factor is intentionally set low to show its dependence on N. The measured jitter transfer function of Loop A in Fig. 9(b) shows the desired independence of N. The slight deviation of the curves is caused by transistor mismatch in the current multiplier.

Fig: 7. Proposed CP circuit. 5. SELF BIASED CHARGE PUMP

The concept of self-biasing introduced in [11] simplifies the design by eliminating process variations and the input reference frequency from the stability constraints. However, the PLL bandwidth is still a function of N, so that maximum noise suppression can only be achieved for a fixed N. In programmable applications, N can vary by more than an order of magnitude, indicating that the variation in stability constraint can be dominated by N instead of process variations, as shown by the stability limit of a charge-pump PLL [12]

Fig: 8. Current multiplier generating charge-pump biasing voltages Vqbn and Vqpb. 5.1 CHARGE SHARING PROBLEM A common problem of many charge pumps is charge sharing. For the charge pump in Fig. 10(a) (Type A), charge sharing is caused by the parasitic capacitance in nodes pcs and ncs [13]. When IUP is active, node pcs is charged to VDD When deactivating IUP some of the charge stored in node pcs will leak through the current source device. Since the parasitics of nodes ncs and pcs can never be matched, this will lead to a static phase offset. This is the transfer function of a phase-frequency detector followed by a Type A charge pump. The two transistors Mp and Mn in the Type B charge pump in Fig. 10(b) will remove the charge from the nodes pcs and ncs when Up and Down are deactivated [14].This leads to a large reduction in the phase offset

------Eq (4) Where fref is the input reference frequency (or effectively the sampling rate of the phase detector), Ko is the VCO gain, Ip is the charge-pump current, R and is the loop filter resistance. Other PLL design parameters, such as bandwidth and damping factor, also change with N. Compensating loop parameters for changes in N guarantees that the PLL is always operating with maximum bandwidth and fixed

2010 IEEE International Conference on Computational Intelligence and Computing Research

through the Mp device to the output when the Dwn control is inactive. When NMOS devices are used for speed-regulating the VCO, Vvco will never drop below Vtn, constraining Vqbn to be less than 2 Vtn which can easily be fulfilled. However, the charge pump works only up to an output voltage of Vvco< Vqbp + Vtp, limiting the upper tuning range of the VCO. However, the charge pump in Fig. 10(a) has the same upper voltage limit. Mismatch in IUP and IDOWN is a similar source of jitter as charge sharing described above. For low jitter, it is essential to have good matching, implying that the devices controlled by Vqbn/Vqbp should be saturated. Again, this requires Vvco< Vqbp + Vtp. Charge removal can also be done by ac coupling [15], but this requires careful timing of the control signals in the charge pump. The solution to charge sharing in [16] is less suitable for low- applications due to the common-mode restrictions on the differential amplifier. 6. CURRENT MATCHING CHARACTERISTICS In this proposed charge pump Fig.11, by using an error amplifer, the voltage Vref, at the node REF of the current mirror (M5 - Ms) follows the voltage Vcpout at the node CPOUT of the charge pump (M1~ M4). As a result, the voltage Vref, is equal to the voltage Vcpout as long as the amplifier maintains a high enough gain. For M5 = M1, M6 = M2, M7 = M3 and M8 = M4, if the DOWN and the UP signal are high, then I4 = I3 = I2, and if the DOWN and the UP signal are low, then I3 = I2 = I1. So we can make the sinking current I4 equal the sourcing current Il. In this way, one can achieve nearly perfect source/sinking current matching characteristics regardless of the charge pump output voltages.

Fig: 9. Jitter transfer functions for different division ratios. (a) Simulated standard PLL. (b) Measured characteristics of Loop A with intentionally low damping.

Fig: 10 (a) Charge-pump suffering from charge sharing (Type A). (b) Charge removal transistors eliminate charge sharing (Type B). A limitation of the Type B charge pump is a reduced dynamic range of the VCO control voltage (Vvco). If Vvco is less than Vqbn-Vtn there will be a current flowing

Fig:11. Proposed charge pump circuit with good current matching. 7. SIMULATION RESULTS The proposed CP and the conventional CP without a gain boosting, stability and current matching circuit are

2010 IEEE International Conference on Computational Intelligence and Computing Research

simulated by SPECTRE with 180nm, 1.8-V CMOS parameters. Fig.16 shows the variation of the Up/Down current without a gain-boosting circuit as the CP output voltage sweeps from 0 to 1.8 V. This CPs shows the current matching characteristics around 5% of the sourcing/sinking current difference. Fig.12-15 shows the stability, gain of VCO output and the charge pump current with reference and feedback signal. The graph has been plotted for both conventional and proposed chargepump PLL. Good current matching characteristics are observed over the CP output voltage ranges 0- 1.8-V CMOS process. The maximum difference of the Up/Down current is less than 0.1%. The sizes of the transistors that affect the most the current matching characteristics are listed in Table I. The longer the channel length, the better the current matching characteristics. The proposed design shows the highest gain and more stability.

Fig: 14 VCO control voltage when reference signal and feed back signal phase & frequencies are equal (Conventional Charge Pump PLL)

Fig:12. VCO control voltage when reference signal leads feed back signal (Conventional Charge Pump PLL)

Fig: 15 VCO control voltage when reference signal and feed back signal phase & frequencies are equal (Proposed Charge Pump PLL)

Fig:13 VCO control voltage when reference signal leads feed back signal (Proposed Charge Pump PLL)

Fig: 16. Ip and In when feed back signal leads reference signal in the proposed CP.

2010 IEEE International Conference on Computational Intelligence and Computing Research

Table: 1 Transistor Sizes of the Proposed Charge Pump Device MP1 MP2 MP3 Width(180nm 7.1 70 200 Device MN1 MN2 MN3 Width(180nm 2 100 200

8. CONCLUSION In this brief, a gain-boosting CP that has good current matching characteristics and stability in the PLL is proposed. By using a simple gain-boosting circuit to increase its output resistance, a CP with good current matching characteristics is achieved without the need for stacking more cascode devices, operational amplifiers with current mirror is provided to reduce the current mismatch. The maximum difference of the Up/Down current over the CP output voltage range 0-1.8-V process is less than 0.1%. It shows a current mismatch has been reduced and the gain has been boosted up with highest stability. The proposed CP has good current matching characteristics and is also suitable for low-power-supplyvoltage operation because it does not require stacking of more cascode devices.

9. References
[1]. F. Gardner, Charge pump phase-lock loops, IEEE Trans. Commun., vol. COM-28, pp. 18491858, Nov 1980. [2]. H. Arora, N. Klemmer, J. C.Morizio, and P. D.Wolf, Enhanced phase noise modeling of fractional-N frequency synthesizers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 379395, Feb. 2005. [3] P. Larsson, A 21600 MHz CMOS clock recovery PLL with low-Vdd capability, IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 19511960, Dec. 1999. [4] W. Rhee, B.-S. Song, and A. Ali, A 1.1 GHz CMOS fractional-N frequency synthesizer a 3-bit third-order modulator, IEEE J. Solid- State Circuits, vol. 35, no. 10, pp. 14531460, Oct. 2000. [5] R. Ahola and K. Halonen, A 1.76 GHz 22.6 mW __ fractional-N frequency synthesizer, IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 138140, Jan. 2003. [6] I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock generator with 5 to 110 MHz of lock range microprocessors, IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 15991607, Nov. 1992. [7] J.-S. Lee, M.-S.Keel, S.-I. Lim, and S. Kim, Charge pump with perfect current matching characteristics in phase-locked loops, Electron. Lett., vol. 36, no. 23, pp. 19071908, Nov. 2000. [8] N. Da Dalt and C. Sander, A subpicosecond jitter PLL for clock generation on 0.12- _m digital CMOS,

IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1275 1278, Jul. 2003. [9] H. Huh, Y. Koo, K. Y. Lee, Y. Ok, S. Lee, D. Kwon, J. Lee, J. Park, K. Lee, D. K. Jeong, and W. Kim, A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pump, in Proc. IEEE Int. Solid-State Circuit Conf., 2004, vol. 1, pp. 100101. [10] S. Pamarti, L. Jansson, and I. Galton, A wideband 2.4 GHz DeltaSigma fractional-N PLL with 1-Mb/s inloop modulation, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 4962, Jan. 2004. [11] J. G. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. SolidState Circuits, vol. 31, pp. 17231732, Nov. 1996. [12] F. M. Gardner, Charge-pump phase-lock loops, IEEE Trans. Communications, vol. COM-28, pp. 1849 1858, Nov. 1980. [13] M. Johnson and E. Hudson, A variable delayline PLL for CPUcoprocessor synchronization, IEEE J. Solid-State Circuits, vol. SC-23, pp. 12181223, Oct. 1988. [14] P. Larsson and J.-Y. Lee, A 400 mW 50380 MHz CMOS programmable clock recovery circuit, in Proc. IEEE ASIC Conf. Exhibit, 1995, pp. 271274. [15] V. von Kaenel, D. Aebisher, C. Piguet, and E. Dijkstra, A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation, in Proc. IEEE Int. Solid-State Circuits Conf., 1996, pp. 132133. [16] M. Johnson and E. Hudson, A variable delayline PLL for CPU coprocessor synchronization, IEEE J. Solid-State Circuits, vol. SC-23, pp. 12181223, Oct. 1988.

V.Sujatha received M.E degree in Applied Electronics from Anna University in 2004 and the Bachelor degree in Electronics & Communication Engineering from Madras University in 1993.She is working as a Professor and Head of the Department of electronics and communication Engineering, Vivekanandha college of Engineering for women, Tiruchengode.She is a member of ISTE, IETE and IEEE. She published several papers in National and International conferences. Her area of research is low jitter charge pump PLL and testing of PLL.

2010 IEEE International Conference on Computational Intelligence and Computing Research

Dr. R.S.D. Wahida Banu, M.E.,Ph.D. Received the Ph.D. degree in Engineering from Anna University, Chennai, in 1998. Her areas of interest are Network security, Neural networks, system-on-a-chip design, She is a life member of IEEE,ISTE,CSI,SSI and member in ISOC and ,VDAT.She is a co-Author of the books titled as Object Oriented Programming Visual Programming, Data mining application for empowering Knowledge societies. She published more than twenty technical papers in international journals, and eight papers in National journals and presented more than eighty papers in International and national level Conferences. Currently she is working as a Professor and Head of the department of Electronics and Communication Engineering, Government college of Engineering, Salem. R.Sakthivel received Bachelor degree in Electrical Engineering from Madras University in 2000 and the M.E degree in Applied Electronics from Anna University in 2004. He is working as a Assistant Professor (Senior) and division Leader of VLSI Division in the School of Electronics Engineering at Vellore Institute of Technology University, Vellore. His current research includes Low power VLSI Design, Developing High speed architecture for cryptography, Analog VLSI. He is a member IEEE, ISTE, SSI and VLSI Society of India (VSI). He is the Co-author of Basic Electrical Engineering" Published by Sonaversity in the year 2001 and author of VLSI Design published by S.Chand in the year 2007. He has also published several technical papers in national and international conferences.