10 MHz, 20 V/s, G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier

Data Sheet
FEATURES
Small package: 10-lead MSOP Programmable gains: 1, 2, 5, 10 Digital or pin-programmable gain setting Wide supply: 5 V to 15 V Excellent dc performance High CMRR 98 dB (minimum), G = 10 Low gain drift: 10 ppm/C (maximum) Low offset drift: 1.7 V/C (maximum), G = 10 Excellent ac performance Fast settling time: 615 ns to 0.001% (maximum) High slew rate: 20 V/s (minimum) Low distortion: 110 dB THD at 1 kHz High CMRR over frequency: 80 dB to 50 kHz (minimum) Low noise: 18 nV/Hz, G = 10 (maximum) Low power: 4.1 mA
DGND WR
2 6

AD8250
FUNCTIONAL BLOCK DIAGRAM
A1
5

A0
4

IN 1

LOGIC

7 OUT

+IN 10

AD8250
8 3 9
06288-001

+VS

VS

REF

Figure 1.
25 G = 10 20 15 G=5

APPLICATIONS
Data acquisition Biomedical analysis Test and measurement

GAIN (dB)

10 G=2 5 G=1 0 5 10 1k

GENERAL DESCRIPTION
The AD8250 is an instrumentation amplifier with digitally programmable gains that has G input impedance, low output noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of 110 dB and fast settling time of 615 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.7 V/C and 10 ppm/C, respectively, for G = 10. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8250 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use the transparent gain mode where the state of the logic levels at the gain port determines the gain.

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 2. Gain vs. Frequency

Table 1. Instrumentation Amplifiers by Category

General Purpose AD82201 AD8221 AD8222 AD82241 AD8228
1

Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571

Mil Grade AD620 AD621 AD524 AD526 AD624

Low Power AD6271 AD6231 AD82231

High Speed PGA AD8250 AD8251 AD8253

Rail-to-rail output.

The AD8250 is available in a 10-lead MSOP package and is specified over the 40C to +85C temperature range, making it an excellent solution for applications where size and packing density are important considerations.

Rev. C

Document Feedback One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 20072013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

06288-023

AD8250 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings ............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 15 Gain Selection ............................................................................. 15 Power Supply Regulation and Bypassing ................................ 17

Data Sheet
Input Bias Current Return Path ............................................... 17 Input Protection ......................................................................... 17 Reference Terminal .................................................................... 18 Common-Mode Input Voltage Range ..................................... 18 Layout .......................................................................................... 18 RF Interference ........................................................................... 19 Driving an ADC ......................................................................... 19 Applications..................................................................................... 20 Differential Output .................................................................... 20 Setting Gains with a Microcontroller ...................................... 20 Data Acquisition ......................................................................... 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22

REVISION HISTORY
5/13Rev. B to Rev. C Changed 49.9 to 100 in Driving an ADC Section and Figure 55 .......................................................................................... 19 11/10Rev. A to Rev. B Changes to Voltage Offset, Offset RTI VOS, Average Temperature Coefficient Parameter in Table 2 ............................. 3 Updated Outline Dimensions ....................................................... 22 5/08Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3.............................................................................6 Added Figure 17; Renumbered Sequentially .................................9 Changes to Figure 23...................................................................... 10 Changes to Figure 24 to Figure 26................................................ 11 Added Figure 29 ............................................................................. 11 Changes to Figure 31...................................................................... 12 Deleted Figure 43 to Figure 46; Renumbered Sequentially ...... 14 Inserted Figure 45 and Figure 46.................................................. 14 Changes to Timing for Latched Gain Mode Section ................. 16 Changes to Layout Section and Coupling Noise Section .......... 18 Changes to Figure 59...................................................................... 21 1/07Revision 0: Initial Version

Rev. C | Page 2 of 24

Data Sheet SPECIFICATIONS

+VS = 15 V, VS = 15 V, VREF = 0 V @ TA = 25C, G = 1, RL = 2 k, unless otherwise noted. Table 2.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 k Source Imbalance G=1 G=2 G=5 G = 10 CMRR to 50 kHz G=1 G=2 G=5 G = 10 NOISE Voltage Noise, 1 kHz, RTI G=1 G=2 G=5 G = 10 0.1 Hz to 10 Hz, RTI G=1 G=2 G=5 G = 10 Current Noise, 1 kHz Current Noise, 0.1 Hz to 10 Hz VOLTAGE OFFSET Offset RTI VOS Over Temperature Average Temperature Coefficient Offset Referred to the Input vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature Average Temperature Coefficient Input Offset Current Over Temperature Average Temperature Coefficient DYNAMIC RESPONSE Small Signal 3 dB Bandwidth G=1 G=2 G=5 G = 10 Settling Time 0.01% G=1 G=2 G=5 G = 10 Conditions +IN = IN = 10 V to +10 V 80 86 94 98 +IN = IN = 10 V to +10 V 80 86 90 90 98 104 110 110 Min Typ Max

AD8250

Unit

dB dB dB dB dB dB dB dB

40 27 21 18 2.5 2.5 1.5 1.0 5 60 G = 1, 2, 5, 10 T = 40C to +85C T = 40C to +85C VS = 5 V to 15 V (70 + 200/G) (90 + 300/G) (0.6 + 1.5/G) (2 + 7/G) 5 T = 40C to +85C T = 40C to +85C 5 T = 40C to +85C T = 40C to +85C (200 + 600/G) (260 + 900/G) (1.2 + 5/G) (6 + 20/G) 30 40 400 30 30 160

nV/Hz nV/Hz nV/Hz nV/Hz V p-p V p-p V p-p V p-p pA/Hz pA p-p V V V/C V/V nA nA pA/C nA nA pA/C

10 10 10 3 OUT = 10 V step 585 605 605 648

Rev. C | Page 3 of 24

MHz MHz MHz MHz ns ns ns ns

AD8250
Parameter Settling Time 0.001% G=1 G=2 G=5 G = 10 Slew Rate G=1 G=2 G=5 G = 10 Total Harmonic Distortion Conditions OUT = 10 V step Min Typ Max 615 635 635 685 20 25 25 25 f = 1 kHz, RL = 10 k, 10 V, G = 1, 10 Hz to 22 kHz band-pass filter G = 1, 2, 5, 10 OUT = 10 V 1 110

Data Sheet
Unit ns ns ns ns V/s V/s V/s V/s dB

GAIN Gain Range Gain Error G=1 G = 2, 5, 10 Gain Nonlinearity G=1 G=2 G=5 G = 10 Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output DIGITAL LOGIC Digital Ground Voltage, DGND Digital Input Voltage Low Digital Input Voltage High Digital Input Current Gain Switching Time 1 tSU tHD t WR -LOW t WR -HIGH

10 0.03 0.04

V/V % % ppm ppm ppm ppm ppm/C

OUT = 10 V to +10 V RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 All gains

6 8 8 10 10

5.3||0.5 1.25||2 VS = 5 V to 15 V T = 40C to +85C VS + 1.5 VS + 1.6 13.5 13.5 37 20 +IN, IN, REF = 0 VS 1 0.0001 Referred to GND Referred to GND Referred to GND VS + 4.25 DGND 2.8 0 +VS 2.7 2.1 +VS 325 See Figure 3 timing diagram See Figure 3 timing diagram See Figure 3 timing diagram See Figure 3 timing diagram 20 10 20 40 1 +VS +VS 1.5 +VS 1.7 +13.5 +13.5

G||pF G||pF V V V V mA k A V V/V V V V A ns ns ns ns ns

T = 40C to +85C

Rev. C | Page 4 of 24

Data Sheet
Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, IS Over Temperature TEMPERATURE RANGE Specified Performance
1

AD8250
Conditions Min 5 4.1 3.7 T = 40C to +85C 40 Typ Max 15 4.5 4.5 4.5 +85 Unit V mA mA mA C

Add time for the output to slew and settle to calculate the total time for a gain change.

TIMING DIAGRAM
tWR-HIGH
WR

tWR-LOW

tSU
A0, A1

tHD
06288-057

Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)

Rev. C | Page 5 of 24

AD8250 ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Common-Mode Input Voltage Differential Input Voltage Digital Logic Inputs Storage Temperature Range Operating Temperature Range3 Lead Temperature (Soldering, 10 sec) Junction Temperature JA (Four-Layer JEDEC Standard Board) Package Glass Transition Temperature
1 2

Data Sheet
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load (RL) is referenced to midsupply, the total drive power is VS/2 IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power Load Power)

Rating 17 V See Figure 4 Indefinite1 +VS + 13 V, VS 13 V +VS + 13 V, VS 13 V2 VS 65C to +125C 40C to +85C 300C 140C 112C/W 140C

VS VOUT PD = (VS I S ) + 2 R L

VOUT 2 RL

Assumes that the load is referenced to midsupply. Current must be kept to less than 6 mA. 3 Temperature for specified performance is 40C to +85C. For performance to 125C, see the Typical Performance Characteristics section.

In single-supply operation with RL referenced to VS, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four-layer JEDEC standard board.
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 40

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8250 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8250. Exceeding a junction temperature of 140C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as TJ = TA + (PD JA)
MAXIMUM POWER DISSIPATION (W)

20

20

40

60

80

100

120

AMBIENT TEMPERATURE (C)

Figure 4. Maximum Power Dissipation vs. Ambient Temperature

ESD CAUTION

Rev. C | Page 6 of 24

06288-004

Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN 1 DGND 2 VS 3 A1 5
10

AD8250

+IN REF

AD8250

WR

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic IN DGND VS A0 A1 WR OUT +VS REF +IN Description Inverting Input Terminal. True differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input.

Rev. C | Page 7 of 24

06288-005

8 +VS TOP VIEW A0 4 (Not to Scale) 7 OUT

AD8250 TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25C, +VS = +15 V, VS = 15 V, RL = 10 k, unless otherwise noted.
1400 1200
400
NUMBER OF UNITS

Data Sheet

500

NUMBER OF UNITS

1000 800 600 400

300

200

100

200 0 120 90 60 30 0 30 60 90 120 CMRR (V/V)

0 30 20 10 0 10 20 30 INPUT OFFSET CURRENT (nA)

06288-006

Figure 6. Typical Distribution of CMRR, G = 1

350 300

Figure 9. Typical Distribution of Input Offset Current

90 80 70
NOISE RTI (nV/ Hz)

250

NUMBER OF UNITS

60 50 G=1 40 30 20 10 0
06288-010

200 150

G=2 G=5 G = 10

100

50

200

150

100

50

50

100

150

200

06288-007

0 OFFSET VOLTAGE RTI (V)

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 7. Typical Distribution of Offset Voltage, VOSI

Figure 10. Voltage Spectral Density Noise vs. Frequency

600

500
NUMBER OF UNITS

400

300

200

100
2V/DIV 1s/DIV
06288-011

30

20

10

10

20

30

INPUT BIAS CURRENT (nA)

Figure 8. Typical Distribution of Input Bias Current

06288-008

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1

Rev. C | Page 8 of 24

06288-009

Data Sheet
150 130 110 G = 10 G=5

AD8250

PSRR (dB)

90 70 50 30

G=2

G=1

06288-012

1V/DIV

1s/DIV

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 10

18 16 150 130

Figure 15. Positive PSRR vs. Frequency, RTI

CURRENT NOISE (pA/ Hz)

14 110 12

G = 10 G=5

PSRR (dB)

10 8 6

90 G=2 70 G=1 50

4 2 0
06288-013

30 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 13. Current Noise Spectral Density vs. Frequency

10

Figure 16. Negative PSRR vs. Frequency, RTI

CHANGE IN OFFSET VOLTAGE, RTI (V)

9 8 7 6 5 4 3 2 1 0 0.01 1 0.1 WARMUP TIME (Minutes) 10

06288-117

06288-014

140pA/DIV

1s/DIV

Figure 14. 0.1 Hz to 10 Hz Current Noise

Figure 17. Change in Offset Voltage, RTI vs. Warmup Time

Rev. C | Page 9 of 24

06288-017

06288-016

10

AD8250
INPUT BIAS CURRENT AND OFFSET CURRENT (nA)

Data Sheet
10 8

15

10 IB
CMRR (V/V)

6 4 2 0 2 4 6 8
06288-019

0 IB+ 5 IOS 10

15 40

25

10

20

35

50

65

80

95

110

125

10 50

30

10

10

30

50

70

90

110

130

TEMPERATURE (C)

TEMPERATURE (C)

Figure 18. Input Bias Current and Offset Current vs. Temperature
140 G = 10 120 G=5 25 20 15 100 CMRR (dB)

Figure 21. CMRR vs. Temperature, G = 1

G = 10

G=5

GAIN (dB)

G=2 80

G=1

10 G=2 5 0 5 10 1k G=1

60

40

06288-020

10

100

1k

10k

100k

1M

10k

100k

1M

10M

100M

FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 19. CMRR vs. Frequency

140 G = 10 120 G=5

Figure 22. Gain vs. Frequency

40 30 20 10 0 10 20
06288-024

f = 1kHz

100 CMRR (dB) G=2 80 G=1

60

40

GAIN NONLINEARITY (10ppm/DIV)

30 40 10

06288-021

20 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)

10

OUTPUT VOLTAGE (V)

Figure 20. CMRR vs. Frequency, 1 k Source Imbalance

Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, RL = 10 k, 2 k, 600

Rev. C | Page 10 of 24

06288-023

20

06288-049

Data Sheet
40 f = 1kHz

AD8250
16 0V, +13.8V 13.8V, +6.9V 8 4 0 4 8 13.8V, 6.9V 12 16 16 0V, 14V 12 8 4 0 4 8 12 16
06288-028
06288-129

INPUT COMMON-MODE VOLTAGE (V)

GAIN NONLINEARITY (10ppm/DIV)

30 20 10 0 10 20
06288-025

12

VS = 15V

+13.8V, +6.9V

0V, +3.7V 3.8V, +1.9V VS = 5V 3.8V, 1.9V 0V, 4.0V +3.8V, 2.1V +3.9V, +1.9V

+13.8V, 6.9V

30 40 10

10

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, RL = 10 k, 2 k, 600

40 f = 1kHz

Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1

16

14.1V, +13.6V

0V, +13.8V VS = 15V

+13.6V, +13.1V

INPUT COMMON-MODE VOLTAGE (V)

GAIN NONLINEARITY (10ppm/DIV)

30 20 10 0 10 20
06288-026

12 8 4 4.2V, +2.2V 0 4 8 12 14.1V, 13.6V 16 16 12 8 4.2V, 2.0V

+0V, +3.5V +4.3V, +2.1V VS = 5V +4.3V, 2.1V 0V, 4.1V

30 40 10

0V, 14V 4 0 4

+13.6V, 13.1V 8 12 16
06288-029

10

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

Figure 25. Gain Nonlinearity vs. Output Voltage, G = 5, RL = 10 k, 2 k, 600

40 f = 1kHz 30

Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 10

35 30 25 IB+ IB IOS

GAIN NONLINEARITY (10ppm/DIV)

INPUT BIAS CURRENT AND OFFSET CURRENT (nA)

06288-027

20 10 0 10 20 30 40 10

20 15 10 5 0 5 10 15 15 10 5 0 5 10 15

10

OUTPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

Figure 26. Gain Nonlinearity vs. Output Voltage, G = 10, RL = 10 k, 2 k, 600

Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage

Rev. C | Page 11 of 24

AD8250
+VS +VS 0.2 OUTPUT VOLTAGE SWING REFERRED TO SUPPLY VOLTAGE (V) 0.4 0.6 0.8 1.0 +85C +25C +125C

Data Sheet

INPUT VOLTAGE REFERRED TO SUPPLY VOLTAGE (V)

1 2 +125C +85C +25C 40C

40C

+1.0 +0.8 +0.6 +0.4 +0.2 VS +125C 4 6 8 10

+25C

40C

+2 +85C +1 +125C
06288-030

+25C

40C

+85C 12 14 16
06288-033

VS

10

12

14

16

SUPPLY VOLTAGE (VS)

SUPPLY VOLTAGE (VS)

Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 k

15 +VS 10 FAULT CONDITION (OVER DRIVEN INPUT) G = 10 FAULT CONDITION (OVER DRIVEN INPUT) G = 10 +IN 0 IN 5

Figure 33. Output Voltage Swing vs. Supply Voltage, G = 10, RL = 10 k

15

+25C

10 OUTPUT VOLTAGE SWING (V)

40C

CURRENT (mA)

5 +85C 0 +125C +85C 5 +125C 10

10 VS
06288-031

40C +25C

12

12

16

1k LOAD RESISTANCE ()

10k

DIFFERENTIAL INPUT VOLTAGE (V)

Figure 31. Fault Current Draw vs. Input Voltage, G = 10, RL = 10 k

+VS 0.2 OUTPUT VOLTAGE SWING REFERRED TO SUPPLY VOLTAGE (V) 0.6 0.8 1.0 +85C +25C +25C +1.0 +0.8 +0.6 +0.4 +0.2 VS +125C +85C 40C 40C +125C

Figure 34. Output Voltage Swing vs. Load Resistance

+VS
OUTPUT VOLTAGE SWING REFERRED TO SUPPLY VOLTAGE (V)

0.4

0.4 +85C 0.8 1.2 1.6 2.0 +2.0 +1.6 +1.2 +0.8 +0.4

+125C

+25C

40C

40C

+25C

+85C 0 2 4 6

+125C 8 10 12 14 16

10

12

14

16

06288-032

VS

SUPPLY VOLTAGE (VS)

OUTPUT CURRENT (mA)

Figure 32. Output Voltage Swing vs. Supply Voltage, G = 10, RL = 2 k

Figure 35. Output Voltage Swing vs. Output Current

Rev. C | Page 12 of 24

06288-035

06288-034

15 16

15 100

Data Sheet
NO LOAD 47pF 100pF

AD8250

5V/DIV

VOUT (V)

605ns TO 0.01% 635ns TO 0.001% 0.002%/DIV

TIME (s)

06288-036

20mV/DIV

2s/DIV

2s/DIV TIME (s)

Figure 36. Small Signal Pulse Response for Various Capacitive Loads

Figure 39. Large Signal Pulse Response and Settling Time G = 5, RL = 10 k

5V/DIV

5V/DIV

585ns TO 0.01% 615ns TO 0.001% 0.002%/DIV 0.002%/DIV

648ns TO 0.01% 685ns TO 0.001%

06288-037

2s/DIV TIME (s)

2s/DIV TIME (s)

Figure 37. Large Signal Pulse Response and Settling Time, G = 1, RL = 10 k

Figure 40. Large Signal Pulse Response and Settling Time G = 10, RL = 10 k

5V/DIV

605ns TO 0.01% 635ns TO 0.001% 0.002%/DIV

06288-038

VOUT (V)

TIME (s)

TIME (s)

Figure 38. Large Signal Pulse Response and Settling Time G = 2, RL = 10 k

Figure 41. Small Signal Response G = 1, RL = 2 k, CL = 100 pF

Rev. C | Page 13 of 24

06288-042

2s/DIV

20mV/DIV

2s/DIV

06288-040

06288-039

AD8250
50 55 60 65 70 75 80 85 90 95 100 105
06288-043

Data Sheet
G G G G =1 =2 =5 = 10

THD + N (dB)

VOUT (V)

20mV/DIV TIME (s)

2s/DIV

115 120 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 42. Small Signal Response G = 2, RL = 2 k, CL = 100 pF

Figure 45. Total Harmonic Distortion + Noise vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, RL = 2 k
50 G G G G =1 =2 =5 = 10

60

70

THD + N (dB)

VOUT (V)

80

90

100
06288-044

20mV/DIV TIME (s)

2s/DIV

110 10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 43. Small Signal Response G = 5, RL = 2 k, CL = 100 pF

Figure 46. Total Harmonic Distortion + Noise vs. Frequency, 10 Hz to 500 kHz Band-Pass Filter, RL = 2 k

VOUT (V)

TIME (s)

Figure 44. Small Signal Response, G = 10, RL = 2 k, CL = 100 pF

06288-045

20mV/DIV

2s/DIV

Rev. C | Page 14 of 24

06288-150

06288-149

110

Data Sheet THEORY OF OPERATION

+VS +VS A0 2.2k +VS IN 2.2k A1 VS +VS DIGITAL GAIN CONTROL 10k 10k VS VS A1

AD8250

A3 VS +VS

OUT

+VS A2 +IN 2.2k VS WR +VS 2.2k

10k

10k

REF

+VS

VS

DGND
06288-054

VS

VS

Figure 47. Simplified Schematic

The AD8250 is a monolithic instrumentation amplifier based on the classic, 3-op-amp topology as shown in Figure 47. It is fabricated on the Analog Devices, Inc., proprietary iCMOS process that provides precision, linear performance, and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 2, 5, and 10. Gain control is achieved by switching resistors in an internal, precision resistor array (as shown in Figure 47). Although the AD8250 has a voltage feedback topology, the gain bandwidth product increases for gains of 1, 2, and 5 because each gain has its own frequency compensation. This results in maximum bandwidth at higher gains. All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout optimized for high CMRR over frequency enables the AD8250 to offer a guaranteed minimum CMRR over frequency of 80 dB at 50 kHz (G = 1). The balanced input reduces the parasitics that, in the past, adversely affected CMRR performance.

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 48 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 5 is the truth table for transparent gain mode, and Figure 48 shows the AD8250 configured in transparent gain mode.
+15V

10F

0.1F

WR A1 A0

15V +5V +5V G = 10

+IN

AD8250
REF IN DGND 10F 0.1F DGND

GAIN SELECTION
Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. See Table 2 for the permissible voltage range of DGND. The gain of the AD8250 can be set using two methods.

Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10

Rev. C | Page 15 of 24

06288-055

15V NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO VS. THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.

AD8250
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR VS VS VS VS A1 Low Low High High A0 Low High Low High Gain 1 2 5 10 WR High to low High to low High to low High to low Low to low Low to high High to high
1

Data Sheet
Table 6. Truth Table Logic Levels for Latched Gain Mode
A1 Low Low High High X1 X1 X1 A0 Low High Low High X1 X1 X1 Gain Change to 1 Change to 2 Change to 5 Change to 10 No change No change No change

Latched Gain Mode

Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8250 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 49 shows a schematic using this method, known as latched gain mode. The AD8250 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table in Table 6 for more information on these gain changes.
+15V WR 10F 0.1F A1 A0 +IN WR A1 A0 +5V 0V +5V 0V +5V 0V G = 10

X = dont care.

On power-up, the AD8250 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8250 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 at power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 have to be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time of tHD after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 can change logic levels, but the gain does not change (until the next downward edge of WR). The minimum duration that WR can be held high is t WR -HIGH, and the minimum duration that WR can be held low is t WR -LOW. Digital timing specifications are listed in Table 2. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 50. When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8250. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board. Pull-up or pull-down resistors should be used to provide a well-defined voltage at the A0 and A1 pins.

G = PREVIOUS STATE REF

AD8250
IN

DGND

DGND

10F

0.1F

Figure 49. Latched Gain Mode, G = 10

tWR-HIGH
WR

06288-056

15V NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.

tWR-LOW

tSU
A0, A1

tHD
06288-057

Figure 50. Timing Diagram for Latched Gain Mode

Rev. C | Page 16 of 24

Data Sheet
POWER SUPPLY REGULATION AND BYPASSING
The AD8250 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier. Place a 0.1 F capacitor close to each supply pin. A 10 F tantalum capacitor can be used farther away from the part (see Figure 51) and, in most cases, it can be shared by other precision integrated circuits.
+VS 0.1F WR A1 +IN 10F

AD8250
INCORRECT
+VS

CORRECT
+VS

AD8250
REF

AD8250
REF

VS TRANSFORMER +VS

VS TRANSFORMER +VS

AD8250
A0 OUT LOAD

AD8250
REF 10M REF

AD8250
IN DGND REF

VS THERMOCOUPLE +VS C
06288-058

VS THERMOCOUPLE +VS C

0.1F DGND VS

10F

AD8250
C REF

fHIGH-PASS = 21 RC

R C R

AD8250
REF

Figure 51. Supply Decoupling, REF, and Output Referred to Ground

INPUT BIAS CURRENT RETURN PATH

The AD8250 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 52).
VS CAPACITIVELY COUPLED

CAPACITIVELY COUPLED

Figure 52. Creating an IBIAS Return Path

INPUT PROTECTION
All terminals of the AD8250 are protected against ESD. Note that 2.2 k series resistors precede the ESD diodes as shown in Figure 47. The resistors limit current into the diodes and allow for dc overload conditions 13 V above the positive supply and 13 V below the negative supply. An external resistor should be used in series with each input to limit current for voltages greater than 13 V beyond either supply rail. In either scenario, the AD8250 safely handles a continuous 6 mA current at room temperature. For applications where the AD8250 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used.

Rev. C | Page 17 of 24

06288-059

VS

AD8250
REFERENCE TERMINAL
The reference terminal, REF, is at one end of a 10 k resistor (see Figure 47). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8250 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS or VS by more than 0.5 V. For best performance, especially in cases where the output is not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance can adversely affect CMRR and gain accuracy.
INCORRECT CORRECT

Data Sheet
The output voltage of the AD8250 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground.

Coupling Noise
To prevent coupling noise onto the AD8250, do the following guidelines: Do not run digital lines under the device. Run the analog ground plane under the AD8250. Shield fast switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. Avoid crossover of digital and analog signals. Connect digital and analog ground at one point only (typically under the ADC). Use the large traces on power supply lines to ensure a low impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section.

AD8250
VREF VREF +

AD8250

OP1177

06288-060

Common-Mode Rejection
The AD8250 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical instrumentation amplifiers whose CMRR falls off around 200 Hz. Typical instrumentation amplifiers often need common-mode filters at their inputs to compensate for this shortcoming. The AD8250 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering. Careful board layout maximizes system performance. To maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), route it perpendicular to the input traces.

Figure 53. Driving the Reference Pin

COMMON-MODE INPUT VOLTAGE RANGE

The 3-op-amp architecture of the AD8250 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8250 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 27 and Figure 28 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains.

LAYOUT
Grounding
In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8250 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PCB can cause errors. Therefore, use separate analog and digital ground planes. Analog and digital ground should meet at only one point: star ground.

Rev. C | Page 18 of 24

Data Sheet
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 54. The filter limits the input signal bandwidth according to the following relationship:

AD8250
DRIVING AN ADC
An instrumentation amplifier is often used in front of an ADC to provide CMRR. Usually, instrumentation amplifiers require a buffer to drive an ADC. However, the low output noise, low distortion, and low settle time of the AD8250 make it an excellent ADC driver. In this example, a 1 nF capacitor and a 100 resistor create an antialiasing filter for the AD7612. The 1 nF capacitor stores and delivers the necessary charge to the switched capacitor input of the ADC. The 100 series resistor reduces the burden of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. Selecting too small a resistor improves the correlation between the voltage at the output of the AD8250 and the voltage at the input of the AD7612 but may destabilize the AD8250. A tradeoff must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability.
+15V
CC

FilterFreq DIFF FilterFreqCM where CD 10 CC.

1 2 R(2C D CC )

1 2 RCC

+15V 0.1F 10F

+IN CD

10F

0.1F

WR A1 A0 100 REF 1nF

AD8250
REF IN

OUT

+12V 0.1F

12V 0.1F

+IN

CC 0.1F 15V 10F

06288-061

AD8250
IN DGND 10F 0.1F

AD7612
+5V ADR435

DGND
06288-062

Figure 54. RFI Suppression

Values of R and CC should be chosen to minimize RFI. A mismatch between the R CC at the positive input and the R CC at the negative input degrades the CMRR of the AD8250. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved.

15V

Figure 55. Driving an ADC

Rev. C | Page 19 of 24

AD8250 APPLICATIONS
DIFFERENTIAL OUTPUT
In certain applications, it is necessary to create a differential signal. High resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. Figure 57 shows how to configure the AD8250 to output a differential signal. An op amp, the AD817, is used in an inverting topology to create a differential voltage. VREF sets the output midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC.
+12V 0.1F AMPLITUDE +5V +IN WR A1 A0 AMPLITUDE VOUTA = VIN + VREF 2 REF 4.99k G=1 +2.5V 0V 2.5V

Data Sheet
SETTING GAINS WITH A MICROCONTROLLER
+15V 10F 0.1F WR A1 +IN A0 MICROCONTROLLER

AD8250
IN

DGND

REF

DGND
06288-063

10F

0.1F

15V

Figure 56. Programming Gain Using a Microcontroller

5V

+
VIN

AD8250

TIME

0.1F

DGND

12V 4.99k +12V 10F 12V 10F DGND 12V 10pF 0.1F

+ AD817
+12V

VREF 0V AMPLITUDE

0.1F +2.5V 0V 2.5V

VOUTB = VIN + VREF 2

TIME

Figure 57. Differential Output with Level Shift

Rev. C | Page 20 of 24

06288-064

Data Sheet
DATA ACQUISITION
The AD8250 makes an excellent instrumentation amplifier for use in data acquisition systems. Its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit ADCs. Figure 59 shows a schematic of the AD825x data acquisition demonstration board. The quick slew rate of the AD8250 allows it to condition rapidly changing signals from the multiplexed inputs. An FPGA controls the AD7612, AD8250, and ADG1209. In addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode. This system achieved 111 dB of THD at 1 kHz and a signal-tonoise ratio of 91 dB during testing, as shown in Figure 58.
0 10 20 30 40

AD8250

AMPLITUDE (dB)

50 60 70 80 90 100 110 120 130 0 5 10 15 20 25 30 35 40 45 50

06288-066

140 FREQUENCY (kHz)

Figure 58. FFT of the AD825x DAQ Demo Board Using the AD8250, 1 kHz Signal

JMP

+12V
0.1F
14

+12V + 10F

JMP
+ 12V

+5V
2k

VS

10F

GND
2

+CH1 +CH2 +CH3 +CH4

806 806 806 806 806 806 806 806

VDD
4 S1A 5 S2A
6

EN
DGND

DGND
DGND

JMP +5V
2k
5

S3A DA 8
0

7 S4A

0
CD

DGND 6
CC +IN

ALTERA EPF6010ATC144-3

ADG1209
10 S4B 11 S3B 12 S2B

CH4 CH3 CH2

DB 9 GND 15 A0
1

A1 4 A0 AD8250 REF IN 9 1 VS CC +VS 3

8

10

WR

DGND
7

OUT 0 49.9

+IN 1nF

AD7612

ADR435

CH1

13 S1B A1

VSS 16
3

C3 0.1F

C4 0.1F

+12V 12V JMP

+5V 2k

0.1F

12V

DGND

JMP

+5V R8 2k
06288-065

DGND

Figure 59. Schematic of ADG1209, AD8250, and AD7612 in the AD825x DAQ Demo Board

Rev. C | Page 21 of 24

AD8250 OUTLINE DIMENSIONS

3.10 3.00 2.90

Data Sheet

10

3.10 3.00 2.90 PIN 1 IDENTIFIER

5.15 4.90 4.65

0.50 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.30 0.15 15 MAX 1.10 MAX 0.70 0.55 0.40
091709-A

6 0

0.23 0.13

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 60. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters

ORDERING GUIDE
Model1 AD8250ARMZ AD8250ARMZ-RL AD8250ARMZ-R7 AD8250-EVALZ
1

Temperature Range 40C to +85C 40C to +85C 40C to +85C

Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Evaluation Board

Package Option RM-10 RM-10 RM-10

Branding H00 H00 H00

Z = RoHS Compliant Part.

Rev. C | Page 22 of 24

Data Sheet NOTES

AD8250

Rev. C | Page 23 of 24

AD8250 NOTES

Data Sheet

20072013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06288-0-5/13(C)

Rev. C | Page 24 of 24