NIELIT-CHENNAI

ASIC Back End Design & Implementation

Objective : This training program aims at giving exposure to Back-end custom IC
design flow and to provide better understanding on ASIC design concepts. Focus shall be
mainly on giving hands-on experience in EDA tools used by industries.
Target Audience :
1. BE/ME Students, Working Professionals.
2. Should be strong in Digital electronics
Batch Size : 10
Topics covered :
Schematic entry
Design test circuit using schematic entry
Functional simulation using Cadence Spectre
Symbol Creation
Layout Design using Cadence Virtuoso
Design Rule check using Cadence Assura
Layout versus Schematic
Duration : 9
th
June to 13
th
June 2014 (30 Hrs, 5days, 6hrs/day)
Timing : 9.30 am to 4 pm
Venue & lab: NIELIT, Chennai Centre
Course fee: Rs.5500/-(inclusive of all Taxes)
Registration fee is non-refundable
Full tuition fee is waived for limited no. of SC/ST candidates
Course in-charge : S.Harini, Project Associate
Email ID : aharini@nielitchennai.edu.in
Phone: 24421445, Ext.:207
How to apply :
Registration needs to be done at our Centre before the last date by
bringing the following documents:
1. Duly filled in registration form
2. Course fees
3. Copy of identity proof
4. Attested copy of community certificate (if availing SC/ST fee
concession)
Mode of payment :
Course fee may be paid by any one of the following modes:
1. Cash
NIELIT-CHENNAI



2. DD drawn from a nationalized bank (preferably SBI) in favour of
NIELIT Chennai payable at Chennai.