Macbook A1278-820-2879 SCH

TABLE_TABLEOFCONTENTS_ITEM
DRAWING
DESCRIPTION REFERENCE DES BOM OPTION QTY PART NUMBER CRITICAL
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3
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BRANCH
DRAWING NUMBER
REVISION
SIZE
D
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
R
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3 4 5 6
D
B
8 7 6 5 4 2 1
1 2
APPD
CK
DESCRIPTION OF REVISION
Schematic / PCB #s
SCHEM,MLB_LDO,K6
PVT, 3/18/10
1 OF 80
051-8563
A.13.0
1 OF 109
2010-03-18
LAST_MODIFIED=Thu Mar 18 17:53:39 2010
FireWire Constraints
Ethernet Constraints
MCP Constraints 2
K69_MLB 48 WELLSPRING 2
AUDIO: CODEC/REGULATOR
55
FSB/DDR3 Vref Margining
31
FireWire LLC/PHY (FW643E)
FireWire Port & PHY Power 34
SATA Connectors
Internal USB Support
SecureDigital Card Reader
41
BOM Configuration
K69_MLB
T27_MLB
SCHEM,MLB_LDO,K6
08/27/2009
Thermal Sensors
55
45 T27_MLB
09/30/2009
Current Sensing
54
44 T27_MLB
08/27/2009
Voltage Sensing
53
43 T27_MLB
08/21/2009
K6 SMBUS CONNECTIONS
52
42 T27_MLB
08/27/2009
LPC+SPI Debug Connector
51
41 T27_MLB
09/02/2009
SMC Support
50
40 T27_MLB
09/02/2009
SMC
49
39 T27_MLB
08/27/2009 48
38 T27_MLB
08/27/2009
External USB Connectors
46
37 T27_MLB
08/06/2009 45
36 T27_MLB
07/28/2009
FireWire Connector
43
35 T27_MLB
12/15/2009 42
T27_MLB
07/20/2009
33 T27_MLB
07/28/2009
Ethernet Connector
40
32 T27_MLB
08/20/2009
Ethernet PHY (Caesar II/IV)
39
T27_MLB
09/30/2009 35
30 T27_MLB
07/28/2009
RIGHT CLUTCH CONNECTOR
34
29 T27_MLB
09/29/2009 33
28 T27_MLB
06/19/2009
DDR3 BYTE/BIT SWAPS-K6
32
27 K18_MLB
07/28/2009
DDR3 SO-DIMM Connector B
31
26 T27_MLB
07/28/2009
DDR3 SO-DIMM Connector A
29
25 T27_MLB
07/28/2009
SB Misc
28
24 T27_MLB
08/06/2009
MCP Graphics Support
26
23 T27_MLB
08/15/2009
MCP Standard Decoupling
25
22 T27_MLB
11/23/2009
MCP89 GFX Core Rail Gating
24
21 T27_MLB
11/23/2009
MCP89 Memory Rail Gating
23
20 T27_MLB
08/06/2009
MCP Power & Ground
20
19 T27_MLB
11/23/2009
MCP HDA, LPC & MISC
19
18 T27_MLB
11/23/2009
MCP SATA, USB & Ethernet
18
17
11/05/2009
MCP Graphics
17
16 T27_MLB
11/05/2009
MCP PCIe Interfaces
16
15 T27_MLB
08/06/2009
MCP Memory Interface
15
14 T27_MLB
11/05/2009
MCP CPU Interface
14
13 T27_MLB
07/28/2009
eXtended Debug Port (mini-XDP)
13
12 T27_MLB
11/23/2009
CPU Decoupling
12
11 T27_MLB
07/20/2009
CPU Power & Ground
11
10 T27_MLB
08/27/2009
CPU FSB
10
9 T27_MLB
07/20/2009
SIGNAL ALIAS
9
8 K24_MLB
07/22/2009
Power Aliases
8
7 K24_MLB
07/20/2009
FUNC TEST
7
6 K24_MLB
07/20/2009
Revision History
5
5 K24_MLB
07/20/2009 4
4 K24_MLB
08/19/2009
Power Block Diagram
3
08/19/2009
System Block Diagram
2
2 K69_MLB
109
T27_MLB
08/06/2009
K6/K69 PCB Rule Definitions 80
108
T27_MLB
09/08/2009
K6/K69 Specific Constraints 79
106
T27_MLB
07/28/2009
SMC Constraints 78
105
T27_MLB
07/20/2009
77
104
T27_MLB
11/23/2009
76
103
T27_MLB
08/27/2009
75
102
T27_MLB
08/03/2009
MCP Constraints 1 74
101
T27_MLB
08/03/2009
Memory Constraints 73
100
T27_MLB
08/03/2009
CPU/FSB Constraints 72
98
T27_MLB
07/28/2009
LCD Backlight Support 71
97 08/27/2009
LCD Backlight Driver 70
94
K24_MLB
07/20/2009
DisplayPort Connector 69
93
K69_MLB
08/12/2009
DISPLAYPORT SUPPORT 68
90
K24_MLB
07/20/2009
LVDS CONNECTOR 67
79
T27_MLB
08/27/2009
Power FETs 66
78
T27_MLB
11/24/2009
Power Sequencing 65
77
T27_MLB
09/30/2009
Misc Power Supplies 64
76
K24_MLB
07/20/2009
CPU VTT(1.05V) SUPPLY 63
75
T27_MLB
08/18/2009
MCP VCore Regulator 62
74
K24_MLB
07/20/2009
IMVP6 CPU VCore Regulator 61
73
T27_MLB
08/06/2009
1.5V/1.35V LVDDR3 Supply 60
72
K24_MLB
07/20/2009
5V/3.3V SUPPLY 59
70
T27_MLB
07/29/2009
PBus Supply & Battery Charger 58
69
K24_MLB
07/20/2009
DC-In & Battery Connectors 57
68
AUDIO
08/27/2009
AUDIO: JACK TRANSLATORS 56
67
AUDIO
08/25/2009
AUDIO: JACK
66
AUDIO
07/17/2009
AUDI0: SPEAKER AMP 54
65
AUDIO
07/17/2009
AUDIO: HEADPHONE FILTER 53
63
AUDIO
07/17/2009
AUDIO: LINE INPUT FILTER 52
62
AUDIO
08/31/2009
51
61
T27_MLB
10/21/2009
SPI ROM 50
59
T27_MLB
07/20/2009
Sudden Motion Sensor (SMS) 49
58
T27_MLB
08/03/2009
57
T27_MLB
08/15/2009
WELLSPRING 1 47
56
K24_MLB
07/20/2009
Fan 46
SCHEM,MLB_LDO,K6 051-8563 SCH 1 CRITICAL
05/20/2009
Table of Contents
1
1 K17_MLB
Sync Contents
(.csa) Date
TITLE=MLB
ABBREV=DRAWING
PCBF,MLB_LDO,K6 820-2879 1 CRITICAL PCB
Page Contents
(.csa) Date
Sync Page
3
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P
G

1
7

U
S
B
(
U
P

T
O

1
2

D
E
V
I
C
E
S
)
6
J1300
J6750,6700
PG 56
U6633, U6623, U6613
PG 55 PG 53
Mic
U6880
PG 54
Filter
PG 53
Filter
PG 52
Amps
P
G

1
5
DISPLAY PORT
J3401
AIR PORT
PG 29
PG 70
J9400
J4501
PG 38
PG 68
PG 29
PG 32
J4000
E-NET
E-NET
BMC5764M
U3900
PG 18
PG 15,18
PG 17
PG 16
MAC
PG 18
PG 18
PG 12
Connectors
PG 37 PG 29
IR
PG 38 PG 47 PG30 PG38
7
USB
EXTERNAL
J4600, J4610
8
1
0

RGB OUT
1
1
9
HDMI OUT
Card reader
J4890
Blue Ray dec
KEYBOARD
J3500 U5701 J3401 J4890
PG 29
LPC+SPI Conn
PG 46
PG 46
J5601
PG 50
U5535,U5515
PG 45
PG 58,59
J6950,U7000
DC/BATT
Conns
Line In HEADPHONE
Amp
Audio
PG 18
PG 18
DDR3-1067/1333MHZ MEMORY
1067/1333 MHz
PG 10
XDP CONN
J1300
PENRYN
PG 12
64-Bit
2.X OR 3.X GHZ
INTEL CPU
U1000
PG 9
2 UDIMMs
J9000
CONN
LVDS
CONN
Conn
4
TMDS OUT
2
CLK
SATA
PCI
LPC
3
SATA
Audio
Codec
FSB
POWER SUPPLY
Conn
PG 31
GB Speaker
HD
ODD
Conn
SYNTH
SPI
PG 18
MAIN
J2900
DIMM
PG 25,26
J5100
Ser Fan ADC B,0 BSB
PWR
Misc
PG 14
GPIOs
1.05V/3GHZ.
1.05V/3GHZ.
PG 38
FSB INTERFACE
SMB
HDA
NVIDIA
SMB
1
0
5
U1400
DVI OUT
P
C
I
-
E
U
P

T
O

2
0

L
A
N
E
S
3
PG 17
LVDS OUT
DP OUT
AirPort
CONN
SATA
J4500
MCP
U6100
SMC
PG 39
SPI
U4900
Boot ROM
Prt
PG 51
FAN CONN AND CONTROL
POWER SENSE
CPU,MCP,TEMP SENSOR
CAMERA
TRACKPAD/ Bluetooth
CTRL
J3401
J3401
PCI-E
U6201
SYNC_MASTER=K69_MLB SYNC_DATE=08/19/2009
System Block Diagram
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MAX8840
PP1V05_S0_MCP_PLL_REG
MCP89
K6 POWER SYSTEM ARCHITECTURE
CHGR_BGATE
BATTERY CHARGER
DELAY
RC
DELAY
RC
DELAY
DELAY
RC
RC P1V8S0_EN
MCPCORES0_EN
CPUVTTS0_EN
P1V5S0_EN
DDRVTT_EN
16-5
16-6
PM_SLP_S3_L
16-3
16-4
AP_PWR_EN
Q7890
(9 TO 12.6V)
3S2P
PM_SLP_S3_L
U1400
PM_SLP_S4_L
MCP89 11
15
DELAY
RC
11-2
RC
DELAY
11-3
11-1
J6950
SMC_ADAPTER_EN
PM_SLP_S3_L
SMC_DCIN_ISENSE
PBUSVSENSE_EN
PPVBAT_G3H_CONN
P5VS0_EN
DELAY
PM_WLAN_EN_L
Q7890,Q7891
RC
P3V3S0_EN
(S0)
(S0)
16-2
16-1
16-1
16
04-1
=DDRREG_EN
=DDTVTT_EN
S5
S3
U7300
MCPCORES0_EN
VOUT2
TPS51116
0.75V
VOUT1
02
VIN
14
EN
VIN
02
1.5V
P5VS3_EN_L
P3V3S3_EN
DDRREG_EN
BKLT_EN
U4900
SMC
Q7055
PBUS SUPPLY/
ISL6259
U7000
P60
P16
PPVBAT_G3H_CHGR_R
ENA
VIN
02
LP8545
U9701
(S5)
04
SMC_PM_G2_EN
VOUT
U7840
01
PPBUS_G3H
A
R7020
ADAPTER
AC
IN
DCIN(16.5V)
F6905
6A FUSE
01
A
VIN
ENABLES
(S5)
CHGR_EN
PP18V5_DCIN_CONN
VOUT
PPVBAT_G3H_CHGR_REG
R7050
Q7085
Q7080
P3V3S5_EN_L
PPVOUT_SW_LCDBKLT
MCP_CORE
ISL9563A
MCPDDROUT
Q7930
SMC_BATT_ISENSE
P5VS3_EN_L
IMVP_VR_ON_R
25
02
U7500
8A FUSE
F7040
VOUT
(1A MAX CURRENT)
PP0V75_S0_REG
(25A MAX CURRENT)
PPMCPCORE_S0_R
(12A MAX CURRENT)
20
PP1V5_S3_REG
EN
U7750
ISL8009B
PP1V5R1V35_SW_MCP
VIN
21
VOUT
R7525
PP0V9_S5_REG
PPMCPCORE_S0_REG
P3V3S0_EN
Q7930
U7720
ST1S12G12R
1.2V
U7710
ISL8009B
U7740
1.8V
TPS62202
U7760
1.5V
EN2
05
VIN
EN1
02
3.3V
TPS51125
P5V3V3_PGOOD
PGOOD1,2
U7201
(RT)
5V
VREG3
(5.5A MAX
VOUT2
VOUT1
VR_ON
U7100
VIN
PGOOD
ISL9504B
VOUT
CPU VCORE
SMC_CPU_ISENSE
PP3V3_S5_REG
PP5V_S3_REG
(13A MAX CURRENT)
VR_PWRGOOD_DELAY
CURRENT)
P3V3S3_EN
Q7910
28
V
PGOOD
PPVCORE_S0_CPU
SMC_CPU_VSENSE
CPUVTTS0_PGOOD
PP1V2_ENET_REG
PP3V3_S0_FET
PP1V8_S0_REG
1.05V
PP1V5_S0_REG
(44A MAX CURRENT)
TPS7470
PP3V3_S0
PP1V5_S0
PP1V05_S0
V3
V2
V1
RST*
ISL88042
U7870
18
S0PGOOD_RST_L
MCPPLLDO_PGOOD
P1V5S0_PGOOD
P5V3V3_PGOOD
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
SLP_S5_L
SLP_S4_L
SLP_S3_L
09
ALL_SYS_PWRGD
05
SMC_ONOFF_L
RSMRST_PWRGD
SLP_S4_L(P94)
SLP_S3_L(P93)
SLP_S5_L(P95)
U4900
PWRGD(P12)
PWR_BUTTON(P90)
RSMRST_IN(P13)
99ms DLY
Q3450
PP3V3_S3_FET
P3V3ENET_EN_L
P3V3_S3_WLAN
26
VIN
EN
U6200
VOUT
4.5V AUDIO
PP4V5_AUDIO_ANALOG
13
24
07
17
Q7940
P5VS0_EN
PP5V_S0_FET
SMC
U2850
29
MCP_PS_PWRGD
U1000
CPU
U1400
PWRGD
PPBUS_G3H
PPDCIN_G3H_OR_PBUS
(S0)
V
PBUS_VSENSE
02
CPUVTTS0_EN
Q5315
02
CPUVTT
(1.05V)
TPS51117
U7600
EN_PSV VOUT
VIN
LT3470
ENABLE
U6990
VOUT
3.425V G3HOT
PBUS_G3H_VSENSE
PP1V05_S0
(8A MAX CURRENT)
PP3V42_G3H_REG
03
RN5VD30A-F
SMC PWRGD
U5010
04
RST*
P17(BTN_OUT)
IMVP_VR_ON(P16)
RSMRST_OUT(P15)
PLT_RST*
CPU_RESET#
PWRBTN*
PLTRST*
RESET*
CPUPWRGD(GPIO49)
PWRGOOD
RSMRST*
IMVP_VR_ON_R
PM_PWRBTN_L
SMC_RESET_L
25
PM_RSMRST_L
32
10
F
S
B
_
C
P
U
R
S
T
_
L
30
CPU_PWRGD
LPC_RESET_L
31
06-1
Power Block Diagram
3 OF 109
A.13.0
051-8563
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TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_BOMGROUP_ITEM
BOM OPTIONS BOM NAME BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_ALT_ITEM
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TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Top
GROUND
SIGNAL(High Speed)
Bar Code Labels / EEE #s
POWER
SIGNAL(High Speed)
11
POWER
10
9
8 GROUND
6
5
4
3
2
GROUND
SIGNAL
SIGNAL(High Speed)
SIGNAL(High Speed)
K6 BOARD STACK-UP
Module Parts
BOM Variants
SIGNAL
GROUND
7
Alternate Parts
DEVELOPMENT BOM
BOTTOM
BOM Groups
Programmable Parts
SYNC_MASTER=K24_MLB
BOM Configuration
152S0778 152S0693 CYNTEC AS ALTERNATE ALL
152S0685 152S0796 CYNTEC AS ALTERNATE ALL
157S0055 157S0058 DELTA AS ALTERNATE ALL
152S0874 152S0516 MAGLAYERS AS ALTERNATE ALL
152S1024 ALL 152S1025 TOKO AS ALTERNATE
337S3769 ALL
ALL 516S0790 MOLEX AS ALTERNATE
516-0201 ALL
152S1135 ALL
152S0586 152S0847 ALL MAGLAYERS AS ALTERNATE
128S0218 128S0093 ALL KEMET AS ALTERNATE
104S0023 104S0018 DALE/VISHAY AS ALTERNATE ALL
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 CRITICAL U5701 337S2983 WELLSPRING:BLANK 1
IC,ENCORE II,CY7C63803-LQXC CRITICAL IR:PROG 341S2384 1 U4800
U5701 CRITICAL WELLSPRING:PROG 1 341S2616 IC,TP PSOC,K17,K18
CRITICAL U4800 338S0633 IR:BLANK 1
U6100 EFI UNLOCKED,K6/K69 1 341T0238 BOOTROM:UNLOCKED CRITICAL
IC,EFI,LOCKED,K6 341S2589 BOOTROM:LOCKED CRITICAL 1 U6100
U6100 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP 335S0610 CRITICAL BOOTROM:BLANK 1
SMC EXTERNAL,K6 1 U4900 CRITICAL SMC:PROG 341T0240
SMC:BLANK 1 U4900 IC,SMC,HS8/2117,9X9MM,TLP,HF
IC,LP8545,LED BKLT CTRLR,LLP24 1 353S2896 U9701 CRITICAL
U3900 IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN 1 CRITICAL 343S0493 BCM5764M
PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA 337S3761 1 CRITICAL U1000 CPU:2.66GHZ
CPU:2.4GHZ PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA 337S3680 U1000 1
CPU:2.26GHZ PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550 U1000 337S3769 1
K6_DEBUG:PVT
K6_DEBUG:ENG
LPCPLUS,XDP_CONN K6_DEVEL:PVT
K6_DEVEL:ENG
K6_PROGPARTS
K6_DEBUG:PROD
K6_COMMON
K6_MISC
PCBA,MLB_LDO,BETTER,K6
PCBA,MLB_LDO,BEST,K6
085-1634 K6_DEVEL:PVT
U1000 1 337S3756 CPU:2.53GHZ PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA
MCP89M:A01 1 337S3797 CRITICAL IC,MCP89M-A01,31X31MM,BGA1168 U1400
U3990 1 BCM5764M CRITICAL 341S2731 IC,1MBIT,SPI FLASH,K17/18
IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12 338S0753 1 U4100 CRITICAL
[EEEE_DD23] EEEE:DD23 CRITICAL LBL,P/N LABEL,PCB,28MM X 6 MM 1 826-4393
[EEEE_DD24] EEEE:DD24 CRITICAL 1 826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM
CRITICAL 1 337S3866 MCP89M:A02 IC,MCP89M-A01,31X31MM,BGA1168 U1400
DEVEL_BOM CRITICAL DEVEL 1 085-1634 K6 MLB_LDO DEVELOPMENT BOM
CRITICAL
639-1120
639-1119
DEVEL_BOM,SMC_DEBUG:YES,XDP
CRITICAL
CRITICAL
CRITICAL
K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23
K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24
COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15
BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG
DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V
K6 MLB_LDO DEVELOPMENT BOM
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL
BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES
IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN
338S0563
516-0213
516S0706
MOLEX AS ALTERNATE
TOKO AS ALTERNATE
INTEL P7550 CPU AS ALTERNATE
152S0586
337S3704
ALL SSM6P15FE AS ALTERNATE 376S0360 376S0699
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NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
Revision History
Revision History
SYNC_MASTER=K24_MLB
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PAGE TITLE
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Apple Inc.
PAGE
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8 7 5 4 2 1
(NEED TO ADD 6 GND TP)
(NEED 3 TP)
KBD BACKLIGHT CONN
(NEED 4 TP)
(NEED 3 TP)
BATT POWER CONN
T57 CONN
RIGHT CLUTCH CONN
IPD_FLEX_CONN
(NEED 3 TP)
BIL CONN
SATA HDD/IR/SIL
SATA ODD CONN
SPEAKER FUNC_TEST
LVDS FUNC_TEST
(NEED 2 TP)
Fan Connectors
DEBUG VOLTAGE
Functional Test Points
KEYBOARD CONN
DC POWER CONN
FSB SIGNALS WITH NOTEST
MIC FUNC_TEST
(NEED 2 TP)
SPI DEBUG CONN
I12
I15
I16
I226
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I228
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I311
I312 I313
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I425
I426
FUNC TEST
SYNC_MASTER=K24_MLB
FSB_REQ_L<4..0> NO_TEST=TRUE
NO_TEST=TRUE FSB_LOCK_L
NO_TEST=TRUE FSB_DSTB_L_P<3..0>
NO_TEST=TRUE FSB_DSTB_L_N<3..0>
TRUE PM_SLP_S4_L
SMC_PM_G2_EN TRUE
PP1V5R1V35_S3 TRUE
PP4V5_AUDIO_ANALOG TRUE
PP3V3_S0_LCD_F TRUE
PP3V3_LCDVDD_SW_F TRUE
PP18V5_S3 TRUE
TRUE PP5V_S0_HDD_FLT
TRUE PPBUS_G3H
TRUE PP3V42_G3H
TRUE PP1V5_S0
TRUE PP3V3_S3
TRUE WS_KBD3
TRUE WS_KBD6
WS_KBD7 TRUE
TRUE PCIE_AP_D2R_N
PCIE_CLK100M_AP_CONN_P TRUE
TRUE USB_CAMERA_CONN_P
USB_BT_CONN_N TRUE
AP_RESET_CONN_L TRUE
TRUE PP3V3_S3
TRUE PP18V5_S3
TRUE Z2_CS_L
TRUE Z2_DEBUG3
TRUE Z2_RESET
TRUE SMBUS_SMC_A_S3_SDA
TRUE PP5V_WLAN
TRUE PP3V3_ENET
SPI_CLK TRUE
TRUE SPI_MOSI
TRUE PP5V_S0
TRUE FAN_RT_PWM
FAN_RT_TACH TRUE
TRUE WS_KBD2
TRUE SPIROM_USE_MLB
TRUE SPI_MISO
TRUE PP5V_SW_ODD
PP5V_WLAN TRUE
TRUE WS_KBD1
TRUE PSOC_SCLK
TRUE Z2_CLKIN
Z2_HOST_INTN TRUE
TRUE Z2_SCLK
Z2_MISO TRUE
Z2_MOSI TRUE
TRUE Z2_BOOST_EN
TRUE PSOC_F_CS_L
WS_KBD11 TRUE
TRUE WS_KBD13
TRUE WS_KBD4
TRUE WS_KBD5
TRUE PP3V3_S5
TRUE PP5V_S3
PP0V9_S5 TRUE
PP3V3_S3 TRUE
TRUE PP1V8_S0
PP3V3_S0 TRUE
WS_KBD_ONOFF_L TRUE
PP1V05_S0 TRUE
WS_KBD20 TRUE
WS_KBD22 TRUE
WS_KBD18 TRUE
TRUE BI_MIC_LO
TRUE WS_KBD14
TRUE WS_KBD16_NUM
WS_KBD15_CAP TRUE
WS_KBD17 TRUE
IR_RX_OUT TRUE
TRUE WS_LEFT_OPTION_KBD
WS_KBD21 TRUE
TRUE SPKRAMP_R_N_OUT
TRUE SPKRAMP_L_N_OUT
TRUE BI_MIC_HI
BI_MIC_SHIELD TRUE
PP5V_SW_ODD TRUE
SATA_HDD_D2R_C_P TRUE
SMC_ODD_DETECT TRUE
TRUE SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N TRUE
SATA_ODD_R2D_N TRUE
PP5V_S0_HDD_FLT TRUE
SATA_HDD_R2D_N TRUE
SATA_HDD_D2R_C_N TRUE
PP5V_S3_IR_R TRUE
WS_LEFT_SHIFT_KBD TRUE
TRUE WS_KBD23
WS_KBD19 TRUE
TRUE PCIE_WAKE_L
TRUE SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT TRUE
SPKRAMP_R_P_OUT TRUE
LVDS_IG_A_DATA_P<1> TRUE
SYS_DETECT_L TRUE
SMBUS_SMC_BSA_SCL TRUE
TRUE PP3V3_LCDVDD_SW_F
TRUE LED_RETURN_1
TRUE SMBUS_SMC_A_S3_SDA
WS_CONTROL_KBD TRUE
TRUE LVDS_IG_A_DATA_N<2>
TRUE LVDS_CONN_A_CLK_F_P
USB_T57_P TRUE
TRUE T57_RESET
PP5V_S3_BTCAMERA_F TRUE
TRUE SPKRAMP_L_P_OUT
TRUE SMBUS_SMC_A_S3_SCL
PCIE_AP_D2R_P TRUE
TRUE PPVCORE_S0_CPU
PCIE_AP_R2D_P TRUE
PCIE_AP_R2D_N TRUE
PPVCORE_S0_MCP TRUE
PP1V2_ENET TRUE
PP5V_S0 TRUE
TRUE LVDS_CONN_A_CLK_F_N
TRUE LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<0> TRUE
LVDS_DDC_CLK TRUE
BKL_VSYNC TRUE
TRUE PPVOUT_SW_LCDBKLT
TRUE PP3V3_S0_LCD_F
TRUE LVDS_IG_A_DATA_P<0>
LVDS_DDC_DATA TRUE
TRUE BKL_ISEN2
TRUE Z2_KEY_ACT_L
TRUE PP5V_S3
TRUE T57_PWR_EN
TRUE PP3V3_S3
TRUE PICKB_L
TRUE PSOC_MISO
TRUE PSOC_MOSI
TRUE SMBUS_SMC_A_S3_SCL
USB_T57_N TRUE
PPVBAT_G3H_CONN TRUE
SMBUS_SMC_BSA_SDA TRUE
SMC_LID_R TRUE
SMC_BIL_BUTTON_L TRUE
SMBUS_SMC_BSA_SDA TRUE
SMBUS_SMC_BSA_SCL TRUE
PP3V42_G3H TRUE
TRUE PCIE_CLK100M_AP_CONN_N
TRUE USB_CAMERA_CONN_N
TRUE USB_BT_CONN_P
TRUE AP_CLKREQ_Q_L
LVDS_IG_A_DATA_N<1> TRUE
SYS_LED_ANODE_R TRUE
SATA_HDD_R2D_P TRUE
TRUE SATA_ODD_R2D_P
TRUE PP3V42_G3H
TRUE BKL_ISEN3
LED_RETURN_4 TRUE
LED_RETURN_5 TRUE
TRUE LED_RETURN_6
WS_KBD12 TRUE
KBDLED_ANODE TRUE
SMC_KDBLED_PRESENT_L
TRUE
TRUE SPI_CS0_L
WS_KBD10 TRUE
TRUE WS_KBD9
TRUE WS_KBD8
TRUE PP3V42_G3H
TRUE PM_SLP_S3_L
TRUE PP18V5_DCIN_FUSE
TRUE ADAPTER_SENSE
FSB_HITM_L NO_TEST=TRUE
FSB_HIT_L NO_TEST=TRUE
NO_TEST=TRUE FSB_DINV_L<3..0>
NO_TEST=TRUE FSB_D_L<63..0>
NO_TEST=TRUE FSB_ADSTB_L<1..0>
FSB_ADS_L NO_TEST=TRUE
NO_TEST=TRUE FSB_A_L<35..3>
7 OF 109
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9 13 72
9 13 72
9 13 72
9 13 72
18 39 40 65
39 65
7 79
51
6 67
6 67
6 48
6 36
7 43
6 7
7 65 79
6 7
47
47
47
15 29 74
29 79
29 79
29 79
29
6 7
6 48
47 48
47 48
47 48
6 42 78
6 29
7
41 75
41 75
6 7 65
46
46
47
18 41 50
18 41 75
6 8
6 29
47
47 48
47 48
47 48
47 48
47 48
47 48
48
47 48
47
47
47
47
7 65 79
6 7
7
6 7
7
7 65 79
47
7 65
47
47
47
55 56
47
47
47
47
36 38
47
47
54 55
54 55
55 56
55 56
6 8
36 74
36 39
36 79
36 79
36 74
6 36
36 74
36 74
36
47
47
47
15 24 29
54 55
54 55
54 55
8 67 74
57
6 42 78
6 67
67 70
6 42 78
47
8 67 74
67 79
38 75
18
29
54 55
6 42 78
15 29 74
7 43
29 74
29 74
7 43
7
6 7 65
67 79
8 67 74
8 67 74
8 67
67 70
67 70
6 67
8 67 74
8 67
70
47 48
6 7
18
6 7
47 48
47 48
47 48
6 42 78
38 75
57 58
6 42 78
57
39 40 57
6 42 78
6 42 78
6 7
29 79
29 79
29 79
29
8 67 74
36
36 74
36 74
6 7
70
67 70
67 70
67 70
47
48
48
41 75
47
47
47
6 7
18 39 65 69
57
57
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
9 13 72
3 6
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PAGE TITLE
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Apple Inc.
PAGE
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3 4 5 6 7 8
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8 7 5 4 2 1
(CPU VCORE PWR)
"S0,S0M" RAILS
(MCP VCORE AFTER SENSE RES)
700 mA max output
"FIREWIRE" RAILS
"S5" RAILS
(BEFORE HIGH SIDE SENSING RES.)
139 mA/ 0 mA
105 mA/241 mA
LVDDR VRef/VTT (0.75V/0.675V) Rails
"ENET" RAILS
(SINCE PE0[3:0] IS NOT USED ON K6)
"S3" RAILS
LVDDR (1.5V/1.35V) Rails
4250 mA
(CONNECTS TO MCP BALLS)
& CPU VTT SENSING RES.)
(AFTER HIGH SIDE CPU VCORE
0.9V Rails
(BCM5764M)
"G3H" RAILS
(OR 1.35V)
0 mA
~400mA
(CONNECTS TO MCP BALLS)
(BCM57765)
(CONNECTS TO THE DECAPS)
UNUSED MCP PE0[3:0] AVDD/DVDD
(CONNECTS TO THE DECAPS)
400mA
~100mA
300mA
I1086
Power Aliases
=PP3V3_S0_OPA333
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_IMVP
=PP3V3_S0_CPUTHMSNS
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
PP1V05_S0_MCP_PLL_UF
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 mm
PP1V2_ENET
MAKE_BASE=TRUE
=PP1V2_ENET_PHY
=PP3V3_ENET_FET_R
=PP3V3_ENET_MCP_RMGT
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V8_S0
=PP3V3_ENET_MCP_PLL_MAC
=PP3V3_S5_REG
=PP3V3_S5_P0V9S5
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP5V_S3_T57
=PP5V_S0_CPU_IMVP
=PPVCORE_S0_MCPGFXFET
=PPVCORE_S0_MCP
=PP5V_S3_WLAN
=PP5V_S3_TPAD
=PP5V_S3_SYSLED
=PP3V3_S3_SMBUS_SMC_A_S3
=PPVCORE_S0_CPU
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_SW_MCP_FSB
=PP1V05_S0_MCP_M2CLK_DLL
=PPLVDDR_S3_MEM_B
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_MCP_PLL_UF_R
=PP1V5_S0_REG
=PP1V05_S0_MCP_DP0_VDD
=PP1V05_S0_FWPWRCTL
=PP1V05_S0_MCP_PLL_IFP
=PPBUS_S5_CPUREGS_ISNS_R
=PP1V05_S0_MCP_PE_AVDD0
=PP1V8_S0_AUDIO
=PP1V2_ENET_PHY_REG
=PP1V05_S0_MCP_PE_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP3V3_S3_PDCISENS
=PPVIN_S0_CPUVTTS0
=PP1V5R1V35_S0_MCPDDRFET
=PPVIN_S0_DDRREG_LDO
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
=PPDCIN_S5_CHGR
=PPVP_FW_PHY_CPS_FET
=PP1V2_ENET_REG
=PP1V5R1V35_S3_MCP_MEM
=PP3V42_G3H_REG
=PPLVDDR_S3_MEM_A
=PPBUS_FW_FET
=PPBUS_S5_CPUREGS_ISNS
=PPVIN_S5_CPU_IMVP
=PP1V0_FW_FET_R
=PP3V3_FW_FWPHY
=PPVP_FW_PORT1
=PP3V42_G3H_BMON_ISNS
=PPDDR_S3_REG
=PP3V3_S5_P3V3S0FET
=PP0V9_ENET_FET
=PP3V3R1V8_S0_MCP_IFP_VDD
=PPBUS_S0_LCDBKLT
=PPBUS_G3H
=PP5V_S3_REG
=PP0V9_S5_REG
=PP0V9_ENET_P0V9ENETFET
=PP0V9_S5_MCP_VDD_AUXC
=PP1V0_FW_FWPHY
=PP5V_S3_BTCAMERA
=PP3V3_FW_FET
=PP1V05_S0_MCP_PLL_OR
=PPMCPCORE_S0_REG
=PP5V_S3_MCPDDRFET
=PP3V3_S5_MCPPWRGD
=PP3V3_FW_P3V3FWFET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_S5_MCP
=PP1V05_S0_MCP_PE_DVDD0
=PPVTT_S0_DDR_LDO
=PPDDRVTT_S0_MEM_A
=PP1V8_S0_REG
=PPVTT_S3_DDR_BUF
=PP3V3_S3_FET
=PP5V_S0_FET
MIN_NECK_WIDTH=0.3 MM
MAKE_BASE=TRUE
VOLTAGE=12.6V
PPBUS_S5_IMVP_VTT_ISNS
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V5R1V35_S3
PPVP_FW
VOLTAGE=12.6V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP3V3_FW
VOLTAGE=3.3V
PP1V05_FW
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPDDRVREF_S3
VOLTAGE=0.75V
MAKE_BASE=TRUE
PP1V05_S0_MCP_PE_AVDD
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
VOLTAGE=0.9V
PP0V9_S5
=PP3V3_S0_TPAD
=PP18V5_DCIN_CONN
=PP5V_S3_IR
=PP5V_S3_DDRREG
PP3V3_ENET
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PP3V3_ENET_PWRCTL
=PP5V_S3_AUDIO
=PP3V3_S0_P1V5S0
=PP3V3_S0_DEBUGROM
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PP3V3_S0_CPUVTTISNS
=PP3V3_S0_FWLATEVG
=PPDDRVTT_S0_MEM_B
PPDDRVTT_S0
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP3V3_S0_PWRCTL
=PP3V3_S0_MCP_HVDD
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP1V5_S0_SATARDRVR
=PP1V8R1V5_S0_AUDIO
=PP1V5_S0_CPU
=PP1V5_S0_MCP_PLL_VLDO
MAKE_BASE=TRUE
PP1V5_S0
VOLTAGE=1.5V
=PP1V5_S0_MCP_HDA_R
=PP3V3_S0_MCPCOREISNS
=PP1V5_S0_AUDIO_R
=PP3V3_S0_MCP_HDA_R
=PP3V3_S0_ENETPHY
=PP3V3_S0_ODD
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S0_P1V8S0
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_SMBUS_MCP_0 MAKE_BASE=TRUE
PPBUS_G3H
VOLTAGE=12.6V
=PP3V42_G3H_BATT
=PP3V42_G3H_TPAD
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_ONEWIRE
=PPVIN_S0_MCPCORE
=PPVIN_S3_DDRREG
=PPBUS_S5_FWPWRSW
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P5VS0FET
=PP5V_S0_ODD
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_VMON
=PP3V3_S5_SMBUS_SMC_MGMT
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_LCD
=PP5V_S3_RTUSB
PP5V_S3
VOLTAGE=5V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S5
VOLTAGE=3.3V
PP3V3_S3
MAKE_BASE=TRUE
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
=PP3V3_S3_CARDREADER
=PP3V3_S3_T57
=PP3V3_ENET_P1V2ENET
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_0_S0
=PPSPD_S0_MEM_B
=PP3V3_S0_AUDIO_R
=PP3V3_S0_SDCONN
=PP3V3_S0_FWPWRCTL
=PP5V_S0_HDD
=PP5V_S0_KBDLED
=PP5VR3V3_S0_DPCADET
=PP5V_S0_CPUVTTS0
=PP5V_S0_MCPREG
=PP5V_S0_MCPFSBFET
=PP3V3_S0_AUDIO
=PP3V3_S0_FAN_RT
MAKE_BASE=TRUE
PP3V3_S0
VOLTAGE=3.3V
=PP3V3_S0_FET
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_FSB
PPVCORE_S0_MCP
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCORE_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=1.25V
=PPVCORE_S0_CPU_REG
=PPCPUVTT_S0_REG
MAKE_BASE=TRUE
PP1V05_S0
VOLTAGE=1.05V
=PP1V05_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=0.9V
PP0V9_ENET
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT
=PP5V_S0_BKL
PP5V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PPVIN_S5_SMCVREF
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
PP3V3_G3_RTC
PP3V42_G3H
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V42_G3H_OPA330
PPDCIN_S5_S5
VOLTAGE=18.5V
MAKE_BASE=TRUE
8 OF 109
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051-8563
7 OF 80
22
12
19 22
61
45
6
31
8
17 19 22
6
19 22
22
59
64
50
67
38
61
21
19 22
29
48
40
42
10 11
19 22
19 22
14 22
26
34
64
64
16 23
34
16 23
44
19
64
7
22
22
60
63
20
60
59
59
58
35
64
14
57
25
34
44
61
34
33 34 35
35
44
60
66
66
16 23
71
58
59
64
66
19 22
33 34
29
34
64
62
20
24
34
66
69
19 22
19
7 22
60
25
64
28 60
66
66 6 79
22
6
48
57
36 38
60
6
24 31 64
65
51 53 55
64
41
69
25
44
34 35
26
65
22
19 22
40
45
36
51
10 11
6 65 79
8
44
8
8
31
36
70
42
64
44
42
6 43
57
47
37
57
62
60
34
54
66
36
17 18
66
66
65
42
16 17 18
67
37
6
6 65 79
6
28
29
18
47 48
49
30
38
64
42
42
26
8
30
34
36
48
69
63
62
21
51 55 56
46
6 65 79 66
22
13 19 22
6 43
6 43 61
63 6 65
9 10 11 12 61
19
19
41
46
70
6 65
65
42
40
41
39 40
58 65
18 19 22
6
22
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT IN
OUT
OUT
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
DISPLAY PORT ALIASES
AUDIO ALIASES
MCPCOREISNS SIGNAL
LEFT OF CPU
BACKLIGHT CONTROLLER ALIASES
5V ODD ALIASES
BELOW CPU
CPU ALIASES
266
UNUSED GPU LANES
BELOW MCP
ABOVE CPU
FAN STANDOFF
PCI-E ALIASES
EMI TALL POGO PINS
FSB MHZ
200
133
BSEL<2..0>
0 0 1
0 0 0
(RSVD)
100
(400) 1 1 0
1 0 1
1 0 0 333
0 1 0
0 1 1 (166)
USB ALIASES
1 1 1
EMI IO (SHORT) POGO PINS
MCP89 ALIASES
UNUSED USB PORTS
MLB MOUNTING (TO TOPCASE) SCREW HOLES
HEATSINK STANDOFFS
ETHERNET ALIASES
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
DACS ALIASES
LVDS ALIASES
UNUSED CRT & TV-OUT INTERFACE
CHARGER SIGNAL
17 76
17 76
17 76
17 76
17 76
17 76
17 76
17
5%
10K
1/16W
MF-LF
R0984
402
MF-LF
402
10K
5%
1/16W
R0983 R0982
MF-LF
1/16W
5%
10K
402
R0981
10K
402
5%
1/16W
MF-LF
R0980
MF-LF
1/16W
5%
402
10K
39 40 57 58
PLACE_NEAR=L9701.1:5MM
402
MF-LF
5%
0
R0910
1/16W
100K
R0920
1/16W
MF-LF 5% 402
R0911
0
5%
MF-LF
1/16W
402
PLACE_NEAR=U7980.A1:5MM
7
HDA:1.5V
402
0
5% MF-LF 1/16W
R0912
402 5% MF-LF
0
1/16W
HDA:3.3V
R0913
0
402 5%1/16W MF-LF
HDA:1.5V
R0914
HDA:3.3V
402 1/16W MF-LF
0
5%
R0915
402
MF-LF
1/16W
10K
5%
R0986
NO STUFF
18 31
OMIT
3R2P5
Z0912
3R2P5
Z0909
OMIT
OMIT
Z0911
3R2P5
OMIT
Z0908
3R2P5
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0901
Z0904
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0902
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0903
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0905
3R2P5
OMIT
Z0910
SM
ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
ZS0906
SM
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
ZS0904
SM
2.0DIA-TALL-EMI-MLB-M97-M98
ZS0907
SM
Z0907
3R2P5
OMIT OMIT
3R2P5
Z0906
1.4DIA-SHORT-EMI-MLB-K19-K24
ZS0900
SM SM
ZS0901 ZS0902
SM
SM
ZS0903 ZS0908
SM SM
ZS0909
SIGNAL ALIAS
SYNC_MASTER=K24_MLB
ENET_RXD<2>
ENET_RX_CTRL
ENET_RXD_PD
MAKE_BASE=TRUE
DP_EXT_HPD
MAKE_BASE=TRUE
DP_IG_HPD0
DP_IG_ML0_N<0..3>
DP_IG_ML0_P<0..3>
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
=MCP_IFPAB_DDC_CLK
LCD_IG_BKLT_PWM
=MCP_IFPB_TXD_N<0..3>
=MCP_IFPA_TXD_N<3>
=MCP_IFPA_TXC_N
CRT_IG_HSYNC
MCP_CLK27M_XTALIN
MCP_TV_DAC_VREF
MCP_TV_DAC_RSET
CRT_IG_R_C_PR
MAKE_BASE=TRUE NO_TEST=TRUE
NC_CRT_IG_HSYNC
=MCP_IFPA_TXD_N<0..2>
=MCP_IFPB_TXC_P
=MCP_IFPAB_DDC_DATA
DP_IG_ML1_N<0..3>
DP_IG_AUX_CH1_P
DP_IG_AUX_CH1_N
TP_DP_IG_AUX_CH1P
MAKE_BASE=TRUE
TP_DP_IG_ML1P<0..3>
MAKE_BASE=TRUE
DP_CA_DET
DP_AUX_CH_C_P
LCD_IG_BKLT_EN
=MCP_IFPB_TXC_N
TP_PEG_CLKREQ_L
MAKE_BASE=TRUE
=PP3V3_ENET_FET_R
TP_DP_IG_AUX_CH1N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_EXT_AUX_CH_C_P
DP_IG_AUX_CH_N
MAKE_BASE=TRUE
USB_EXTC_N
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
TP_MCP_RGB_HSYNC
TP_MCP_RGB_DAC_RSET
PPBUS_SW_LCDBKLT_PWR
USB_EXTD_P
TP_MCP_RGB_VSYNC
=PP5V_SW_ODD_FET
TP_MCP_RGB_DAC_VREF
CPU_PECI_MCP
MCP_CLK27M_XTALOUT
=PEG_R2D_C_P<3:0>
=PEG_D2R_P<3:0>
=PEG_R2D_C_N<3:0>
PEG_CLK100M_P
PEG_CLK100M_N
CRT_IG_VSYNC
USB_WM_N
USB_MINI_P
USB_EXTD_N
USB_WM_P
USB_EXTC_P
PEG_CLKREQ_L
CRT_IG_G_Y_Y
=PEG_D2R_N<3:0>
=MCP_BSEL<0:2>
=PPBUS_SW_BKL
=PP5V_SW_ODD
=MCP_IFPA_TXD_P<0..2>
=MCP_IFPA_TXC_P
=MCP_IFPA_TXD_P<3>
=MCP_IFPB_TXD_P<0..3>
CRT_IG_B_COMP_PB
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE MAKE_BASE=TRUE
NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_N<0..2>
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
NO_TEST=TRUE
LCD_BKLT_PWM
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<0..3>NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_CLKN NO_TEST=TRUE
MAKE_BASE=TRUE
LCD_BKLT_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE NC_LVDS_IG_A_DATAP<3>
NC_MCP_TV_DAC_VREF
NC_MCP_CLK27M_XTALOUT
NC_CRT_IG_R_C_PR
NC_MCP_RGB_RED
MAKE_BASE=TRUE
DP_IG_AUX_CH_P
MAKE_BASE=TRUE
DP_EXT_AUX_CH_C_N
DP_EXT_CA_DET
MAKE_BASE=TRUE
DP_EXT_ML_P<0..3>
MAKE_BASE=TRUE
NC_MCP_RGB_BLUE
NC_MCP_RGB_GREEN
NC_PEG_R2D_C_P<3:0>
TP_USB_WMP
MAKE_BASE=TRUE
NC_MCP_TV_DAC_RSET
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<3:0>
NO_TEST=TRUE
NC_PEG_D2R_P<3:0>
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
TP_PEG_CLK100M_P
MAKE_BASE=TRUE
TP_PEG_CLK100M_N
MAKE_BASE=TRUE
TP_USB_WMN
MAKE_BASE=TRUE
TP_USB_MINIP
MAKE_BASE=TRUE
TP_USB_EXTDN
TP_USB_EXTCN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_USB_EXTCP
MAKE_BASE=TRUE
TP_USB_EXTDP
MAKE_BASE=TRUE
NC_MCP_RGB_VSYNC
NO_TEST=TRUE
NC_MCP_RGB_DAC_RSET
MAKE_BASE=TRUE
LVDS_IG_A_DATA_P<0..2>
MAKE_BASE=TRUE
LVDS_IG_A_CLK_N
CPU_BSEL<0:2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<3:0>
NO_TEST=TRUE
NC_CRT_IG_B_COMP_PB
VOLTAGE=5V
PP5V_SW_ODD
MAKE_BASE=TRUE
TP_DP_IG_ML1N<0..3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_EXT_ML_N<0..3>
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
LVDS_DDC_CLK
MAKE_BASE=TRUE
LVDS_DDC_DATA
MAKE_BASE=TRUE
USB_MINI_N TP_USB_MININ
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPBUS_SW_BKL
VOLTAGE=12.6V
ENET_MDIO
ENET_RXD<1>
ENET_RXD<3>
MAKE_BASE=TRUE
ENET_RXCLK_PD ENET_CLK125M_RXCLK
=PP3V3_ENET_FET
ENET_RXD<0>
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_ENET_FET
=MCPCOREISNS_P
=MCPCOREISNS_N
SMC_BC_ACOK
MAKE_BASE=TRUE
MCPCOREISNS_N
MAKE_BASE=TRUE
MCPCORES0_VO
MCPCOREISNS_P
MAKE_BASE=TRUE
MCPCORES0_ISP_R
=CHGR_ACOK
DP_IG_HPD1
=PP3V3R1V5_S0_MCP_HDA
=PP3V3R1V5_S0_AUDIO
VOLTAGE=1.5V
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_MCP_HDA_R
=PP1V5_S0_AUDIO_R
=PP3V3_S0_AUDIO_R
=PP1V5_S0_MCP_HDA_R
DP_IG_ML1_P<0..3>
DP_AUX_CH_C_N
DP_IG_ML_N<0..3>
DP_IG_ML_P<0..3>
VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6mm
PP3V3R1V5_S0_AUDIO
ENET_LOW_PWR
MCP_RGMII_VREF
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V
9 OF 109
A.13.0
051-8563
8 OF 80
1
2
1
2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
1
1
1
1
1
1
1
1
1
1 1 1 1
1 1
1 1 1
1 1 1
69 16
16
16
16
16
16
16
16
16
16
74
74
74
74
16
16
16
16
16
16
68
68
16
16
69 79
68 74
17 75
16
16
16
16
16
70 71
17 75
16
36
16
13
15
15
15
15 74
15 74
74
17 75
17 75
17 75
17 75
17 75
15
74
15
13
70
36
16
16
16
16
74
67 74
6 67 74
70
71
68 74
69 79
69
69 79
6 67 74
67 74
9 72
6
69 79
6 67
6 67
17 75
66
44
44 62
62
16
18 22
51
7
7
7
7
16
68
74
74
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
BI
BI
BI
TEST7
TEST6
DSTBP1*
DINV1*
D31*
D30*
D25*
D11*
D12*
D13*
D14*
DSTBP0*
DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
D0* D32*
D1*
D2*
D5*
D16*
D20*
D21*
D22*
D23*
D24*
D26*
D27*
D28*
D29*
DSTBN1*
GTLREF
TEST3
TEST4
TEST5
BSEL0
BSEL1
BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
COMP0
COMP1
COMP2
COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
TEST2
TEST1
2 OF 4
D
A
T
A

G
R
P

3
D
A
T
A

G
R
P

2
MISC
D
A
T
A

G
R
P

0
D
A
T
A

G
R
P

1
LOCK*
INIT*
A20M*
A6*
A3*
A4*
A14*
A16*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20*
A21*
A22*
A23*
A24*
A26*
A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
RSVD5
RSVD6
RSVD7
RSVD8
1 OF 4
C
O
N
T
R
O
L
THERMAL
X
D
P
/
I
T
P

S
I
G
N
A
L
S
H CLK
A
D
D
R

G
R
O
U
P
1
I
C
H
R
E
S
E
R
V
E
D
A
D
D
R

G
R
O
U
P
0
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
CPU JTAG Support
R1023.1:
R1020.1:
R1021.1:
R1022.1:
PLACE_NEARs:
PLACE_NEARs:
R1006.1:
C1014.1:
R1005.2:
R1000
402
MF-LF
1/16W
1%
54.9
R1002
402
MF-LF
1/16W
5%
68
R1005
U1000.AD26:12.7 mm 402
MF-LF
1/16W
1%
1K
R1006
U1000.AD26:12.7 mm
402
MF-LF
1/16W
1%
2.0K
R1023
U1000.Y1:12.7 mm
54.9
1/16W
402
MF-LF
1%
R1022
U1000.AA1:12.7 mm
402
MF-LF
1/16W
1%
27.4
R1021
U1000.U26:12.7 mm
402
MF-LF
1/16W
1%
54.9
R1020
U1000.R26:12.7 mm
27.4
1/16W
402
MF-LF
1%
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
13 61 72
13 72
13 72
13 72
61
12 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
8 72
8 72
8 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
6 13 72
13 72
13 72
13 72
13 72
13 72
13 72
6 13 72
6 13 72
6 13 72
12 72
12 72
12 72
12 72
12 72
12 72
9 12 72
12 24
13 40 61 72
45 79
13 40 72
13 72
12 13 72
13 72
13 72
13 72
13 72
9 12 72
9 12 72
9 12 72
9 12 72
45 79
13 72
13 72
13 72
13 72
13 72
13 72
13 72
13 72
13 72
R1010
1/16W
NO STUFF
0
MF-LF
5%
402 R1011
NO STUFF
402
MF-LF
1/16W
5%
1K
R1001
402
MF-LF
1/16W
1%
54.9
R1090
54.9
1/16W
MF-LF
1%
402
R1091
54.9
1/16W
MF-LF
1%
402
R1093
54.9
1/16W
MF-LF
1%
402
6 13 72
6 13 72
6 13 72
6 13 72
R1094
649
1/16W
MF-LF
1%
402
R1012
NO STUFF
402
MF-LF
1/16W
5%
1K
C1014
16V
X5R
U1000.AF26:12.7 mm
NO STUFF
10%
402
0.1uF
U1000
FCBGA
PENRYN
OMIT
R1092
PLACE_NEAR=J1300.51:12.7 mm
1/16W
MF-LF
54.9
1%
402
U1000
OMIT
PENRYN
FCBGA
CPU FSB
SYNC_MASTER=T27_MLB SYNC_DATE=08/27/2009
FSB_D_L<16>
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
FSB_D_L<63>
CPU_COMP<0>
TP_CPU_RSVD_D3
TP_CPU_RSVD_D22
TP_CPU_RSVD_D2
TP_CPU_RSVD_F6
FSB_A_L<5>
FSB_A_L<15>
FSB_A_L<10>
FSB_ADS_L
CPU_IGNNE_L
CPU_THERMD_N
FSB_A_L<25>
FSB_A_L<11>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_BPRI_L
FSB_A_L<12>
FSB_A_L<13>
FSB_ADSTB_L<0>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
CPU_FERR_L
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
FSB_BNR_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_THERMD_P
PM_THRMTRIP_L
FSB_CLK_CPU_P
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_A_L<16>
FSB_A_L<14>
FSB_A_L<4>
FSB_A_L<3>
FSB_A_L<6>
CPU_A20M_L
CPU_INIT_L
FSB_LOCK_L
FSB_D_L<10>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<17>
CPU_PSI_L
FSB_CPUSLP_L
CPU_PWRGD
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
CPU_BSEL<2>
CPU_BSEL<1>
CPU_BSEL<0>
TP_CPU_TEST5
TP_CPU_TEST3
FSB_DSTB_L_N<1>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<5>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<32> FSB_D_L<0>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<25>
FSB_D_L<30>
FSB_D_L<31>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
TP_CPU_TEST6
TP_CPU_TEST7
CPU_IERR_L
XDP_BPM_L<5>
CPU_PROCHOT_L
XDP_TMS
XDP_TDI
CPU_GTLREF
XDP_TCK
XDP_TRST_L
=PP1V05_S0_CPU
XDP_BPM_L<0>
FSB_CLK_CPU_N
XDP_TDO
CPU_TEST2
CPU_TEST1
CPU_TEST4
FSB_D_L<43>
FSB_D_L<36>
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1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
1 2
1 2
1 2
1
2
2
1
C3
A26
M26
N24
N25
T25
P23
J23
H22
F26
K22
H26
H25
G24
K24
E23
E25
R23
P26
E22 Y22
F24
E26
G25
N22
L23
M24
L22
M23
P25
P22
T24
R24
L25
L26
AD26
C24
AF26
AF1
B22
B23
C21
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
K25
F23
G22
J26
H23
J24
D25
C23
1 2
H4
B3
A6
K5
J4
L5
P4
R1
K3
H2
K2
J3
L1
A21
A22
C7
A24
D21
C20
AB6
AB5
AB3
AA6
AC5
AC1
AC2
AC4
AD1
AD3
AD4
E4
G6
G2
G3
F4
F3
C1
D20
F1
E1
F21
H5
E2
B2
V3
T2
N5
M4
A3
B4
C6
D5
A5
V1
AA3
AB2
AA4
W3
V4
U2
Y4
W5
R3
U5
Y2
M1
L2
P2
G5
W6
U4
Y5
U1
R4
T3
W2
J1
N2
M3
P5
T5
B25
C4
H1
N3
P1
L4
F6
D2
D22
D3
72
72
72
72
72
9 12 72
9 12 72
28 72
9 12 72
9 12 72
7 10 11 12 61
9 12 72
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC
VCCP
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
VCC
3 OF 4
VSS VSS
4 OF 4
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Current numbers from Merom for Santa Rosa EMTS, doc #20905.
(Socket-P KEY)
(CPU CORE POWER)
44 A (SV Design Target)
41 A (SV HFM)
30.4 A (SV LFM)
23 A (LV Design Target)
(CPU IO POWER 1.05V)
4500 mA (before VCC stable)
2500 mA (after VCC stable)
(CPU INTERNAL PLL POWER 1.5V)
130 mA
(BR1#)
61 72
61 72
61 72
61 72
61 72
61 72
MF-LF
402
100
1%
1/16W
PLACE_NEAR=U1000.AE7:25.4 mm
R1101
61 72
61 72
61 72
OMIT
PENRYN
FCBGA
U1000
OMIT
PENRYN
FCBGA
U1000
100
1%
1/16W
MF-LF
402
PLACE_NEAR=U1000.AF7:25.4 mm
R1100
SYNC_DATE=07/20/2009 SYNC_MASTER=T27_MLB
CPU Power & Ground
CPU_VID<6>
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
CPU_VCCSENSE_P
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
=PPVCORE_S0_CPU
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1
2
AD15
AD17
AD18
C15
A7
A10
A13
A17
B15
B17
B20
C17
C18
D9
D12
D14
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
A9
A12
A15
B14
B18
C9
C10
C12
C13
D10
D15
D17
B12
B10
B7
A18
F17
B9
A20
N23
N26
B1
P3
E19
B19
A23
D16
D11
D4
D1
C25
C22
C2
T4
B8
A4
A8
A11
A14
A16
A19
AF2
B11
B13
B16
B21
B24
C5
C8
C11
C14
C16
C19
D8
D13
D26
E3
E6
E11
E14
E16
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L21
L24
M2
M5
M22
M25
N1
N4
P6
P21
P24
R2
R5
R22
R25
T1
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
E8
E21
L6
D23
D19
B6
1
2
7 11
7 9 11 12 61
7 10 11
7 10 11
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PLACEMENT_NOTE (C1240-C1243):
1x 330uF, 6x 0.1uF 0402
PLACEMENT_NOTE (C1200-C1219):
4X 330UF. 20X 22UF 0805
CPU VCore HF and Bulk Decoupling
VCCA (CPU AVdd) DECOUPLING
VCCP (CPU I/O) DECOUPLING
1x 10uF, 1x 0.01uF
C1260
20%
2.0V
POLY-TANT
D2T-SM2
330UF
CRITICAL
PLACEMENT_NOTE=Place C1260 between CPU & NB.
20%
X5R-CERM
NO STUFF
C1209
CRITICAL
22UF
6.3V
603
CPU_CAP:15&CPU_CAP:12
C1219
22UF
CRITICAL
X5R-CERM
6.3V
20%
603
CRITICAL
NO STUFF
6.3V
20%
X5R-CERM
603
22UF
C1208
6.3V
CRITICAL
603
X5R-CERM
20%
22UF
C1218
NO STUFF
603
X5R-CERM
20%
6.3V
22UF
CRITICAL
C1207
22UF
C1217
CRITICAL
6.3V
20%
X5R-CERM
603
X5R-CERM
CRITICAL
603
20%
6.3V
22UF
C1206
CRITICAL
603
X5R-CERM
22UF
C1216
CPU_CAP:15
6.3V
20%
22UF
C1205
6.3V
X5R-CERM
603
CRITICAL
CPU_CAP:15
20%
CRITICAL
6.3V
603
20%
C1215
X5R-CERM
22UF
603
NO STUFF
CRITICAL
X5R-CERM
22UF
C1204
6.3V
20%
6.3V
22UF
20%
603
X5R-CERM
C1214
CRITICAL
CRITICAL
C1243
D2T-SM
POLY-TANT
2.0V
20%
Place on secondary side.
470UF-4MOHM
C1213
CRITICAL
X5R-CERM
6.3V
22UF
20%
603
NO STUFF
C1203
20%
X5R-CERM
6.3V
22UF
603
CRITICAL
C1242
CRITICAL
POLY-TANT
2.0V
D2T-SM
20%
470UF-4MOHM
22UF
X5R-CERM
CRITICAL
6.3V
C1202
603
20%
C1212
6.3V
CRITICAL
603
20%
X5R-CERM
22UF
X5R-CERM
20%
NO STUFF
CRITICAL
22UF
C1201
603
6.3V
NO STUFF
CRITICAL
C1211
20%
6.3V
603
22UF
X5R-CERM
C1241
CRITICAL
POLY-TANT
2.0V
D2T-SM
20%
470UF-4MOHM
Place inside socket cavity on secondary side.
CRITICAL
C1200
22UF
6.3V
20%
603
X5R-CERM
603
C1210
CRITICAL
22UF
X5R-CERM
6.3V
20%
20%
2.0V
POLY-TANT
D2T-SM
CRITICAL
NO STUFF
C1240
470UF-4MOHM
CPU_CAP:15
C1222
20%
X5R-CERM
603
22UF
6.3V
CRITICAL
CRITICAL
20%
6.3V
X5R-CERM
603
22UF
C1221
NO STUFF
603
20%
6.3V
22UF
X5R-CERM
C1220
CRITICAL
C1261
20%
10V
CERM
402
0.1UF
C1262
20%
10V
CERM
402
0.1UF
C1263
20%
10V
CERM
402
0.1UF
C1264
20%
10V
CERM
402
0.1UF
C1265
20%
10V
CERM
402
0.1UF
C1266
20%
10V
CERM
402
0.1UF
BYPASS=U1000.B26::4 mm
10%
CERM
16V
402
0.01UF
C1251 C1250
20%
6.3V
X5R
603
10uF
CPU Decoupling
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
=PP1V5_S0_CPU
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1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
3 2
1
2
1
2
1
3 2
1
2
1
2
1
2
1
2
1
3 2
1
2
1
2
1
3 2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
7 10
7 9 10 12 61
7 10
IN
BI
BI
BI
BI
OUT
IN
BI
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
NC
IN
3 6
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REVISION
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OBSDATA_C1
OBSFN_C0
MCP89-specific pinout
Mini-XDP Connector
ITPCLK#/HOOK5
VCC_OBS_CD
XDP_PRESENT#
Use with 920-0620 adapter board to support CPU, MCP debugging.
OBSFN_A0
OBSFN_A1
OBSDATA_A0
OBSDATA_B1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
OBSFN_C1
OBSDATA_C2
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSDATA_B3
OBSFN_D1
PWRGD/HOOK0
OBSDATA_B2
TCK1
TMS
HOOK1
HOOK3
TRSTn
SDA
SCL
OBSFN_D0
RESET#/HOOK6
TDI
TDO
VCC_OBS_AB
NOTE: This is not the standard XDP pinout.
on even-numbered side of J1300
Please avoid any obstructions
DBR#/HOOK7
OBSDATA_C3
OBSDATA_C0
OBSDATA_A1
TCK0
Direction of XDP module
OBSDATA_D1
OBSDATA_D0
OBSFN_B1
OBSDATA_B0
OBSFN_B0
OBSDATA_A2
OBSDATA_A3
HOOK2
998-1571
9 13 72
R1399
1K
1/16W
5%
402
MF-LF
XDP
18 42 75
18 42 75
R1315
1/16W
1%
402
MF-LF
54.9
XDP
C1300
16V
10%
402
X5R
0.1uF
XDP
C1301
402
XDP
16V
10%
X5R
0.1uF
9 72
9 72
9 72
9 13 72
R1303
1/16W
5%
402
MF-LF
1K
XDP
PLACEMENT_NOTE=Place close to CPU to minimize stub.
9 72
9 72
9 72
9 72
18
18
18
18
18
13 72
13 72
9 72
9 72
9 72
9 72
9 24
18
J1300
CRITICAL
F-ST-SM
LTH-030-01-G-D-NOPEGS
XDP_CONN
eXtended Debug Port (mini-XDP)
FSB_CPURST_L
CPU_PWRGD
XDP_TMS
XDP_TDO
XDP_TRST_L
XDP_TDI
XDP_DBRESET_L
XDP_CPURST_L
FSB_CLK_ITP_N
TP_XDP_OBSDATA_D2
TP_XDP_OBSDATA_D0
TP_XDP_OBSDATA_D1
JTAG_MCP_TDI
TP_XDP_OBSDATA_C2
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B2
XDP_PWRGD
TP_XDP_OBSDATA_B3
XDP_OBS20
=PP1V05_S0_CPU
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
XDP_TCK
FSB_CLK_ITP_P
TP_XDP_OBSDATA_D3
JTAG_MCP_TMS
TP_XDP_OBSDATA_C3
=PP3V3_S0_XDP
TP_XDP_OBSDATA_C1
TP_XDP_OBSDATA_C0
JTAG_MCP_TRST_L
JTAG_MCP_TDO
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1
2
2
1
2
1
1 2
60
58
52
54
56
50
48
46
44
42
36
40
38
32
34
28
30
26
24
22
18
16
20
14
12
10
8
6
2
4 3
1
5
7
9
11
13
19
15
17
23
21
29
27
25
33
31
37
39
35
43
41
45
49
47
55
53
51
57
59
72
7 9 10 11 61
7
IN
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
CPU_A18*
CPU_D35*
CPU_D37*
CPU_A10*
CPU_A9*
CPU_D48*
CPU_A16*
CPU_D33*
CPU_RS2*
CPU_RS1*
CPU_RS0*
CPU_BSEL2
CPU_BSEL1
CPU_THERMTRIP*
CPU_PECI
CPU_PROCHOT*
CPU_DBSY*
CPU_ADSTB1*
CPU_REQ1*
CPU_REQ4*
CPU_BR0*
CPU_BNR*
CPU_ADS*
CPU_REQ2*
CPU_REQ3*
CPU_REQ0*
CPU_ADSTB0*
CPU_A31*
CPU_A32*
CPU_A30*
CPU_A28*
CPU_A26*
CPU_A27*
CPU_A23*
CPU_A24*
CPU_A25*
CPU_A21*
CPU_A22*
CPU_A19*
CPU_A20*
CPU_A13*
CPU_A14*
CPU_A12*
CPU_A11*
CPU_A8*
CPU_A5*
CPU_A6*
CPU_A7*
CPU_A3*
CPU_A4*
CPU_DSTBN0*
CPU_DBI0*
CPU_DSTBP1*
CPU_DSTBN1*
CPU_DBI1*
CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*
CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*
CPU_BSEL0
CPU_COMP_GND
BCLK_VML_COMP_VDD
CPU_COMP_VCC
BCLK_VML_COMP_GND
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D9*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D34*
CPU_D36*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*
CPU_A20M*
CPU_IGNNE*
CPU_INIT*
CPU_INTR
CPU_NMI
CPU_SMI*
CPU_PWRGD
CPU_RESET*
CPU_DPRSLPVR
CPU_SLP*
CPU_D10*
CPU_D8*
CPU_D7*
CPU_A33*
CPU_A34*
CPU_A35*
CPU_D44*
CPU_D43*
CPU_DSTBP0*
CPU_TRDY*
CPU_LOCK*
CPU_HIT*
CPU_DRDY*
CPU_HITM*
CPU_DPRSTP*
CPU_D0*
CPU_DPSLP*
CPU_DPWR*
CPU_STPCLK*
CPU_A15*
CPU_A17*
CPU_A29*
CPU_BPRI*
CPU_DEFER*
CPU_FERR*
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
BCLK_OUT_NB_N
BCLK_IN_N
BCLK_IN_P
BCLK_OUT_NB_P
(1 OF 11)
F
S
B
OUT
IN
IN
IN
IN
IN
IN
IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
Loop-back clock for delay matching.
8
8
8
9 72
9 12 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
6 9 72
9 72
9 72
9 72
9 72
9 72
9 72
12 72
12 72
9 72
9 72
9 72
9 72
9 72
9 72
9 72
9 72
9 12 72
9 72
9 72
9 72
9 72
9 61 72
8
9 40 61 72
9 40 72
6 9 72
6 9 72
1%
1/16W
MF-LF
402
49.9
R1436
49.9
MF-LF
402
1%
1/16W
R1431
1/16W
1%
402
MF-LF
49.9
R1430
402
MF-LF
1%
1/16W
49.9
R1435
5%
62
MF-LF
402
1/16W
R1415
1%
54.9
MF-LF
402
1/16W
R1410
150
1/16W
NO STUFF
402
MF-LF
5%
R1440
OMIT
MCP89M-A01
FBGA
U1400
61 72
6 9 72
6 9 72
9 72
9 72
9 72
9 72
6 9 72
MCP CPU Interface
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<39>
FSB_D_L<36>
FSB_D_L<33>
FSB_D_L<31>
FSB_D_L<0>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<10>
CPU_DPRSTP_L
CPU_STPCLK_L
FSB_DPWR_L
CPU_DPSLP_L
FSB_CPUSLP_L
PM_DPRSLPVR
FSB_CPURST_L
CPU_PWRGD
CPU_SMI_L
CPU_NMI
CPU_INTR
CPU_INIT_L
CPU_IGNNE_L
CPU_A20M_L
FSB_CLK_MCP_N
FSB_CLK_MCP_P
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_CPU_N
FSB_CLK_CPU_P
FSB_BPRI_L
FSB_DEFER_L
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<47>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<38>
FSB_D_L<34>
FSB_D_L<32>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<25>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<17>
FSB_D_L<16>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<9>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<1>
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_BCLK_VML_COMP_VDD
MCP_CPU_COMP_GND
=MCP_BSEL<0>
FSB_DINV_L<3>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<2>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<1>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<0>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_A_L<4>
FSB_A_L<3>
FSB_A_L<7>
FSB_A_L<6>
FSB_A_L<5>
FSB_A_L<8>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<15>
FSB_A_L<14>
FSB_A_L<13>
FSB_A_L<17>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<25>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<28>
FSB_A_L<30>
FSB_A_L<29>
FSB_A_L<33>
FSB_A_L<32>
FSB_A_L<31>
FSB_A_L<35>
FSB_A_L<34>
FSB_ADSTB_L<0>
FSB_REQ_L<0>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_REQ_L<4>
FSB_REQ_L<1>
FSB_ADSTB_L<1>
FSB_DBSY_L
FSB_DRDY_L
FSB_HITM_L
FSB_HIT_L
FSB_TRDY_L
FSB_LOCK_L
CPU_PROCHOT_L
CPU_PECI_MCP
CPU_FERR_L
PM_THRMTRIP_L
=MCP_BSEL<1>
=MCP_BSEL<2>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_A_L<16>
FSB_D_L<48>
FSB_A_L<9>
FSB_A_L<10>
FSB_D_L<37>
FSB_D_L<35>
FSB_A_L<18>
=PP1V05_S0_MCP_FSB
=PP1V05_S0_MCP_FSB
14 OF 109
A.13.0
051-8563
13 OF 80
1
2
1
2
1
2
1
2
1
2
1
2
1
2
AB35
L31
P32
Y38
T37
C37
Y35
G34
AC31
AC33
AB29
B34
C34
W33
AH34
U28
AE29
AB34
T36
T35
AE30
AE32
AE31
U37
T38
U36
W36
AC35
AE37
AC37
AE36
AB37
AC34
AC38
AB36
AB38
AC36
AF36
Y34
AE38
U33
W34
Y36
W35
W38
U35
T34
W37
U38
U34
K35
L37
T31
T30
P28
K33
K32
N35
C36
D36
A35
A34
AH35
AH37
AH36
AH38
N36
P36
L36
N34
L35
P37
L34
K36
K38
N37
H37
L38
N28
U30
N29
P34
T29
T32
U32
T33
P31
P30
N30
P33
N31
T28
P35
P29
H33
L30
L33
N32
N33
H35
K31
H34
G33
H32
G35
D37
H38
G38
G37
G36
B35
E35
B36
E36
C35
D34
E38
D38
E34
E37
W30
AB30
AB28
W31
AC30
AC28
Y32
AE28
G1
Y33
K37
H36
P38
AE35
AE33
AE34
L32
K30
K34
AC29
AC32
W32
U29
AB31
W29
N38
AB33
U31
Y29
Y37
AF38
AF37
Y31
Y30
AB32
AF33
AF32
AF34
AF35
AF28
AF31
AF30
AF29
72
72
72
72
72
72
7 13 19 22
7 13 19 22
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
MDQS0_7_P
MDQS0_6_N
MDQS0_6_P
MDQS0_7_N
MDQS0_5_N
MDQS0_5_P
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MRAS0*
MCAS0*
MWE0*
MBA0_2
MBA0_1
MBA0_0
MA0_14
MA0_15
MA0_13
MA0_12
MA0_11
MA0_9
MA0_10
MA0_8
MA0_7
MA0_6
MA0_3
MA0_4
MA0_1
MA0_2
MA0_0
+VIO_M2CLK_DLL_1
+VIO_M2CLK_DLL_2
+VIO_PLL_MEM_2
+VIO_PLL_MEM_1
+VIO_PLL_FSB_1
+VIO_PLL_FSB_2
MCLK0A_1_P
MCLK0A_1_N
MCLK0A_0_P
MCLK0A_0_N
MCS0A_1*
MCS0A_0*
MODT0A_0
MODT0A_1
MCKE0A_1
MCKE0A_0
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_58
MDQ0_59
MDQ0_55
MDQ0_57
MDQ0_56
MDQ0_53
MDQ0_54
MDQ0_50
MDQ0_52
MDQ0_51
MDQ0_48
MDQ0_49
MDQ0_45
MDQ0_46
MDQ0_47
MDQ0_43
MDQ0_44
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_37
MDQ0_38
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_27
MDQ0_28
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_22
MDQ0_23
MDQ0_19
MDQ0_21
MDQ0_20
MDQ0_17
MDQ0_18
MDQ0_16
MDQ0_14
MDQ0_15
MDQ0_12
MDQ0_13
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_5
MDQ0_6
MDQ0_4
MDQ0_2
MDQ0_3
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_2
MDQM0_3
MDQM0_0
MDQM0_1
MDQ0_42
MA0_5
+VIO_PLL_CPU_4
+VIO_PLL_CPU_3
+VIO_PLL_CPU_2
+VIO_PLL_CPU_1
MDQS0_3_N
MDQ0_60
M
E
M
O
R
Y

P
A
R
T
I
T
I
O
N

0
(2 OF 11)
MDQ1_51
MDQ1_13
MDQ1_25
MDQ1_39
MEM_COMP_VDD
MEM_COMP_GND
MDQM1_1
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_38
MDQ1_10
MDQ1_16
MDQ1_14
MDQ1_3
MDQ1_2
MDQ1_1
MDQM1_2
MDQM1_3
MDQM1_4
MDQM1_5
MDQM1_6
MDQM1_7
MDQS1_6_N
MDQS1_7_N
MDQS1_7_P
MDQ1_0
MDQ1_4
MDQ1_5
MDQ1_6
MDQ1_7
MDQ1_8
MDQ1_9
MDQ1_11
MDQ1_12
MDQ1_15
MDQ1_17
MDQ1_18
MDQ1_21
MDQ1_22
MDQ1_23
MDQ1_24
MDQ1_26
MDQ1_27
MDQ1_28
MDQ1_29
MDQ1_30
MDQ1_31
MDQ1_32
MDQ1_33
MDQ1_34
MDQ1_35
MDQ1_36
MDQ1_37
MDQ1_46
MDQ1_47
MDQ1_48
MDQ1_52
MDQ1_53
MDQ1_54
MDQ1_56
MDQ1_57
MDQ1_58
MDQ1_59
MDQ1_60
MDQ1_61
MDQ1_62
MDQ1_49
MDQS1_6_P
MDQ1_63
MDQ1_50
MDQM1_0
MDQ1_45
MDQ1_55
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_N
MDQS1_0_P
MRAS1*
MCAS1*
MWE1*
MBA1_2
MBA1_1
MBA1_0
MA1_15
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_4
MA1_5
MA1_3
MRESET0*
MCLK1A_1_P
MCLK1A_1_N
MCLK1A_0_P
MCLK1A_0_N
MCS1A_1*
MCS1A_0*
MODT1A_1
MODT1A_0
MCKE1A_1
MCKE1A_0
MA1_1
MA1_0
MA1_2
MDQ1_19
MDQ1_20
M
E
M
O
R
Y

P
A
R
T
I
T
I
O
N

1
(3 OF 11)
OUT
OUT
OUT
OUT
OUT
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
20 mA
25 mA
25 mA
70 mA
550 mA
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
25 73
20 25 73
20 25 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
26 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
27 73
25 73 26 73
20 26 73
20 26 73
MCP89M-A01
FBGA
OMIT
U1400
FBGA
MCP89M-A01
OMIT
U1400
26 73
26 73
26 73
26 73
25 26
1K
MF-LF
1/16W
402
5%
R1520
MF-LF
40.2
1/16W
1%
402
R1511
1%
40.2
1/16W
402
MF-LF
R1510
MCP Memory Interface
MEM_A_DQS_N<6>
MEM_A_A<7>
PP1V05_S0_MCP_PLL_FSBMEM
MEM_B_DQ<9>
MEM_B_DQ<29>
MEM_A_A<5>
MEM_A_A<6>
MEM_B_DQ<27>
MEM_A_DQ<39>
MEM_A_WE_L
MEM_RESET_L
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CLK_P<0>
MEM_B_DQ<51>
MEM_B_DQ<13>
MEM_B_CS_L<1>
MEM_B_DQ<25>
MEM_B_DQ<39>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
MEM_B_DM<1>
MEM_B_DM<0>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<38>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_DQ<10>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<16>
MEM_B_DQ<14>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_CS_L<0>
MEM_B_CLK_N<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQ<0>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<26>
MEM_B_DQ<28>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<50>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQ<49>
MEM_B_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_BA<0>
MEM_A_A<13>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<12>
MEM_A_A<10>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_DQ<31>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<63>
MEM_A_DM<0>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQ<0>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<8>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<28>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<62>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_P<4>
MEM_A_DQS_N<5>
=PP1V5R1V35_S3_MCP_MEM
MEM_A_A<0>
MEM_A_A<11>
MEM_A_A<9>
MEM_B_DQ<15>
MEM_A_A<3>
=PP1V5R1V35_SW_MCP_MEM
MEM_A_A<8>
15 OF 109
A.13.0
051-8563
14 OF 80
AN7
AM10
AN10
AM7
AM13
AN13
AL16
AK16
AH28
AM29
AN29
AP34
AP35
AH31
AG31
AN19
AL19
AL20
AL25
AN20
AM19
AK25
AK26
AJ20
AJ26
AH25
AH26
AM20
AN23
AJ25
AM22
AL23
AN22
AK23
AK22
AL22
AF24
AG25
AG26
AF25
AF26
AG28
AH23
AJ23
AJ22
AH22
AH19
AK20
AK19
AH20
AL26
AN25
AP5
AP7
AR8
AR5
AR4
AK11
AM8
AN8
AH13
AL11
AK10
AH14
AL10
AJ13
AN11
AJ16
AK14
AK13
AJ14
AH16
AM14
AN14
AK17
AN17
AL17
AJ19
AH17
AJ17
AM16
AM17
AN26
AH29
AK29
AM25
AL29
AM26
AL28
AK28
AP29
AM28
AP28
AL31
AN32
AN31
AN28
AM31
AM32
AR34
AL35
AL33
AP32
AP33
AM35
AL32
AJ35
AH32
AJ31
AH33
AL34
AJ34
AJ33
AJ32
AR7
AM11
AL14
AN16
AP31
AJ29
AJ30
AM34
AL13
AM23
AF27
AE26
AD26
AC26
AJ28
AP8
AV5
AR37
AV28
AV14
AG22
AG23
AT37
AR14
AR11
AP11
AT11
AP13
AU14
AU35
AT32
AT35
AP37
AP36
AJ38
AV32
AR28
AT14
AV10
AU7
AT2
AV8
AR1
AR2
AJ37
AL36
AJ36
AM37
AM36
AR38
AR36
AV34
AP38
AV35
AU32
AR31
AT34
AR32
AT31
AV29
AV26
AV25
AT29
AU29
AT26
AU26
AR16
AP16
AT13
AP14
AP17
AR17
AU10
AT10
AT8
AR10
AU8
AT7
AT4
AU3
AP2
AP3
AU4
AV4
AR3
AP10
AV7
AP1
AU5
AM38
AR13
AT5
AU11
AV11
AU13
AV13
AT28
AU28
AU31
AV31
AU36
AT36
AL37
AL38
AR19
AU17
AT17
AR25
AT19
AR20
AP26
AR26
AV16
AP25
AT23
AP20
AU23
AV22
AV23
AT22
AP23
AU22
AR23
AP4
AU20
AV20
AU19
AV19
AU16
AP19
AT16
AV17
AU25
AT25
AR22
AT20
AP22
AR29
AU34
1
2
1
2
1
2
22
7 22
73
73
7
19 20 22
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PE0_REFCLK_P
PE0_REFCLK_N
PE1_REFCLK_P
PE2_REFCLK_P
PE1_REFCLK_N
PE3_REFCLK_P
PE2_REFCLK_N
PE4_REFCLK_P
PE3_REFCLK_N
PE5_REFCLK_P
PE4_REFCLK_N
PE5_REFCLK_N
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX3_P
PE0_TX2_N
PE0_TX4_P
PE0_TX3_N
PE0_TX5_P
PE0_TX4_N
PE0_TX5_N
PE1_TX0_N
PE1_TX0_P
PE1_TX1_P
PE1_TX1_N
PEX_RST*
PEX0_TERM_P
PEA_CLKREQ*/GPIO_49
PEB_CLKREQ*/GPIO_50
PEC_CLKREQ*/GPIO_51
PEE_CLKREQ*/GPIO_53
PED_CLKREQ*/GPIO_52
PEF_CLKREQ*/GPIO_54
PE_WAKE*
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX3_P
PE0_RX4_P
PE0_RX3_N
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE1_RX0_P
PE1_RX0_N
PE1_RX1_N
PE1_RX1_P
+3.3V_PLL_HVDD_1
+3.3V_PLL_HVDD_2
+VIO_PLL_PE
+VIO_PLL_XREF_XS_1
+VIO_PLL_XREF_XS_2
+VIO_PLL_SATA_1
+VIO_PLL_XREF_XS_3
+VIO_PLL_SATA_2
+VIO_PLL_H
PE0_RX2_N
PE0_RX2_P
P
C
I

E
X
P
R
E
S
S
(4 OF 11)
OUT
IN
OUT
OUT
IN
IN
IN
OUT
OUT
IN
OUT
OUT
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
PE1 ports are Gen1-only. 2 RCs: x1, x1
PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
If PE0[3:0] are not used,
+VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
If PE0[4:5] and PE1[0:1] are not used,
(IPU-S5)
50 mA
100 mA
120 mA
25 mA
80 mA
325 mA
(IPU)
(IPD)
R1610
2.49K
1%
1/16W
MF-LF
402
PLACE_NEAR=U1400.U2:12.7 mm
31 74
31 74
6 29 74
6 29 74
6 24 29
34
29
8
8
8
8
8
8
8
8
29 74
29 74
18 24
33 74
33 74
29 74
29 74
8 74
8 74
8
8
8
8
8
8
8
8
U1400
OMIT
MCP89M-A01
FBGA
34
8
31 74
31 74
31
33 74
33 74
33 74
33 74
34
31 74
31 74
R1600
10K
5%
402
MF-LF
1/16W
NO STUFF
MCP PCIe Interfaces
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
TP_PCIE_PE4_D2RP
PCIE_FW_R2D_C_N
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_N
=PEG_R2D_C_P<1>
PP3V3_S0_MCP_PLL_HVDD
PCIE_ENET_D2R_N
PCIE_FW_D2R_P
PCIE_WAKE_L
=PEG_R2D_C_P<0>
TP_PCIE_CLK100M_PE4N
FW_CLKREQ_L
MCP_PEX0_TERMP
PCIE_AP_R2D_C_P
=PEG_R2D_C_P<2>
TP_PCIE_CLK100M_PE5P
PCIE_CLK100M_FW_P
PCIE_ENET_D2R_P
TP_PCIE_PE4_D2RN
=PEG_D2R_P<2>
=PEG_D2R_N<1>
=PEG_D2R_P<1>
=PEG_D2R_N<0>
=PEG_D2R_P<0>
PEG_CLKREQ_L
TP_PCIE_PE4_R2D_CP
PCIE_ENET_R2D_C_P
TP_PCIE_PE4_R2D_CN
PEG_CLK100M_P
PEG_CLK100M_N
AP_CLKREQ_L
PCIE_FW_D2R_N
PCIE_FW_R2D_C_P
FW_PME_L
PCIE_AP_D2R_P
TP_PCIE_CLK100M_PE4P
PCIE_AP_D2R_N
PP1V05_S0_MCP_PLL_PEXSATA
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<1>
ENET_CLKREQ_L
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<3>
PCIE_CLK100M_FW_N
FW_PWR_EN
PCIE_CLK100M_AP_P
PCIE_CLK100M_ENET_P
TP_PCIE_CLK100M_PE5N
PCIE_AP_R2D_C_N
PCIE_ENET_R2D_C_N
PCIE_RESET_L
16 OF 109
A.13.0
051-8563
15 OF 80
1
2
Y1
W1
W3
U4
W2
U7
U5
U9
U6
W10
U8
W11
AC3
AC2
AB2
AB3
AC6
AC8
AC7
AB4
AC9
Y5
AB5
Y4
Y6
Y7
Y9
Y8
U1
U2
W4
W5
W7
W6
W8
W9
U3
AC1
AB1
AC5
AC4
AB7
AB9
AB6
AB8
Y2
Y3
AB11
AB10
Y11
Y10
V11
V13
AH10
AG11
AF12
AH8
AF13
AH9
AH11
AC11
AC10
1
2
22
74
22
OUT
IN
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
F
L
A
T

P
A
N
E
L
R
G
B
(5 OF 11)
+3.3V_RGBDAC
DDC_DATA0/GPIO_39
DDC_CLK0/GPIO_38
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_HSYNC
RGB_DAC_BLUE
RGB_DAC_VSYNC
RGB_DAC_RSET
RGB_DAC_VREF
IFPA_TXC_P
IFPA_TXD0_P
IFPA_TXC_N
IFPA_TXD0_N
DP0_3_P/TMDS0_TXC_P
DP0_3_N/TMDS0_TXC_N
DP0_2_N/TMDS0_TX0_N
DDC_CLK3/DP_AUX_CH1_P
DDC_DATA3/DP_AUX_CH1_N
DP0_1_P/TMDS0_TX1_P
DP0_1_N/TMDS0_TX1_N
DP0_0_P/TMDS0_TX2_P
DP0_0_N/TMDS0_TX2_N
DP1_3_P/TMDS0B_TXC_P
DP1_3_N/TMDS0B_TXC_N
DP1_2_P/TMDS0_TX3_P
DP1_2_N/TMDS0_TX3_N
DP1_1_P/TMDS0_TX4_P
DP1_1_N/TMDS0_TX4_N
DP1_0_P/TMDS0_TX5_P
DP1_0_N/TMDS0_TX5_N
HPLUG_DET0/GPIO_20
HPLUG_DET1/GPIO_21
HPLUG_DET2/GPIO_22
DDC_CLK2/DP_AUX_CH0_P
DDC_DATA2/DP_AUX_CH0_N
+3.3V_PLL_DP0_1
+VIO_PLL_IFPAB_1
+3.3V_PLL_USB_2
+VIO_PLL_IFPAB_2
+VIO_PLL_SPPLL0_1
+VIO_PLL_CORE_LEG
+VIO_PLL_SPPLL0_2
+VIO_PLL_NV_1
+VIO_PLL_V
+VDD_IFPA
+VIO_PLL_NV_2
+VDD_IFPB
+VIO_DP0_1
+VIO_DP0_2
+VIO_DP0_3
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
DDC_CLK1/GPIO_40
DDC_DATA1/GPIO_41
TMDS0_RSET
TMDS0_VPROBE
IFPAB_RSET
IFPAB_VPROBE
+3.3V_PLL_USB_1
+3.3V_PLL_DP0_2
DP0_2_P/TMDS0_TX0_P
LCD_PANEL_PWR/GPIO_58
LCD_BKL_ON/GPIO_59
LCD_BKL_CTL/GPIO_57 OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
140 mA
LVDS: Power +VDD_IFPx at 1.8V
=MCP_IFPAB_DDC_DATA
=MCP_IFPA_TXC_P/N
=MCP_IFPAB_DDC_CLK
=MCP_IFPB_TXD_P/N<3>
=MCP_IFPB_TXC_P/N
=MCP_IFPA_TXD_P/N<3>
(UNUSED)
(UNUSED)
(UNUSED)
MCP Signal TMDS/HDMI
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_TXD_P/N<5>
TMDS_IG_TXD_P/N<4>
TMDS_IG_TXD_P/N<3>
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<2>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<0>
Interface Mode
LVDS_IG_A_CLK_P/N
LVDS_IG_A_DATA_P/N<0>
LVDS_IG_B_CLK_P/N
LVDS_IG_B_DATA_P/N<0>
LVDS_IG_DDC_DATA
LVDS_IG_DDC_CLK
LVDS
NOTE: No Composite/S-Video/Component Video support on MCP89
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).
(GMUX_INT)
160 mA
Connect +3.3V_RGBDAC pin to GND.
RGB DAC Disable:
TMDS: Power +VDD_IFPx at 3.3V
180 mA
30 mA
210 mA
60 mA
40 mA
60 mA
40 mA
20 mA
180 mA
NOTE: 100K pull-downs required if
HPLUG_DET0/HPLUG_DET1 are not used.
GPIO Pull-Ups
DDC Mode Pull-downs
NOTE: DP_AUX_CH1 also requires pull-downs if used for
dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
only pull-ups are necessary.
160 mA
16 36
8
8
8 16
8
8
8
8
8
8
8
8
23 74
23 74
8
8
8
8
8
8
8
8
8
8
8
8
FBGA
MCP89M-A01
OMIT
U1400
8
8
67
23 74
23 74
8
8
8
8
8
8
8
8
8 16
8
8
8
8
8
8
8
8
8
8
8
8
16 56
16
5% 1/16W 402 MF-LF
10K R1782
10K
MF-LF 402 1/16W 5%
R1781
10K
MF-LF 402 1/16W 5%
R1780
MF-LF 402 1/16W 5%
100K R1711
MF-LF 402 1/16W 5%
100K R1710
MCP Graphics
DP_IG_ML0_P<3>
DP_IG_AUX_CH0_P
DP_IG_AUX_CH0_N
SATARDRVR_A_EN
AUD_IP_PERIPHERAL_DET
=PP3V3_S0_MCP_GPIO
MIKEY_MIC_LOAD_DET
DP_IG_AUX_CH0_N
DP_IG_AUX_CH0_P
DP_IG_AUX_CH1_P
SATARDRVR_A_EN
DP_IG_HPD1
TP_MCP_RGB_VSYNC
=MCP_IFPA_TXD_P<0>
DP_IG_ML1_P<0>
DP_IG_ML0_N<0>
PP3V3_S0_MCP_DAC
PP1V05_S0_MCP_PLL_CORE
DP_IG_HPD0
=MCP_IFPAB_DDC_DATA
MCP_IFPAB_VPROBE
=MCP_IFPB_TXD_P<0>
TP_MCP_RGB_DAC_VREF
DP_IG_ML0_N<3>
DP_IG_ML0_N<2>
DP_IG_ML0_N<1>
DP_IG_ML0_P<2>
DP_IG_ML1_P<2>
DP_IG_ML1_P<1>
DP_IG_ML1_N<2>
DP_IG_ML1_P<3>
TP_MCP_RGB_RED
TP_MCP_RGB_HSYNC
TP_MCP_RGB_GREEN
LCD_IG_BKLT_EN
=MCP_IFPB_TXD_N<3>
=MCP_IFPB_TXD_N<0>
=MCP_IFPB_TXD_P<1>
=MCP_IFPB_TXC_P
=MCP_IFPA_TXD_N<3>
=MCP_IFPA_TXD_P<3>
=MCP_IFPA_TXD_N<2>
=MCP_IFPA_TXD_P<2>
=MCP_IFPA_TXC_P
=MCP_IFPA_TXC_N
MIKEY_MIC_LOAD_DET
AUD_IP_PERIPHERAL_DET
MCP_IFPAB_RSET
MCP_TMDS0_RSET
DP_IG_ML1_N<1>
MCP_TMDS0_VPROBE
=MCP_IFPB_TXD_P<3>
=MCP_IFPAB_DDC_CLK
DP_IG_ML1_N<3>
DP_IG_ML0_P<1>
DP_IG_ML0_P<0>
LCD_IG_BKLT_PWM
LCD_IG_PWR_EN
=MCP_IFPB_TXC_N
=MCP_IFPB_TXD_N<1>
=MCP_IFPB_TXD_P<2>
=MCP_IFPB_TXD_N<2>
=MCP_IFPA_TXD_N<0>
=MCP_IFPA_TXD_N<1>
TP_MCP_RGB_BLUE
=MCP_IFPA_TXD_P<1>
DP_IG_ML1_N<0>
DP_IG_AUX_CH1_N
PP3V3_S0_MCP_PLL_DP_USB
TP_MCP_RGB_DAC_RSET
17 OF 109
A.13.0
051-8563
16 OF 80
B29
H25
F29
C31
B31
D31
A31
E31
C29
D29
K22
C22
L22
B22
D26
E26
F26
K25
K26
F25
G25
E25
D25
F28
G28
E28
D28
A28
A29
C28
B28
H26
J26
J25
L28
K28
M23
N23
M22
L24
N25
M25
L26
N24
M26
A22
L25
A23
A26
B26
C26
E22
D22
F22
G22
H22
J22
B23
C23
L23
K23
J23
H23
G23
F23
D23
E23
J28
G29
F31
H28
K20
L20
N21
N22
G26
C25
B25
A25
1 2
1 2
1 2
1 2
1 2 8 16
8 16
16 36
16 56
7 17 18
16
8
23
7 23
22
7 23
8
8
8
8
7 23
8
22
8
IN
BI
IN
IN
IN
IN
IN
IN
USB0_N
USB0_P
SATA_A0_RX_N
SATA_A1_TX_P
SATA_A1_TX_N
USB4_N
SATA_A0_RX_P
USB1_P
USB1_N
USB2_P
USB2_N
USB3_N
USB3_P
USB4_P
USB5_P
USB5_N
USB6_P
USB6_N
USB7_P
USB7_N
USB8_N
USB9_N
USB9_P
USB10_N
USB10_P
USB_OC3*/GPIO_28_MGPIO_1
USB_RBIAS_GND
RGMII_VREF
RGMII_TXD1
RGMII_TXD0
RGMII_TXD3
RGMII_TXD2
RGMII_TXCLK
RGMII_TXCTL
RGMII_MDC
RGMII_MDIO
BUF_25MHZ
RGMII_RESET*
SATA_A0_TX_P
SATA_A0_TX_N
SATA_A1_RX_P
SATA_A1_RX_N
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_LED*/GPIO_30
SATA_TERMP
NC_1
NC_2
NC_4
NC_3
RGMII_RXD1
RGMII_RXD0
RGMII_RXD2
RGMII_RXD3
RGMII_RXCLK
RGMII_RXCTL
RGMII_INTR/GPIO_35
+3.3V_PLL_MAC_DUAL
RGMII_COMP_VDD
RGMII_COMP_GND
USB8_P
USB_OC2*/GPIO_27_MGPIO_0
USB_OC1*/GPIO_26
USB_OC0*/GPIO_25
USB11_P
USB11_N
L
A
N
S
A
T
A
U
S
B
(6 OF 11)
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
NC
NC
NC
NC
IN
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
Internal MAC Disable:
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_MDIO to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
20 mA
External A
Bluetooth
IR
All other pins can be left TP or NC.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_RXCLK to 10K pull-down.
T57
Connect RGMII_RXD<0:3> together to 10K pull-down.
OC2# Also for EXTE
OC3# Also for EXCARD
External B
External D
O
H
C
I
0
/
E
H
C
I
0
O
H
C
I
1
/
E
H
C
I
1
U
S
B

J
T
A
G

i
n

S
3
/
S
4
/
S
5
.
O
n
l
y

U
S
B
8
-
1
1

s
u
p
p
o
r
t

n
V
Geyser Trackpad/Keyboard
Watermelon
SD Card/ExpressCard
Camera/External E
AirPort (PCIe Mini-Card)
I
n
t
e
r
n
a
l

1
9
.
5
K

P
u
l
l
-
D
o
w
n
s

o
n

a
l
l

U
S
B

p
a
i
r
s
External C
8
8 76
8 76
8 76
8 76
8 76
8 76
8 76
R1810
1%
1/16W
MF-LF
402
49.9
R1811
1%
402
49.9
MF-LF
1/16W
MCP89M-A01
FBGA
U1400
OMIT
29 75
29 75
37 75
37 75
47 75
47 75
8 75
8 75
30 75
30 75
MF-LF
R1850
402
5%
8.2K
1/16W
R1851
1/16W
5%
8.2K
402
MF-LF
R1852
1/16W
MF-LF
402
5%
8.2K
R1853
5%
MF-LF
1/16W
402
8.2K
29 75
29 75
8 75
8 75
8 75
8 75
8 75
8 75
37 75
37 75
887
1/16W
1%
MF-LF
402
R1860
36 74
36 74
36 74
36 74
36 74
36 74
36 74
36 74
R1805
MF-LF
1%
402
1/16W
2.49K
31
38 75
38 75
R1800
5%
100K
402
MF-LF
1/16W
MCP SATA, USB & Ethernet
NC_USB_T57_P
NC_USB_T57_N
USB_EXTC_P
USB_WM_P
USB_WM_N
USB_CAMERA_N
USB_CAMERA_P
USB_EXTA_P
USB_EXTA_N
USB_MINI_N
USB_EXTC_N
USB_EXTA_OC_L
USB_EXTD_OC_L
USB_EXTB_OC_L
MCP_USB_RBIAS_GND
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
SATA_HDD_D2R_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_HDD_D2R_P
USB_MINI_P
USB_SDCARD_P
USB_SDCARD_N
USB_EXTD_P
USB_EXTD_N
USB_TPAD_N
USB_EXTB_N
USB_EXTB_P
USB_IR_N
USB_IR_P
MCP_RGMII_VREF
TP_ENET_TXD<1>
TP_ENET_TXD<0>
TP_ENET_TXD<3>
TP_ENET_TXD<2>
TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL
TP_ENET_MDC
ENET_MDIO
TP_MCP_CLK25M_BUF0_R
TP_ENET_RESET_L
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
TP_SATA_C_D2RN
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
MXM_GOOD_L
MCP_SATA_TERMP
ENET_RXD<1>
ENET_RXD<0>
ENET_RXD<2>
ENET_RXD<3>
ENET_CLK125M_RXCLK
ENET_RX_CTRL
ENET_ENERGY_DET
PP3V3_ENET_MCP_PLL_MAC
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
USB_TPAD_P
USB_EXTC_OC_L
USB_BT_P
USB_BT_N
=PP3V3_S5_MCP_GPIO
=PP3V3_S0_MCP_GPIO
18 OF 109
A.13.0
051-8563
17 OF 80
1
2
1
2
C20
B20
AJ4
AJ3
AJ2
D20
AJ5
J20
H20
C19
B19
F20
G20
E20
E19
D19
G19
F19
J17
H17
H19
B17
C17
D17
E17
K19
L19
C13
H13
G13
D14
F14
G14
E14
F13
K13
J13
J14
AH4
AH5
AH3
AH2
AJ6
AJ7
AH7
AH6
AL4
AL3
AL1
AL2
AH1
AJ1
G4
E7
F4
F7
C14
B14
D16
F16
E16
A14
H14
M16
D13
E13
J19
K17
L17
A17
F17
G17
1
2
1
2
1
2
1
2
1
2
1
2
1
2
37
37
75
74
22
76
76
7 18
7 16 18
7 19 22
OUT
OUT
IN OUT
HDA_SDATA_OUT
HDA_BITCLK
HDA_RESET*
HDA_SYNC
LPC_SERIRQ
LPC_FRAME*
LPC_RESET*
LPC_CLK0
MISC_VDDEN0/GPIO_47
MISC_VDDEN1/GPIO_48
MISC_VDDEN4/GPIO_19
MISC_VDDEN3/GPIO_18
MISC_VDDEN2/GPIO_17
MEM_VDD_SEL/GPIO_46
FANCTL0/GPIO_61
FANRPM0/GPIO_60/MGPIO_2
FANCTL1/GPIO_62
SLP_S3*
FANRPM1/GPIO_63/MGPIO_3
SLP_S5*
SLP_RMGT*
MCP_VID0/GPIO_13
MCP_VID2/GPIO_15
MCP_VID1/GPIO_14
SPI_CS0*/GPIO_10
SPI_DI/GPIO_08
SPI_DO/GPIO_09
SPI_CLK/GPIO_11
SPKR/GPIO_1
THERM_DIODE_N
THERM_DIODE_P
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_CLK0
SMB_ALERT*/GPIO_64
SMB_DATA1/MSMB_DATA
SUS_CLK/GPIO_34
BUF_SIO_CLK/GPIO_33
PKG_TEST
TEST_MODE_EN
PKG_TEST2
+VDD_HDA
HDA_SDATA_IN0
HDA_PULLDN_COMP
HDA_SDATA_IN1/GPIO_2
LPC_AD1
LPC_AD0
LPC_DRQ0*/GPIO_43
LPC_AD3
LPC_AD2
LPC_CLKRUN*/GPIO_42
EXT_SMI*/GPIO_32
SIO_PME*/GPIO_31
A20GATE/GPIO_55
KBRDRSTIN*/GPIO_56
RSTBTN*
PWRBTN*
RTC_RST*
PWRGD_SB
PWRGD
MCP_WAKE_REQ*
MCP_MEMVDD_EN/GPIO_44
MEMVTT_EN/GPIO_45
INTRUDER*
MGPU_PIO1/GPIO_7
MGPU_PIO0/GPIO_6
MGPU_PIO3/GPIO_24
MGPU_PIO2/GPIO_23
JTAG_TDO
JTAG_TDI
JTAG_TRST*
JTAG_TCK
JTAG_TMS
XTALIN
XTALIN_RTC
XTALOUT
XTALOUT_RTC
MCP_VID3/GPIO_16
MCP_WAKE_DIS*
M
I
S
C
L
P
C
(7 OF 11)
H
D
A
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
BI
OUT
OUT
BI
BI
BI
BI
OUT
IN
IN
BI
OUT
OUT
IN
IN
OUT
OUT
IN
BI
OUT
OUT
BI
IN OUT
OUT IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
not use LPC for BootROM override.
LPC ROMs. So Apple designs will
NOTE: MCP89 does not support FWH, only
these pins.
NOTE: MCP89 A01 has strong (~10K)
pull-downs on these pins.
HDA Output Caps
(IPD)
(IPD)
For EMI Reduction on HDA interface
Confirmed OK for this signal.
(IPD)
(
I
P
U
-
S
5
)
(IPU)
Platform-Specific Connections
(IPD)
MCP_SPKR:
0 = USER mode (Normal boot mode)
1 = SAFE mode (For ROMSIP recovery)
70 mA
behavior of Intels SLP_S4# signal.
NOTE: MCP SLP_S5# signal has the
(IPU)
SPI
1
(IPU-S5)
BUF_SIO_CLK Frequency
SPI_CLK
I/F
HDA_SYNC
1
0
(IPU)
(IPU)
(IPD)
(IPU)
(IPU-S5)
LPC
LPC_FRAME#
0
BIOS Boot Select
Frequency
0
SPI_DO
1
SPI Frequency Select
1
1
0
0
14.31818 MHz
24 MHz
Frequency
0
1
(IPU)
(IPU)
(IPU)
(IPD)
70 mA
(IPD)
(
I
P
U
)
(IPU-S5)
pull-downs on
strong (~10K)
(IPU)
NOTE: MCP89 A01 has
Connects to SMC for automatic recovery.
25.0 MHz
31.2 MHz
42.7 MHz
62.5 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.
Output limited to +VDD_HDA.
GPIO Pull-Ups/Downs
39 41 75
18 24 75
39 41 24 75
1
2
R1961
MF-LF
1/16W
5%
10K
402
OMIT
U1400
FBGA
MCP89M-A01
R1953
22
5%
402
1/16W
MF-LF
51 75
R1952
22
1/16W
5%
402
MF-LF
R1951
5%
22
1/16W
MF-LF
402
R1950
1/16W
22
402
5%
MF-LF
51 75
51 75
51 75
R1900
49.9
MF-LF
1/16W
1%
402
51 75
24
24
24
24
39
39
12
24
18 62
18 62
18 62
18 62
45 79
45 79
6 18 39 40 65
65
6 39 65 69
41 75
6 18 41 75
41 75
41 75
R1970
402
5%
10K
MF-LF
1/16W
40
R1959
10K
402
5%
MF-LF
1/16W
R1975
402
1/16W
1%
MF-LF
1K
24 75
18 29 65
42 75
42 75
12 42 75
12 42 75
R1930
402
1/16W
MF-LF
5%
10K
R1931
402
5%
1/16W
MF-LF
100K
12
12
12
12
12
24
39
39
40
R1920
1/16W
402
MF-LF
49.9K
1%
R1921
49.9K
402
1%
1/16W
MF-LF
C1951
10PF
CERM
402
5%
50V
C1950
402
5%
10PF
50V
CERM
C1953
CERM
402
5%
10PF
50V
402
C1952
50V
CERM
5%
10PF
39 41
20
20 65
R1960
1/16W
22
402
5%
MF-LF
R1910
402
22
5% 1/16W MF-LF
R1912
5%
22
1/16W MF-LF 402
R1911
402 MF-LF 1/16W
22
5%
R1913
5%
22
1/16W MF-LF 402
39 41 75
39 41 75
39 41 75
39 41 75
56
39
56
6 18 41 50
18 21
6 18
18 25 26 39
18 30
18 36
8 18 31
39 40 65
6 18
60
18 40
R1985
402
100K
1/16W MF-LF 5%
R1996
5% 1/16W 402 MF-LF
10K
R1988 10K
MF-LF 1/16W 5% 402
10K R1980
MF-LF 5% 1/16W 402
R1987
5% 1/16W 402 MF-LF
100K
R1990 10K
5% 1/16W MF-LF 402
R1991 10K
1/16W MF-LF 402 5%
R1989
5% 1/16W 402 MF-LF
10K
R1997 100K
5% 1/16W 402 MF-LF
R1981 10K
MF-LF 402 1/16W 5%
R1992 100K
402 5% 1/16W MF-LF
R1993
402 5% 1/16W MF-LF
100K
R1994
402 5% 1/16W MF-LF
100K
R1995 100K
MF-LF 1/16W 5% 402
R1984
5% 1/16W MF-LF
10K
402
100K R1986
402 MF-LF 1/16W 5%
18 41
6 18 39 40 65 39
39 41 18 24 75
R1965
402
5%
MF-LF
1/16W
33
R1966
NO STUFF
10K
5%
1/16W
402
MF-LF
R1983
5% 1/16W MF-LF
10K
402
R1998 20K
MF-LF 1/16W 5% 402
100K R1999
5% 1/16W MF-LF 402
MCP HDA, LPC & MISC
MCP_VID<0>
LPC_RESET_L
RTC_RST_L
SMC_IG_THROTTLE_L
MCP_CLK25M_XTALOUT
RTC_CLK32K_XTALIN
MCP_CLK25M_XTALIN
JTAG_MCP_TCK
SM_INTRUDER_L
PCIE_RESET_L
=PP3V3_S3_MCP_GPIO
=PP3V3_S5_MCP_GPIO
=PP3V3_S0_MCP_GPIO
ENET_LOW_PWR
SMC_IG_THROTTLE_L
HDA_BIT_CLK_R
SMBUS_MCP_1_DATA
HDA_SDIN0
AUD_IPHS_SWITCH_EN
PM_BATLOW_L
MCP_PS_PWRGD
LPC_AD<3>
LPC_AD<1>
LPC_AD<0>
GFXVCORE_PWR_EN
T57_RESET
JTAG_MCP_TMS
LPC_AD<2>
MCP_MEM_VTT_EN
JTAG_MCP_TDI
LPC_PWRDWN_L
PM_SLP_S5_L
LPC_RESET_L
MAKE_BASE=TRUE
PM_SLP_S4_L
MCP_WAKE_REQ_L
JTAG_MCP_TDO
HDA_SDOUT
HDA_RST_R_L HDA_RST_L
HDA_BIT_CLK_R HDA_BIT_CLK
=PP3V3_S0_MCP_GPIO
LPC_FRAME_L
HDA_SDOUT_R
ARB_DETECT_L
SPI_MISO
SPI_MOSI_R
MCP_THMDIODE_N
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
AP_PWR_EN
PM_CLK32K_SUSCLK_R
SPIROM_USE_MLB
HDA_SYNC
LPC_FRAME_R_L
MCP_CPU_VTT_EN_L
SMC_RUNTIME_SCI_L
LPC_SERIRQ
AUD_I2C_INT_L
MCP_HDA_PULLDN_COMP
LPC_AD_R<1>
LPC_AD_R<0>
PM_CLKRUN_L
LPC_AD_R<3>
LPC_AD_R<2>
TP_MLB_RAM_SIZE
PM_LATRIGGER_L
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
PM_SLP_S3_L
PM_SLP_RMGT_L
MCP_VID<2>
MCP_THMDIODE_P
HDA_SYNC_R
MCP_TEST_MODE_EN
RTC_CLK32K_XTALOUT
PM_RSMRST_L
JTAG_MCP_TRST_L
SPIROM_USE_MLB
MCP_CPU_VTT_EN_L
MLB_RAM_VENDOR
T57_PWR_EN
LPCPLUS_GPIO
ODD_PWR_EN_L
MEM_EVENT_L
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
AP_PWR_EN
ARB_DETECT_L
HDA_RST_R_L
HDA_SYNC_R
MCP_VID<3>
SPI_MISO
HDA_SDOUT_R
SMC_WAKE_SCI_L
PP3V3_G3_RTC
SDCARD_RESET
T57_RESET
GFXVCORE_PWR_EN
SPI_CS0_R_L
SPI_CLK_R
MCP_SPKR
MCP_MEM_VDD_EN
LPC_CLK33M_SMC_R
ODD_PWR_EN_L
MCP_VID<3>
MCP_VID<1>
PM_SLP_S4_L
SDCARD_RESET
ENET_LOW_PWR
MEM_EVENT_L
LPCPLUS_GPIO
MLB_RAM_VENDOR
T57_PWR_EN
SMC_ADAPTER_EN
MCP_MEM_VDD_SEL_1V5
19 OF 109
A.13.0
051-8563
18 OF 80
E1
E4
D1
D2
L8
L7
K7
L5
K10
C8
G8
D8
A8
C7
H7
H6
G6
C4
H4
D5
K9
K3
K5
K4
E11
F11
B8
D7
H3
G2
G3
B4
A5
A4
C5
B5
H11
H1
L16
D4
K16
D6
E2
D3
E3
L1
K1
K2
L3
L2
L6
G11
D11
B3
H2
F10
J10
G16
C11
C2
H16
B7
G10
J16
H5
G5
J11
H10
D10
C10
E10
A10
B10
A11
B16
B11
C16
K6
A7
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
8 22
15 24
7
7 17
7 16 17 18
8 18 31
18 40
18 75
18 75
18 75
7 16 17 18
18 75
18
18
75 18 75
6 18 41 50
18
18
6 18
18 41
18 36
18 25 26 39
18 62
18 62
18 62
18 29 65
18
18 75
18 75
18 62
6 18 41 75
18 75
7 19 22
18 30
6 18
18 21
18
+VDD_MEM_30
+VDD_MEM_31
+VDD_MEM_28
+VDD_MEM_29
+VDD_MEM_25
+VDD_MEM_26
+VDD_MEM_27
+VDD_MEM_23
+VDD_MEM_24
+VDD_MEM_22
+VDD_MEM_20
+VDD_MEM_21
+VDD_MEM_17
+VDD_MEM_18
+VDD_MEM_19
+VDD_MEM_15
+VDD_MEM_16
+VDD_MEM_12
+VDD_MEM_13
+VDD_MEM_14
+VDD_MEM_10
+VDD_MEM_11
+VDD_MEM_8
+VDD_MEM_9
+VDD_MEM_7
+VDD_MEM_5
+VDD_MEM_6
+VDD_MEM_4
+VDD_MEM_3
+VDD_MEM_2
+VDD_MEM_1
+VTT_CPU2_1
+VTT_CPU2_2
+VTT_CPU2_3
+VTT_CPU2_4
+VTT_CPU_27
+VTT_CPU_24
+VTT_CPU_25
+VTT_CPU_26
+VTT_CPU_23
+VTT_CPU_22
+VTT_CPU_21
+VTT_CPU_20
+VTT_CPU_19
+VTT_CPU_18
+VTT_CPU_16
+VTT_CPU_17
+VTT_CPU_14
+VTT_CPU_15
+VTT_CPU_11
+VTT_CPU_12
+VTT_CPU_13
+VTT_CPU_9
+VTT_CPU_10
+VTT_CPU_8
+VTT_CPU_1
+VTT_CPU_7
+VTT_CPU_6
+VTT_CPU_5
+VTT_CPU_4
+VTT_CPU_3
+VTT_CPU_2
(8 OF 11)
P
O
W
E
R

I
P
O
W
E
R

I
I
(9 OF 11)
+VDD_COREB_1
+VDD_COREB_3
+VDD_COREB_2
+VDD_COREB_4
+VDD_COREB_5
+VDD_COREB_6
+VDD_COREB_8
+VDD_COREB_7
+VDD_COREB_9
+VDD_COREB_10
+VDD_COREB_11
+VDD_COREB_13
+VDD_COREB_12
+VDD_COREB_14
+VDD_COREB_15
+VDD_COREB_16
+VDD_COREB_18
+VDD_COREB_17
+VDD_COREB_19
+VDD_COREB_20
+VDD_COREB_21
+VDD_COREB_22
+VDD_COREB_23
+VDD_COREB_24
+VDD_COREB_26
+VDD_COREB_25
+VDD_COREB_27
+VDD_COREB_28
+VDD_COREB_29
+VDD_COREB_31
+VDD_COREB_30
+VDD_COREB_32
+VDD_COREB_33
+VDD_COREB_34
+VDD_COREB_36
+VDD_COREB_35
+VDD_COREB_37
+VDD_COREB_38
+VDD_COREB_39
+VDD_COREB_40
+VDD_COREB_41
+VDD_COREB_42
+VDD_COREB_SENSE
GND_COREB_SENSE
+VIO_SATA_AVDD_1
+VIO_SATA_AVDD_3
+VIO_SATA_AVDD_2
+VIO_SATA_AVDD_4
+VIO_SATA_AVDD_5
+VIO_SATA_DVDD_1
+VIO_SATA_DVDD_2
+VIO_SATA_DVDD_3
+VIO_SATA_DVDD_4
+VIO_SATA_DVDD_5
+VIO_SATA_DVDD_6
+VIO_SATA_DVDD_7
+VIO_SATA_DVDD_8
+VIO_SATA_DVDD_9
+VIO_SATA_DVDD_10
+VIO_SATA_DVDD_11
+VIO_SATA_DVDD_12
+VDD_DUAL_RMGT_1
+VDD_DUAL_RMGT_2
+3.3V_DUAL_RMGT_1
+3.3V_DUAL_USB_1
+3.3V_DUAL_RMGT_2
+3.3V_DUAL_USB_2
+3.3V_DUAL_1
+3.3V_DUAL_2
+3.3V_HVDD_3
+3.3V_HVDD_1
+3.3V_HVDD_2
+3.3V_5
+3.3V_3
+3.3V_4
+3.3V_2
+3.3V_1
+VDD_DUAL_AUXC_2
+VDD_DUAL_AUXC_1
+VDD_DUAL_AUXC_3
+3.3V_VBAT
+VIO_PE_AVDD1_4
+VIO_PE_AVDD1_5
+VIO_PE_AVDD1_1
+VIO_PE_AVDD1_3
+VIO_PE_AVDD1_2
+VIO_PE_AVDD0_5
+VIO_PE_AVDD0_6
+VIO_PE_AVDD0_3
+VIO_PE_AVDD0_4
+VIO_PE_AVDD0_2
+VIO_PE_AVDD0_1
+VIO_PE_DVDD1_2
+VIO_PE_DVDD1_3
+VIO_PE_DVDD1_1
+VIO_PE_DVDD0_3
+VIO_PE_DVDD0_4
+VIO_PE_DVDD0_2
+VIO_PE_DVDD0_1
+VDD_COREA_32
+VDD_COREA_33
+VDD_COREA_30
+VDD_COREA_31
+VDD_COREA_29
+VDD_COREA_28
+VDD_COREA_27
+VDD_COREA_25
+VDD_COREA_24
+VDD_COREA_26
+VDD_COREA_22
+VDD_COREA_23
+VDD_COREA_21
+VDD_COREA_19
+VDD_COREA_20
+VDD_COREA_18
+VDD_COREA_16
+VDD_COREA_17
+VDD_COREA_15
+VDD_COREA_14
+VDD_COREA_11
+VDD_COREA_12
+VDD_COREA_13
+VDD_COREA_9
+VDD_COREA_10
+VDD_COREA_6
+VDD_COREA_7
+VDD_COREA_8
+VDD_COREA_4
+VDD_COREA_5
+VDD_COREA_1
+VDD_COREA_3
+VDD_COREA_2
GND_COREA_SENSE
+VDD_COREA_SENSE
(10 OF 11)
G
N
D
GND_28
GND_29
GND_27
GND_97
GND_98
GND_69
GND_68
GND_71
GND_70
GND_72
GND_74
GND_73
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_84
GND_83
GND_85
GND_86
GND_87
GND_89
GND_88
GND_90
GND_92
GND_91
GND_94
GND_93
GND_95
GND_96
GND_99
GND_102
GND_100
GND_101
GND_103
GND_104
GND_105
GND_107
GND_106
GND_109
GND_108
GND_110
GND_112
GND_111
GND_113
GND_114
GND_115
GND_117
GND_116
GND_118
GND_119
GND_120
GND_122
GND_121
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_130
GND_129
GND_131
GND_133
GND_132
GND_134
GND_2
GND_1
GND_4
GND_3
GND_6
GND_7
GND_5
GND_8
GND_9
GND_12
GND_11
GND_10
GND_14
GND_13
GND_15
GND_16
GND_17
GND_19
GND_18
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_30
GND_31
GND_32
GND_35
GND_34
GND_33
GND_37
GND_36
GND_38
GND_40
GND_39
GND_43
GND_41
GND_42
GND_45
GND_44
GND_47
GND_48
GND_46
GND_50
GND_49
GND_53
GND_52
GND_51
GND_55
GND_54
GND_56
GND_57
GND_58
GND_60
GND_59
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
(11 OF 11)
G
N
D
GND_157
GND_158
GND_199
GND_198
GND_197
GND_196
GND_195
GND_194
GND_193
GND_192
GND_191
GND_188
GND_190
GND_189
GND_187
GND_186
GND_183
GND_184
GND_185
GND_182
GND_181
GND_179
GND_180
GND_178
GND_177
GND_176
GND_175
GND_173
GND_174
GND_170
GND_172
GND_171
GND_169
GND_168
GND_166
GND_165
GND_167
GND_164
GND_163
GND_161
GND_160
GND_162
GND_159
GND_156
GND_155
GND_154
GND_153
GND_152
GND_150
GND_151
GND_147
GND_149
GND_148
GND_146
GND_145
GND_142
GND_143
GND_144
GND_140
GND_141
GND_138
GND_139
GND_137
GND_136
GND_135
GND_264
GND_263
GND_262
GND_261
GND_259
GND_258
GND_260
GND_256
GND_257
GND_254
GND_253
GND_255
GND_252
GND_251
GND_250
GND_249
GND_248
GND_246
GND_247
GND_245
GND_244
GND_243
GND_241
GND_242
GND_240
GND_239
GND_238
GND_236
GND_235
GND_237
GND_233
GND_234
GND_232
GND_230
GND_231
GND_228
GND_229
GND_227
GND_225
GND_226
GND_223
GND_224
GND_220
GND_222
GND_221
GND_219
GND_218
GND_217
GND_215
GND_216
GND_213
GND_212
GND_214
GND_211
GND_210
GND_209
GND_208
GND_207
GND_205
GND_206
GND_203
GND_204
GND_202
GND_200
GND_201
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
500 mA (AVDD0 & AVDD1)
500 mA (AVDD0 & AVDD1)
200 mA (DVDD0 & DVDD1)
200 mA (DVDD0 & DVDD1)
30 mA
150 mA
5 mA (S0)
140 mA
240 mA
40 mA
200 mA
300 mA
100 mA
300 mA
15350 mA (0.85V) 8450 mA (0.85V)
200 mA
2000 mA 4300 mA
Instead connect regulator sense point
COREA/COREB are powered by separate
regulators.
as close to COREB FET as possible.
(PE0[3:0])
(PE0[5:4], PE1[1:0])
NOTE: VDD_COREx_SENSE signals should NOT
be used for remote sensing unless
(PE0[3:0])
(PE0[5:4], PE1[1:0])
250 mA
?? uA (G3)
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
U1400
MCP89M-A01
OMIT
FBGA
U1400
FBGA
MCP89M-A01
OMIT
U1400
MCP89M-A01
OMIT
FBGA
U1400
FBGA
OMIT
MCP89M-A01
MCP Power & Ground
=PP1V05_S0_MCP_FSB
PP3V3_G3_RTC
TP_MCP_VDDCOREA_SENSEP
=PP1V05_SW_MCP_FSB
=PP3V3_S0_MCP
TP_MCP_VDDCOREB_SENSEN
=PPVCORE_SW_MCP_GFX
PP1V05_S0_MCP_SATA_AVDD
=PPVCORE_S0_MCP
TP_MCP_VDDCOREA_SENSEN
=PP3V3_S0_MCP_HVDD
TP_MCP_VDDCOREB_SENSEP
=PP3V3_S5_MCP
20 OF 109
A.13.0
051-8563
19 OF 80
AJ10
AF20
AJ8
AF14
AL8
AF17
AJ11
AM3
AL5
AF15
AH12
AM2
AG17
AL6
AG16
AJ9
AF19
AM5
AG19
AF23
AF22
AG20
AG13
AF16
AK8
AM1
AM4
AF21
AF18
AL7
AG14
W27
W28
Y27
Y28
N26
H31
B32
R26
T26
U26
H30
M28
E32
C32
U27
G31
H29
W26
P26
F32
A32
J29
N27
T27
G32
P27
V26
Y26
L29
D32
K29
M4
P4
M2
N12
N4
N14
N10
V20
P3
P1
N11
P6
N6
N2
N9
N8
N3
M10
N1
M5
M7
P2
M8
M11
N7
V19
N16
P5
N5
N15
N13
P9
V17
V18
M13
M14
Y19
Y20
Y17
Y18
P7
P8
U10
T10
AE1
AE3
AE2
AE4
AE5
AF1
AF2
AF3
AF4
AF5
AF6
AF9
AF10
AF11
AE11
AE12
AE13
L12
L13
A13
A20
B13
A19
F8
E8
U13
T11
T12
E5
F5
E29
U12
U11
M17
L11
M20
A16
W12
W13
Y12
AA13
Y13
AD13
AB13
AC12
AD11
AB12
AC13
AE7
AE8
AE6
AE9
AE10
AF8
AF7
P10
P11
AA22
P12
Y22
W22
V22
T9
T5
U22
R5
T7
T4
T8
R8
R2
AB19
P13
R4
AB21
AB18
T1
T2
AB17
R10
T6
T13
R11
R13
R7
T3
AB20
AB22
L9
L10
M32
B2
B18
AM27
AP27
B12
AD7
E12
D12
G12
AL12
A2
AM6
AD37
AG32
H12
AR35
H9
G24
V10
AL30
V5
G7
V29
AP15
AJ12
AN2
AR15
D21
N20
G21
E21
H21
AR27
AM15
AH24
AA31
AM9
K12
J31
E30
V7
AK7
AU12
M31
AP6
A36
B37
F35
L27
D35
AP30
AL24
AH15
B21
AV3
B38
AT38
AA21
AD4
A37
AP18
AN4
B24
V4
D30
AA7
AK4
AD34
R37
M37
AP21
AU37
AM21
D18
B1
AC27
AD5
J2
C1
AM30
AT1
AP24
AT3
AM33
AE27
AJ24
AA8
AH18
AM18
B6
J32
AJ21
AK35
H15
D33
E6
J5
K18
F34
AD10
AN34
R35
V8
AR9
AA10
AA2
H8
R32
AG29
AM12
AP12
V32
AR33
AH21
AA32
J7
K24
AK37
AG34
J8
K21
AG8
AN5
V2
AD2
AD32
D15
AG2
L15
AK32
AR12
AN35
AN37
AH27
E18
H27
N19
L4
D9
AV37
AL27
G15
A3
L18
B15
AJ15
AA4
H18
AU38
E9
E27
L21
AG10
AU1
J4
AU27
AH30
J34
AU33
AR30
AK34
E15
D27
J35
R34
C38
V28
M34
AA11
B27
AL21
V34
K11
AK31
AU21
AA34
M19
K15
E24
N18
AK5
D24
AU30
H24
AR21
B30
AM24
AU9
AA5
G18
B9
AL18
AR24
AD35
AJ18
AG5
AU15
AU24
U21
AA20
AA19
AA18
AB27
AA26
AA17
W19
W20
AD29
AD28
AG4
N17
AA29
AA28
V21
W17
W18
U20
U19
W21
U18
Y21
V31
K8
U17
R31
R28
G30
R29
AB26
M29
AL9
F2
K27
L14
K14
AR18
AG37
AL15
V37
AA37
AU2
AD31
AP9
AD8
AG7
AG35
AJ27
G9
AV36
AR6
B33
AU18
AA35
G27
V35
J37
F37
C3
AK2
AU6
AV2
E33
M35
7 17 22
7 22
7 13 22
14 20 22
7 22
7 18 22
7 22
7 22
7
21 23
22
7 22
7 22
7
7
7 22
7 22
7
NC
NC
OUT
OUT
IN
BI
BI
BI
BI
D
G S
IN
VCC
D
DONE
G
GND
THRM
S
EN
CNFG
PAD
NC
K1
G
S
S
E
N
S
E
D
KELVIN
D
G
G
D
S
S
D
G
G
D
S
S
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NV Requirements:
Q2355/Q2356 chosen for low output capacitance.
CKE must be held low to keep memory in self-refresh.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps enable before MCP89 MEMVDD rail switched off.
NO STUBS on CKE signals!
DIMM CKE Clamps
<R1>
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)
(G driven to VCC)
Gated Rail Savings: 120mW
NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.
- Min Ramp-Up Time: 20 uS (10% to 90%)
- Max Ramp-Up Time: 65 uS (ENABLE to 90%)
- FET Ron <= 3.8 mOhms
4250 mA
(OR 1.35V)
Q2300
Loading
Rds(on)
Type
Part
N-Channel
4.3 A (EDP)
10 mOhm @3.2V
STMFS4854N
C2300 helps reduce input rail
droop during Q2300 turn-on.
44
44
R2305
MF
560K
402
1/16W
1%
18 65
C2305
0.1UF
402
CERM
10V
20%
C2300
CRITICAL
PLACE_NEAR=Q2300.9:2 mm
1206-1
CERM-X5R
6.3V
20%
100UF
14 26 73
14 26 73
14 25 73
14 25 73
Q2350
SSM3K15FV
SOD-VESM-HF
18
R2350
5%
1/16W
10K
402
MF-LF
U2305
CRITICAL
TDFN
SLG5AP031
Q2300
CRITICAL
DFN
STMFS485NST1G
CRITICAL
NTUD3170NZXXG
SOT-963
Q2355
CRITICAL
NTUD3170NZXXG
Q2356
SOT-963
MCP89 Memory Rail Gating
MCPDDRFET_KELVIN
MCPDDRFET_SENSE
MCP_MEM_VDD_EN
MCPMEM_CNFG
TP_MCPMEM_DONE
=PP1V5R1V35_S0_MCPDDRFET
PP1V5R1V35_SW_MCP
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP5V_S3_MCPDDRFET
MCPMEM_GATE
=PP5V_S3_MCPDDRFET
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_B_CKE<1>
MEMVTT_EN_L
MEM_B_CKE<0>
MCP_MEM_VTT_EN
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6
7
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3
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2
4
5
6
7
7 20
7 20
14 19 22
OUT
OUT
S
D
G
IN
CNFG
EN
S
THRM
GND
G
DONE
D
VCC
PAD
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<C1>
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)
(G driven to VCC)
- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)
Q2400
15.35 A (EDP)
NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.
droop during Q2400 turn-on.
C2400 helps reduce input rail
N-Channel
Si4838BDY
3.2 mOhm @2.5V
- Min Ramp-Up Time: 100 uS (10% to 90%)
- FET Ron <= 2.5 mOhms
Gated Rail Savings: 860mW
NV Requirements:
Type
Part
Loading
Rds(on)
XW2401
PLACE_NEAR=C2400.2:1 mm
SM
XW2400
SM
62 79
62 79
Q2400
CRITICAL
SI4838BDY
SO-8
18
C2405
20%
10V
CERM
402
0.1UF
C2400
100UF
CRITICAL
1206-1
CERM-X5R
6.3V
20%
C2406
10%
CERM
820PF
402
50V
U2405
SLG5AP033
TDFN
CRITICAL
MCP89 GFX Core Rail Gating
=PPVCORE_SW_MCP_GFX
MCPCORES0_VSEN_N
MCPCORES0_VSEN_P
MCPGFX_GATE
=PPVCORE_S0_MCPGFXFET
MCPGFX_CNFG
GFXVCORE_PWR_EN
VOLTAGE=0.9V
MAKE_BASE=TRUE
PPVCORE_SW_MCP_GFX
TP_MCPGFX_DONE
=PP5V_S0_MCPFSBFET
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7
8
5
1
19 23
7
7
NC
VOUT
EN
VIN
GND
IN
OUT
+IN
-IN
V+
V-
+IN
-IN
V+
V-
D
S
G
D S
G
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(For R and C)
PLACEMENT_NOTEs:
MCP 1.05V SATA Digital Power
200 mA
MCP 3.3V DP & USB PLL Power
210 mA
MCP 3.3V PCIe/SATA I/O PLL Power
MCP 3.3V/1.5V HDA Power
100 mA
260 mA
50 mA
MCP 1.05V PCIe/SATA PLL Power
70 mA 555 mA
MCP 1.05V CPU/FSB/MEM PLL Power
MCP 1.05V SATA Analog Power
300 mA
MCP 0.9V MAC/SMU Power
MCP 2.0V-3.3V RTC Power
8450 mA (0.85V)
MCP 3.3V AUX/USB Power
MCP Non-GFX Core Power
800 mA 500 mA
240 mA
300 mA
5 mA (S0)
30 mA
550 mA
140 mA 150 mA
200 mA 2000 mA
4300 mA (1.5V)
MCP 1.05V PCIe Analog Power
MCP 3.3V I/O Power
MCP S0 FSB (VTT) Power
250 mA
? uA (G3)
MCP 1.05V Memory DLL Power
20 mA
MCP 3.3V MAC PLL Power
20 mA
MCP CPU FSB (VTT) Power
325 mA
160 mA
MCP Memory Power
MCP 0.9V AUX Core Power
MCP 1.05V PCIE Digital Power
MCP 3.3V MAC/SMU Power
70 mA
MCP 3.3V PLL Power
MCP 1.05V Core/Misc PLL Power
C2504
HTOL_SENSE:YES
MCPHVDD:P3V3
SMC_P_FOLLOW
OPA330
SC70-5
Place close to SMC
HTOL_SENSE:YES
SOT-563-HF
NTZD3152P
CRITICAL
Q2592
HTOL_SENSE:YES
SOT-563-HF
NTZD3152P
CRITICAL
Q2592
HTOL_SENSE:YES
4.53K
20%
HTOL_SENSE:YES
HTOL_SENSE:YES
0.1UF
L2590
FERR-240-OHM-200MA
C2591
PLACE_NEAR=R2575.1:50 mil
HTOL_SENSE:YES
10V
SMC_N_MIRROR
1/16W
402
C2594
HTOL_SENSE:YES
PP3V3_S0_MCP_HVDD
603
C2580
4.7UF
C2599
0.1UF
LDO:ADJ
C2582
402
MF-LF
HTOL_SENSE:YES
R2590
100K
1%
CERM
CRITICAL
LDO:ADJ
C2597
0.1uF
20%
10V
CRITICAL
CRITICAL
VOLTAGE=3.3V
PP3V3_S0_MCP_PLL_HVDD
HTOL_SENSE:YES
U2594
20%
402
CERM
R2597
1/16W
402
MF-LF
1%
1K
U2593
SC70-5
OPA330
402
20%
10V
CRITICAL
MF-LF
1/16W
1%
402
R2598
Place close to SMC
HTOL_SENSE:YES
402
C2598
0.22UF
20%
6.3V
X5R
100K
5%
1/16W
MF-LF
402
HTOL_SENSE:YES
R2599
1/16W
5%
402
MF-LF
0
R2593
MF-LF
1/16W
1%
1K
R2596
402
GND_SMC_AVSS
PP3V3_S0_LDO_R
MCPHVDD:P2V5
C2596
SYNC_DATE=08/15/2009
PP3V3_S0_MCP_PLL_DP_USB
1/16W
10K
402
MF-LF
5%
1/16W
5%
10K
R2594
LDO:ADJ
MF-LF
C2595
4.7UF
CERM
CERM
SMC_N_FOLLOW
4.7UF
MCP Standard Decoupling
SYNC_MASTER=T27_MLB
6.3V
C2590
10%
U2592
U2592
402
1UF
10V
X5R
402
C2593
MCPHVDD:P2V5
402
R2592
MF-LF
1/16W
5%
10K
U2592
SC70
MIC5365-2.5V
CRITICAL
OMIT_TABLE
10%
10V
1UF
402
X5R
C2592
CERM
SMC_P10
L2595
220-OHM-2.2A
0603
GND_MCP_PLL_DP_USB
0402
SMC_NB_MISC_ISENSE
VOLTAGE=3.3V
R2595
=PP3V3_S0_OPA333
39
LDO_ADJ MCP_PLL_LD0_EN
4.7UF
=PP3V3_S0_MCP_HVDD
4.7UF
1
353S2979 IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF
IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF 353S2971
1
VOLTAGE=0V
VOLTAGE=3.3V
603
6.3V
20%
CERM
MF
5%
0.33
1/16W
0402
10V
0.1UF
CERM
20%
402
10V
CERM
0.1uF
20%
VOLTAGE=3.3V
CRITICAL
20%
402
CERM
10V
20%
0.1UF
3
9

PP1V05_S0_MCP_PLL_CORE
VOLTAGE=1.05V
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_PEXSATA
CRITICAL
220-OHM-2.2A
L2580
0603
CRITICAL
220-OHM-2.2A
0603
L2575
402
20%
4V
X5R
10V
C2581
CERM
402
0.1UF
402
CERM
C2575
402
4.7UF
20%
X5R
4V
C2576
402
CERM
10V
20%
0.1UF
C2577
20%
10V
CERM
0.1uF
402
402
0.1UF
10V
C2583
20%
20%
10V
402
C2584
0.1UF
0.1UF
20%
10V
CERM
C2578
402
0.1UF
402
CERM
10V
20%
C2579
VOLTAGE=0V
GND_MCP_PLL_FSB
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_FSBMEM
L2570
CRITICAL
0603
220-OHM-2.2A
C2570
20%
4V
4.7UF
402
X5R
1/16W
5%
0402
0.33
R2570
MF
CERM
0.1UF
20%
402
10V
C2571 C2572
10V
0.1uF
402
CERM
20%
C2573
0.1UF
20%
10V
CERM
402
PP1V05_S0_MCP_SATA_AVDD
VOLTAGE=1.05V
L2567
0603
30-OHM-5A
X5R
603-1
10UF
6.3V
C2567
20% 20%
4V
X5R
C2568
4.7UF
402
0.1UF
402
CERM
10V
20%
C2569
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_SW_MCP_FSB
=PP3V3_ENET_MCP_PLL_MAC
PP3V3_ENET_MCP_PLL_MAC
VOLTAGE=3.3V
=PP3V3_S0_MCP
=PP3V3_S5_MCP
=PPVCORE_S0_MCP
PP3V3_G3_RTC
=PP1V05_S0_MCP_FSB
VOLTAGE=1.05V
PP1V05_S0_MCP_PE_AVDD
CRITICAL
0402
FERR-240-OHM-200MA
L2555
4.7UF
CERM
20%
6.3V
603
C2552
20%
CERM
6.3V
603
C2541
10V
CERM
402
0.1uF
20%
C2542 C2540
4V
4.7UF
402
X5R
20%
C2566
0.1UF
402
CERM
10V
20%
C2565
0.1UF
402
CERM
10V
20%
C2564
402
CERM
10V
20%
0.1UF
C2563
402-1
1UF
X5R
10V
10%
402-1
10V
10%
1UF
X5R
C2562 C2561
4V
4.7UF
402
X5R
20%
10UF
X5R
20%
603-1
C2560
6.3V
4.7UF
CERM
20%
6.3V
603
C2555
4.7UF
402
X5R
20%
4V
C2524
1UF
X5R
10V
10%
402-1
C2525 C2523
10%
10V
402-1
X5R
1UF
C2522
10%
10V
X5R
402-1
1UF
C2521
4V
4.7UF
402
X5R
20%
C2520
6.3V
20%
X5R
603-1
10UF
C2547
20%
10V
402
0.1uF
CERM
C2546
402
CERM
10V
20%
0.1uF
C2545
0.1uF
402
10V
20%
CERM
C2544
0.1uF
402
CERM
10V
20%
C2543
603
6.3V
4.7uF
CERM
20%
C2550
603
6.3V
4.7uF
CERM
20%
C2551
0.1uF
402
CERM
10V
20%
C2553
603
6.3V
20%
CERM
4.7uF
C2554
20%
10V
CERM
402
0.1uF
402
CERM
10V
20%
0.1uF
C2535
C2548
20%
CERM
4.7UF
6.3V
603 402
CERM
20%
10V
0.1uF
C2549
402
X5R
4V
C2528
20%
4.7uF
20%
CERM
402
0.1uF
C2529
10V
0.1UF
20%
10V
CERM
402
C2556
C2534
20%
402
CERM
10V
0.1uF
C2533
0.1uF
402
CERM
10V
20%
0.1uF
CERM
20%
402
10V
C2537
C2526
0.1uF
402
CERM
10V
20%
C2527
0.1uF
402
CERM
20%
10V
C2501
4.7UF
402
4V
20%
X5R
20%
X5R
603-1
6.3V
10UF
C2500
30-OHM-5A
0603
L2560
20%
C2510
4V
4.7UF
X5R
402
C2511
402
10V
20%
0.1UF
CERM
C2512
CERM
10V
20%
0.1UF
C2513
0.1UF
402
CERM
10V
20%
C2514
0.1UF
402
10V
20%
CERM
C2515
0.1UF
402
CERM
10V
20%
C2516
0.1UF
402
CERM
10V
20%
C2517
20%
0.1UF
402
CERM
10V
C2518
0.1UF
402
CERM
10V
20%
C2519
20%
CERM
10V
0.1UF
402
20%
4V
402
X5R
C2536 C2530
4V
4.7UF
X5R
20%
402
C2531
402-1
X5R
10V
10%
1UF 1UF
10V
402-1
X5R
10%
C2532
20%
10V
CERM
402
0.1UF
C2508
402
CERM
20%
10V
0.1UF
C2505
20%
402
0.1UF
10V
CERM
C2506
20%
10V
CERM
402
0.1UF
C2507
20%
CERM
402
0.1UF
10V
C2502
1UF
10%
10V
X5R
402-1
C2503
6.3V
20%
X5R
402
0.22UF
R2591
402
=PP3V42_G3H_OPA330
MCPHVDD:P2V5
LDO:FIXED
CRITICAL
CRITICAL HTOL_SENSE:NO RES,0402,0,5%,1/16W 116S0004 1 R2596 25 OF 109
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2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2 1
2 1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
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1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2 1
2 1
2 1
2 1
2 1
2
1 1
2
2
1
2
1
2 1
2
4
5
3
1 2
1
1 2
1
2
1
2
1 2
2
1
2
1
1 2
2
5
4
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3
2
5
4
1
3
2
1
1 2
4
3
5
16
2
44
43
40
39
7
15
7
7
15
16
14 7
19
18 8
19 7
19 7
7
7
19 7
7 17
19 7
19 17 7
14 7
19 7
20 19 14
19 7
19 7
19 18 7
19 13 7
19 7
7
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140 mA
180 mA (1.8V LVDS) 60 mA
15350 mA (0.85V)
If RGBDAC is used, requires ferrite (155S0382)
plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.
If RGBDAC is not used, tie to GND.
MCP 3.3V RGBDAC Power
MCP GFX Core Power
160 mA
MCP 1.05V DisplayPort Power
MCP 1.05V IFP PLL Power MCP 3.3V/1.8V IFP Interface Power
C2650
402
CERM
10V
20%
0.1UF
NO STUFF R2655
1/16W
1%
402
MF-LF
1K
NO STUFF
C2655
NO STUFF
0.1UF
CERM
402
20%
10V
C2640
4V
X5R
402
20%
4.7UF
R2670
0
MF-LF
402
5%
1/16W
C2620
20%
4.7uF
6.3V
CERM
603
C2621
10V
402
0.1uF
20%
CERM
C2631
CERM
20%
0.1uF
402
10V
C2630
20%
4.7uF
4V
X5R
402
C2600
603-1
10UF
20%
X5R
6.3V
C2601
20%
4V
X5R
402
4.7UF
C2602
10%
10V
X5R
402-1
1UF
C2603
10%
10V
X5R
402-1
1UF
C2604
0.22UF
20%
6.3V
X5R
402
C2605
20%
6.3V
X5R
402
0.22UF
C2606
402
CERM
20%
10V
0.1UF
C2607
20%
10V
CERM
402
0.1UF
C2608
20%
10V
CERM
402
0.1UF
C2609
20%
10V
CERM
402
0.1UF
C2610
20%
10V
CERM
402
0.1UF
C2611
20%
10V
CERM
402
0.1UF
C2612
20%
10V
CERM
402
0.1UF
C2641
10V
402
0.1uF
20%
CERM
R2650
1K
402
MF-LF
1/16W
1%
SYNC_MASTER=T27_MLB
MCP Graphics Support
VOLTAGE=0V
GND_MCP_DAC_P3V3
MAKE_BASE=TRUE
MCP_IFPAB_RSET
MCP_TMDS0_VPROBE
MCP_TMDS0_RSET
MCP_IFPAB_VPROBE
PP3V3_S0_MCP_DAC
=PPVCORE_SW_MCP_GFX
26 OF 109
A.13.0
051-8563
23 OF 80
2
1
1
2 2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
7 16
7 16
16 74
16 74
16 74
7 16
16 74
16
19 21
IN OUT
IN OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT IN
NC
NC
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
D
G
S
IN
NC
NC
OUT
B
Y
A
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
MCP S0 PWRGD & CPU_VLD
Ethernet WAKE# Isolation
LPC Reset (Unbuffered)
Platform Reset Connections
10K pull-up to 3.3V S0 inside MCP
System Reset Circuit
PCIE Reset (Unbuffered)
RTC Crystal
MCP 25MHz Crystal
Caesar II (ENET) 25MHz Crystal
9 12 18
C2810
12pF
5%
CERM
402
50V
C2811
5%
50V
CERM
402
12pF
R2810
MF-LF
5%
0
1/16W
402 R2811
NO STUFF
1/16W
MF-LF
5%
402
10M
18 75
R2896
XDP
1/16W
MF-LF
5%
0
402
R2883
33
MF-LF
5%
1/16W
402
PLACEMENT_NOTE=Place close to U1400
R2881
1/16W
5%
33
MF-LF
402
R2897
OMIT
SILK_PART=SYS RST
402
MF-LF
1/16W
5%
0
PLACEMENT_NOTE=Place R2897 on BOTTOM
41
39
18
18
15 18
R2826
33
5%
MF-LF
1/16W
402
R2825
402
1/16W
MF-LF
33
5%
18 75
C2815
50V
5%
CERM
402
12pF
C2816
12pF
402
CERM
5%
50V
Y2815
SM-3.2X2.5MM
CRITICAL
25.0000M
R2815
402
5%
MF-LF
1/16W
0
R2816
1/16W
NO STUFF
MF-LF
402
5%
1M
18
18
39 75
R2829
402
MF-LF
5%
1/16W
22
18 75
R2899
1/16W
402
MF-LF
5%
33
C2899
NO STUFF
402
10V
X5R
1UF
10%
34
39
41 75
39 75
Y2810
32.768K
7X1.5X1.4-SM
CRITICAL
R2891
0
5%
MF-LF
1/16W
402
28
R2893
0
5%
1/16W
MF-LF
402
71
29
R2894
0
402
5%
MF-LF
1/16W
61
39 65
C2850
402
CERM
10V
20%
0.1UF
18
30
R2895
0
5%
1/16W
MF-LF
402
6 15 29
31
31
Q2830
SOD-VESM-HF
SSM3K15FV
31
R2821
10M
MF-LF
5%
1/16W
NO STUFF
402
R2830
MF-LF
1/16W
402
5%
10K
R2820
200
MF-LF
5%
1/16W
402
Y2820
SM-3.2X2.5MM
25.0000M
CRITICAL
C2821
27pF
402
CERM
50V
5%
C2820
27pF
402
5%
50V
CERM
31 76
R2892
1/16W
MF-LF
5%
402
0
74LVC1G08GW
SOT353
U2850
SB Misc
PCIE_RESET_L
MAKE_BASE=TRUE
ENET_WAKE_L
MAKE_BASE=TRUE
BCM5764_CLK25M_XTALO
MCP_CLK25M_XTALOUT
BCM5764_CLK25M_XTALO_R
MCP_CLK25M_XTALOUT_R
RTC_CLK32K_XTALOUT RTC_CLK32K_XTALOUT_R
BCM5764_CLK25M_XTALI
MCP_CLK25M_XTALIN
ENET_RESET_L
SDCARD_PLT_RST_L
AP_RESET_L
PM_SYSRST_L
PM_SYSRST_DEBOUNCE_L
LPCPLUS_RESET_L LPC_RESET_L
PCA9557D_RESET_L
PM_CLK32K_SUSCLK PM_CLK32K_SUSCLK_R
XDP_DBRESET_L
SMC_LRESET_L
BKLT_PLT_RST_L
=FW_RESET_L
=PP3V3_ENET_PHY
PCIE_WAKE_L =ENET_WAKE_L
LPC_CLK33M_SMC_R LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
RTC_CLK32K_XTALIN
=PP3V3_S5_MCPPWRGD
VR_PWRGOOD_DELAY
MCP_PS_PWRGD
ALL_SYS_PWRGD
28 OF 109
A.13.0
051-8563
24 OF 80
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1 2
3
1
2
4
1 2
1
2
1 2
1 2
2
1
4
1
1 2
1 2
1 2
2
1
1 2
1
2 3
1
2
1
2
1 2
3
1
2
4
1 2
1 2
1 2
4
3
1
2
5
7 31 64
7
A6
A7
A11
A5
DQ33
VDD
A10/AP
VDD
VSS
SA1
VTT
VSS
DQS4*
DQS4
VSS
DQ35
VSS
CK0*
SA0
VSS
DQ58
DQ59
DM7
VSS
DQ57
DQ56
DQ50
DQ51
VSS
DQS6*
DQS6
VSS
DQ49
DQ48
DQ43
VSS
DM5
VSS
DQ42
SDA
SCL
VTT
VSS
EVENT*
DQ62
VSS
DQ63
DQS7*
DQS7
DQ60
DQ61
VSS
VSS
DQ55
DQ54
DM6
VSS
DQ53
VSS
DQ52
DQ47
VSS
DQS5
VSS
DQ46
DQ41
VSS
DQ40
DQ34
VSS
DQ32
TEST
VDD
VDD
S1*
A13
CAS*
WE*
BA0
VDD
VDD
CK0
A1
A3
VDD
VDD
A8
A9
A12/BC*
VDD
BA2
NC
VDD
CKE0
VSS
DQS5*
VSS
DQ44
DQ45
DQ39
DQ38
VSS
VSS
DM4
VSS
DQ37
DQ36
VREFCA
VDD
ODT1
NC
S0*
ODT0
BA1
RAS*
VDD
CK1*
VDD
VDD
A0
CK1
A2
VDD
A4
VDD
VDD
A14
A15
CKE1
VDD
VSS
VDDSPD
KEY
(
S
Y
M
B
O
L

2

O
F

2
)
IN
DQ16
DM3
DQ26
DQ27
DQ4
DQ31
DQ30
DQS3
DQS3*
DQ29
DQ28
DQ23
DQ22
DM2
DQ21
DQ20
DQ15
DQ14
RESET*
DM1
DQ13
DQ12
DQ7
DQ6
DQS0
DQS0*
DQ5
DQ24
DQ25
DQ19
DQ18
DQS2
DQS2*
DQ17
DQ11
DQ10
DQS1
DQS1*
DQ8
DQ9
DM0
DQ0
DQ1
VREFDQ
DQ3
DQ2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(
S
Y
M
B
O
L

1

O
F

2
)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
IN
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
516-0201
BOM options provided by this page:
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMA_SDA
(NONE)
- =I2C_SODIMMA_SCL
"Factory" (top) slot
SPD Addr: 0xA0(Wr)/0xA1(Rd)
Page Notes
- =PPLVDDR_S3_MEM_A
- =PPDDRVTT_S0_MEM_A
Power aliases required by this page:
516-0201
DDR3 Plane Stitching Caps (Space evenly across plane split)
J2900
F-RT-THB
D
D
R
3
-
S
O
D
I
M
M
-
D
U
A
L
-
M
9
7
-
3
CRITICAL
CERM
0.1UF
C2931
20%
10V
402
C2930
2.2UF
CERM
402-LF
20%
6.3V
14 20 73
J2900
CRITICAL
F-RT-THB
D
D
R
3
-
S
O
D
I
M
M
-
D
U
A
L
-
M
9
7
-
3
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
C2936
10V
20%
402
CERM
0.1UF
C2935
6.3V
20%
402-LF
CERM
2.2UF
18 26 39
42
42
14 20 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
R2941
1/16W
5%
402
MF-LF
10K
R2940
10K
MF-LF
402
5%
1/16W
C2940
2.2UF
CERM
402-LF
20%
6.3V
C2900
6.3V
20%
X5R
10UF
603
C2901
10UF
20%
6.3V
X5R
603
C2910
10V
20%
0.1UF
402
CERM
2
1
C2911
0.1UF
CERM
20%
10V
402
2
1
C2912
0.1UF
CERM
20%
10V
402
2
1
C2913
0.1UF
20%
10V
402
2
1 CERM
C2914
0.1UF
CERM
20%
10V
402
2
1 1
2 C2915
10V
20%
CERM
0.1UF
402
10V 1
2 C2916
20%
CERM
0.1UF
402
0.1UF
10V
CERM
402
1
2 C2917
20%
1
2 C2918
402
0.1UF
CERM
20%
10V 1
2 C2919
10V
20%
CERM
0.1UF
402
1
2 C2920
10V
20%
CERM
0.1UF
402
1
2 C2921
10V
20%
CERM
0.1UF
402
1
2 C2922
10V
20%
CERM
0.1UF
402
1
2 C2923
10V
20%
CERM
0.1UF
402
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
14 26
27
27
27
27
27
27
27
27
27
27
27
27
DDR3 SO-DIMM Connector A
=PPLVDDR_S3_MEM_A
MEM_A_CKE<1>
MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<4>
=PPDDRVTT_S0_MEM_A
MEM_A_A<6>
=MEM_A_DQ<32>
MEM_A_CS_L<1>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_A_SA<0>
=MEM_A_DQ<57>
=MEM_A_DQS_N<6>
=MEM_A_DM<5>
=MEM_A_DQ<41>
=MEM_A_DQS_P<4>
PPVREF_S3_MEM_VREFDQ_A
=MEM_A_DQ<1>
=MEM_A_DQ<30>
=MEM_A_DQ<31>
=MEM_A_DM<2>
=MEM_A_DQ<21>
=MEM_A_DQ<13>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DM<1>
MEM_RESET_L
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<20>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DM<0>
=MEM_A_DQ<0>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DM<3>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
=MEM_A_DQ<17>
=MEM_A_DQ<16>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<1>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
=MEM_A_DM<6>
=MEM_A_DQ<53>
=MEM_A_DQ<52>
=MEM_A_DQ<47>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQS_N<5>
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DM<4>
=MEM_A_DQ<36>
=MEM_A_DQ<37>
MEM_A_ODT<1> MEM_A_A<13>
=MEM_A_DQ<49>
=MEM_A_DM<7>
=MEM_A_DQS_P<6>
PPVREF_S3_MEM_VREFCA_A
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_A<12>
MEM_A_A<3>
=PPSPD_S0_MEM_A
MEM_A_SA<1> =I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA
MEM_EVENT_L
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_BA<1>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<7>
MEM_A_A<15>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_BA<0>
MEM_A_A<10>
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_A<1>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<9>
29 OF 109
A.13.0
051-8563
25 OF 80
90
86
84
91
131
105
107
124
195
201
203
127
135
137
139
143
151
103
197
189
191
193
187
179
183
181
175
177
173
169
171
167
165
163
159
161
153
155
157
200
202
204
196
198
192
190
194
186
188
180
182
184
178
176
174
170
172
166
168
164
160
162
154
156
158
149
145
147
141
133
129
125
123
117
121
119
115
113
109
111
99
101
97
95
93
87
89
85
83
81
79
77
75
73
150
152
144
146
148
142
140
138
134
136
128
132
130
126
118
120
122
114
116
108
110
112
104
106
100
98
102
96
94
92
88
82
80
78
74
76
185
199
2
1
2
1
37
39
61
63
65
67
69
71
4
72
70
68
66
64
62
60
58
56
52
54
50
48
46
42
44
40
38
36
32
34
30
28
26
24
22
20
18
16
14
12
10
8
6
2
57
59
55
53
51
47
49
45
41
43
35
31
33
29
27
25
21
23
19
13
11
9
5
7
1
3
17
15
2
1
2
1
1
2
1
2
2
1
2
1
2
1
7
7
28
28
7
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ2
DQ3
VREFDQ
DQ1
DQ0
DM0
DQ9
DQ8
DQS1*
DQS1
DQ10
DQ11
DQ17
DQS2*
DQS2
DQ18
DQ19
DQ25
DQ24
DQ5
DQS0*
DQS0
DQ6
DQ7
DQ12
DQ13
DM1
RESET*
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3*
DQS3
DQ30
DQ31
DQ4
DQ27
DQ26
DM3
DQ16
(
1

O
F

2
)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
A1
A3
VDD
A5
A8
VDD
A9
VDD
A12/BC*
VSS
DQ42
DQ43
DQ48
DQ49
VSS
VSS
DQ41
DQS4*
DM5
VDD
CKE1
A15
A14
VDD
A11
A7
A6
VDD
A4
A2
CK1
A0
VDD
VDD
CK1*
VDD
RAS*
BA1
ODT0
S0*
NC
ODT1
VDD
VREFCA
VDD
DQ36
DQ37
VSS
DM4
VSS
VSS
DQ38
DQ39
DQ45
DQ44
VSS
DQS5*
VSS
CKE0
VDD
NC
BA2
CK0
VDD
BA0
WE*
A13
S1*
VDD
VDD
TEST
DQ33
DQ32
VSS
DQ34
DQ40
VSS
DQ46
VSS
DQS5
VSS
DQ47
DQ52
VSS
DQ53
VSS
DM6
DQ54
DQ55
VSS
VSS
DQ61
DQ60
DQS7
DQS7*
DQ63
VSS
DQ62
EVENT*
VSS
VTT
SCL
SDA
VSS
DQS6
DQS6*
VSS
DQ51
DQ50
A10/AP
VDD
CK0*
DQ35
VSS
DQS4
VSS
CAS*
VDD
DM7
VSS
DQ56
MTG PIN MTG PIN
MTG PIN MTG PIN
MTG PIN MTG PIN
MTG PIN
VSS
DQ57
VTT
SA1
SA0
DQ58
VSS
DQ59
VSS
VDDSPD
MTG PIN
MTG PINS
KEY
(
2

O
F

2
)
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
(NONE)
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
"Expansion" (bottom) slot
516s0706
516s0706
DDR3 Plane Stitching Caps (Space evenly across plane split)
SPD Addr: 0xA2(Wr)/0xA3(Rd)
Page Notes
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =PPLVDDR_S3_MEM_B
- =PPDDRVTT_S0_MEM_B
10V
20%
402
CERM
0.1UF
C3131
2.2UF
CERM
402-LF
20%
6.3V
C3130
14 20 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
10V
20%
402
CERM
0.1UF
C3136
6.3V
20%
402-LF
CERM
2.2UF
C3135
18 25 39
42
42
14 20 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
1/16W
5%
402
MF-LF
10K
R3141
402
1/16W
5%
MF-LF
10K
R3140
2
1
2.2UF
CERM
402-LF
20%
6.3V
C3140
603
10UF
X5R
20%
6.3V
C3100
6.3V
20%
603
X5R
10UF
C3101
402
0.1UF
CERM
20%
10V
C3110 2
1 10V
20%
CERM
0.1UF
402
C3111 2
1 10V
20%
CERM
0.1UF
402
C3112 2
1 10V
20%
CERM
0.1UF
402
C3113 2
1 10V
20%
CERM
0.1UF
402
C3114 2
1
402
0.1UF
CERM
20%
10V
C3115 2
1
402
0.1UF
CERM
20%
10V
C3116 2
1
402
0.1UF
CERM
20%
10V
C3117 2
1 10V
20%
CERM
0.1UF
402
C3118 2
1
402
0.1UF
CERM
20%
10V
C3119 2
1
402
0.1UF
CERM
20%
10V
C3120 2
1
402
0.1UF
CERM
20%
10V
C3121 2
1
402
0.1UF
CERM
20%
10V
C3122 2
1
402
0.1UF
CERM
20%
10V
C3123 2
1
J3100
F-RT-BGA3
D
D
R
3
-
S
O
D
I
M
M
CRITICAL
CRITICAL
D
D
R
3
-
S
O
D
I
M
M
F-RT-BGA3
J3100
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
14 25
27
27
27
27
27
27
27
27
27
27
27
27
27
DDR3 SO-DIMM Connector B
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DQS_N<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<13>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQS_P<0>
=MEM_B_DQS_N<0>
=MEM_B_DQ<12>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<24>
=MEM_B_DQ<19>
=MEM_B_DM<3>
=MEM_B_DQ<27>
=MEM_B_DQ<25>
=MEM_B_DQ<26>
=MEM_B_DQ<9>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>
=MEM_B_DQ<16>
=MEM_B_DQ<10>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DM<0>
=MEM_B_DQ<17>
=MEM_B_DQ<2>
=MEM_B_DQ<11>
=MEM_B_DQ<8>
=MEM_B_DQ<3>
=MEM_B_DQ<0>
=MEM_B_DQ<1>
PPVREF_S3_MEM_VREFDQ_B
=MEM_B_DQ<54>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DM<6>
=MEM_B_DQ<36>
=MEM_B_DQ<47>
=MEM_B_DQ<55>
=MEM_B_DQ<60>
=MEM_B_DQS_N<7>
=MEM_B_DQ<37>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<61>
=MEM_B_DQ<62>
=MEM_B_DQ<45>
=MEM_B_DQS_P<7>
=MEM_B_DQ<63>
=MEM_B_DQ<44>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DM<4>
=PPLVDDR_S3_MEM_B
PPVREF_S3_MEM_VREFCA_B
MEM_B_SA<0>
=MEM_B_DQS_N<4>
=MEM_B_DQ<35>
=MEM_B_DM<5>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<34>
=MEM_B_DQS_P<4>
=PPDDRVTT_S0_MEM_B
=MEM_B_DQ<33>
=MEM_B_DQS_P<6>
=MEM_B_DQ<50>
=MEM_B_DQ<57>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQ<51>
=MEM_B_DQ<43>
=MEM_B_DQ<59>
=MEM_B_DQ<56>
=MEM_B_DM<7>
=MEM_B_DQ<58>
=MEM_B_DQ<42>
=MEM_B_DQ<32>
MEM_B_CS_L<1>
MEM_B_BA<1>
MEM_B_CS_L<0>
=PPSPD_S0_MEM_B
MEM_B_A<12>
MEM_B_CKE<1>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_ODT<1>
=I2C_SODIMMB_SDA
MEM_EVENT_L
=I2C_SODIMMB_SCL
MEM_B_CKE<0>
MEM_B_BA<2>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_SA<1>
=MEM_B_DQ<18>
31 OF 109
A.13.0
051-8563
26 OF 80
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
15
17
3
1
7
5
9
11
13
19
23
21
25
27
29
33
31
35
43
41
45
49
47
51
53
55
59
57
2
6
8
10
12
14
16
18
20
22
24
26
28
30
34
32
36
38
40
44
42
46
48
50
54
52
56
58
60
62
64
66
68
70
72
4
71
69
67
65
63
61
39
37
99
97
95
93
91
89
87
85
81
83
161
157
159
163
165
167
151
149
135
153
76
74
78
80
82
84
86
90
88
92
96
102
98
100
106
104
112
110
108
116
114
122
120
118
126
124
130
132
128
136
134
138
140
142
148
146
144
152
150
73
75
77
79
101
111
109
113
119
121
117
123
125
131
129
133
141
147
145
158
156
154
162
160
164
168
166
172
170
174
176
178
184
182
180
188
186
194
190
192
198
196
204
202
200
155
171
169
173
177
175
107
105
103
143
139
137
127
115
94
187
185
181
208 207
209 210
211 212
206
179
183
203
201
197
191
189
193
195
199
205
28
7
28
7
7
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
MCP CHANNEL B DQS 2 -> DIMM B DQS 1
MCP CHANNEL A DQS 7 -> DIMM A DQS 7
DDR3 BYTE/BIT SWAPS-K6
SYNC_DATE=06/19/2009 SYNC_MASTER=K18_MLB
=MEM_B_DQS_N<2>
=MEM_B_DQ<15>
=MEM_B_DQ<11>
=MEM_B_DQ<12>
=MEM_B_DQ<10>
=MEM_B_DQ<23>
=MEM_B_DQ<18>
=MEM_B_DM<2>
=MEM_B_DQ<22>
=MEM_A_DQ<31>
=MEM_B_DQ<16>
=MEM_A_DQS_P<0>
=MEM_B_DQ<8>
=MEM_B_DQ<13>
=MEM_B_DQ<9>
=MEM_B_DM<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<30>
=MEM_B_DQ<29>
=MEM_B_DQS_P<3>
=MEM_B_DQ<38>
=MEM_B_DQ<33>
=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<37>
=MEM_B_DQ<32>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQ<37>
=MEM_A_DQ<46>
=MEM_A_DQ<35>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
=MEM_A_DQS_N<4>
=MEM_A_DM<4>
=MEM_A_DQ<41>
=MEM_A_DQS_P<5>
=MEM_A_DQS_N<5>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<47>
=MEM_A_DQ<43>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DM<2>
=MEM_A_DQ<16>
=MEM_A_DQ<21>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQ<20>
=MEM_A_DQ<17>
=MEM_A_DQS_P<3>
=MEM_A_DQ<30>
=MEM_A_DM<3>
=MEM_A_DQS_N<3>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<28>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DQ<29>
=MEM_A_DQS_P<7>
=MEM_A_DQS_N<7>
=MEM_A_DM<7>
=MEM_A_DQS_N<6>
=MEM_A_DM<6>
=MEM_A_DQ<49>
=MEM_A_DQ<55>
=MEM_A_DQ<52>
=MEM_A_DQ<54>
=MEM_A_DQ<48>
=MEM_A_DQ<50>
=MEM_A_DQ<53>
=MEM_A_DQ<51>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<36>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
=MEM_A_DQ<58>
=MEM_A_DQ<63>
=MEM_A_DQ<60>
=MEM_A_DQ<57>
=MEM_A_DQ<59>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<56>
=MEM_A_DQS_P<6>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<11>
=MEM_A_DQ<15>
=MEM_A_DQ<13>
=MEM_A_DQ<10>
=MEM_A_DQ<14>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<12>
=MEM_B_DQ<47>
=MEM_B_DQ<43>
=MEM_B_DQ<46>
=MEM_B_DQ<26>
=MEM_B_DQ<5>
=MEM_B_DQ<3>
=MEM_B_DQ<7>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<19>
=MEM_B_DQ<17>
=MEM_B_DQS_P<2>
=MEM_B_DQ<14>
=MEM_B_DQS_N<1>
=MEM_B_DQ<28>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DQ<31>
=MEM_B_DQ<27>
=MEM_B_DM<3>
=MEM_B_DQS_N<3>
=MEM_B_DQ<39>
=MEM_B_DM<4>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<42>
=MEM_B_DQ<44>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<45>
=MEM_B_DM<5>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<49>
=MEM_B_DQ<53>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<48>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DM<6>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQ<56>
=MEM_B_DQ<60>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<61>
=MEM_B_DM<7>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<4>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=MEM_B_DQ<6>
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<57>
=MEM_A_DQS_N<0>
=MEM_A_DM<0>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<4>
=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DQ<7>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
MEM_B_DQ<12>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<13>
MAKE_BASE=TRUE
MEM_B_DQ<15>
MAKE_BASE=TRUE
MEM_B_DQ<17>
MAKE_BASE=TRUE
MEM_B_DQ<18>
MAKE_BASE=TRUE
MEM_B_DQ<19>
MAKE_BASE=TRUE
MEM_B_DQ<20>
MAKE_BASE=TRUE
MEM_B_DQ<21>
MAKE_BASE=TRUE
MEM_B_DQ<10>
MAKE_BASE=TRUE
MEM_B_DQ<11>
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MEM_B_DQS_N<0>
MAKE_BASE=TRUE
MEM_B_DM<0>
MAKE_BASE=TRUE
MEM_B_DQ<7>
MAKE_BASE=TRUE
MEM_B_DQ<6>
MAKE_BASE=TRUE
MEM_B_DQ<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<8>
MEM_B_DQ<9>
MAKE_BASE=TRUE
MEM_A_DQS_N<4>
MAKE_BASE=TRUE
MEM_A_DQ<40>
MAKE_BASE=TRUE
MEM_A_DQ<41>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQ<43>
MAKE_BASE=TRUE
MEM_A_DQ<48>
MAKE_BASE=TRUE
MEM_A_DQ<50>
MEM_B_DQ<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<56>
MEM_A_DM<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<61>
MAKE_BASE=TRUE
MEM_A_DQ<3>
MAKE_BASE=TRUE
MEM_A_DQ<1>
MEM_A_DQ<9>
MAKE_BASE=TRUE
MEM_A_DQS_N<1>
MAKE_BASE=TRUE
MEM_A_DQ<13>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<0>
MAKE_BASE=TRUE
MEM_B_DQS_P<1>
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MEM_B_DQ<32>
MAKE_BASE=TRUE
MEM_B_DQ<33>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_P<2>
MAKE_BASE=TRUE
MEM_B_DQ<24>
MAKE_BASE=TRUE
MEM_B_DQ<27>
MAKE_BASE=TRUE
MEM_B_DQ<31>
MAKE_BASE=TRUE
MEM_B_DQ<28>
MEM_B_DQS_N<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MEM_A_DQ<49>
MAKE_BASE=TRUE
MEM_A_DM<6>
MEM_B_DQ<61>
MAKE_BASE=TRUE
MEM_A_DM<3>
MAKE_BASE=TRUE
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MEM_A_DQS_N<7>
MAKE_BASE=TRUE
MEM_A_DQ<63>
MAKE_BASE=TRUE
MEM_A_DQ<62>
MAKE_BASE=TRUE
MEM_A_DQ<60>
MAKE_BASE=TRUE
MEM_A_DQ<58>
MEM_A_DQ<57>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<59>
MAKE_BASE=TRUE
MEM_A_DQS_P<6>
MEM_A_DQS_N<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<47>
MAKE_BASE=TRUE
MEM_A_DM<5>
MAKE_BASE=TRUE
MEM_A_DQ<44>
MEM_A_DQ<45>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<46>
MEM_A_DQS_N<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<53>
MAKE_BASE=TRUE
MEM_A_DQ<54>
MAKE_BASE=TRUE
MEM_A_DQ<55>
MAKE_BASE=TRUE
MEM_A_DQ<51>
MAKE_BASE=TRUE
MEM_A_DQ<52>
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MEM_A_DQS_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<4>
MEM_A_DQ<39>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<38>
MAKE_BASE=TRUE
MEM_A_DQ<37>
MEM_A_DQ<36>
MAKE_BASE=TRUE
MEM_A_DQ<34>
MAKE_BASE=TRUE
MEM_A_DQ<33>
MAKE_BASE=TRUE
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<35>
MAKE_BASE=TRUE
MEM_A_DQ<31>
MEM_A_DQ<30>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<23>
MEM_A_DQ<22>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<2>
MEM_A_DQ<21>
MAKE_BASE=TRUE
MEM_A_DQ<20>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<18>
MEM_A_DQ<17>
MAKE_BASE=TRUE
MEM_A_DQ<28>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<25>
MEM_A_DQ<24>
MAKE_BASE=TRUE
MEM_A_DQ<29>
MAKE_BASE=TRUE
MEM_A_DQ<27>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<26>
MAKE_BASE=TRUE
MEM_B_DQ<51>
MEM_B_DQ<63>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<44>
MAKE_BASE=TRUE
MEM_B_DQ<45>
MAKE_BASE=TRUE
MEM_B_DQ<46>
MEM_B_DQ<43>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<42>
MEM_B_DQ<47>
MAKE_BASE=TRUE
MEM_B_DM<5>
MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUE
MEM_B_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<49>
MAKE_BASE=TRUE
MEM_B_DQ<50>
MAKE_BASE=TRUE
MEM_B_DQ<54>
MEM_B_DM<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<6>
MEM_B_DQ<56>
MAKE_BASE=TRUE
MEM_B_DQ<57>
MAKE_BASE=TRUE
MEM_B_DQ<58>
MAKE_BASE=TRUE
MEM_B_DQ<59>
MAKE_BASE=TRUE
MEM_B_DQ<60>
MAKE_BASE=TRUE
MEM_B_DQ<62>
MAKE_BASE=TRUE
MEM_B_DM<7>
MAKE_BASE=TRUE
MEM_B_DQS_N<7>
MAKE_BASE=TRUE
MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MEM_B_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<34>
MEM_B_DQ<35>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<16>
MEM_B_DQ<22>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<23>
MAKE_BASE=TRUE
MEM_B_DM<2>
MAKE_BASE=TRUE
MEM_B_DQ<25>
MAKE_BASE=TRUE
MEM_B_DQ<26>
MAKE_BASE=TRUE
MEM_B_DQ<29>
MAKE_BASE=TRUE
MEM_B_DQ<30>
MAKE_BASE=TRUE
MEM_B_DM<3>
MEM_B_DQS_N<3>
MAKE_BASE=TRUE
MEM_B_DQ<36>
MAKE_BASE=TRUE
MEM_B_DQ<37>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<38>
MEM_B_DQ<39>
MAKE_BASE=TRUE
MEM_B_DM<4>
MAKE_BASE=TRUE
MEM_B_DQS_N<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_P<4>
MAKE_BASE=TRUE
MEM_B_DQ<41>
MAKE_BASE=TRUE
MEM_A_DQ<7>
MAKE_BASE=TRUE
MEM_A_DQ<11>
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
MEM_A_DQ<10>
MAKE_BASE=TRUE
MEM_A_DQ<8>
MAKE_BASE=TRUE
MEM_A_DQ<14>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<12>
MEM_A_DM<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<14>
MEM_B_DM<1>
MAKE_BASE=TRUE
MEM_B_DQS_N<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<0>
MEM_B_DQ<3>
MAKE_BASE=TRUE
MEM_B_DQ<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<1>
MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<55>
MAKE_BASE=TRUE
MEM_B_DQ<53>
MAKE_BASE=TRUE
MEM_B_DQ<52>
MAKE_BASE=TRUE
MEM_B_DQ<48>
MAKE_BASE=TRUE
MEM_A_DQ<4>
MAKE_BASE=TRUE
MEM_A_DQ<5>
MEM_A_DQ<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
MAKE_BASE=TRUE
MEM_A_DQ<0>
MEM_A_DQ<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<19>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<15>
32 OF 109
A.13.0
051-8563
27 OF 80
26
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14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
14 73
OUT
OUT
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
IN
NC
RESET*
A0
A1
A2
SCL
SDA
P0
P1
P2
P5
P6
P7
P3
P4
THRM
VCC
GND PAD
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA SCL
SDA
A0
A1
GND
IN
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
both at the same time!
DAC step size:
NOTE: MEMVREG and FRAMEBUF share
0.000V - 1.501V (0x00 - 0x74)
MEM VREG
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
10mA max load
Page Notes
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
7.69mV / step @ output
+3.4mA - -3.4mA (- = sourced)
0.300V - 1.200V (+/- 450mV)
0.75V (DAC: 0x3A)
0.000V - 1.191V (0x00 - 0x5C)
0.200V - 1.050V (+/- 500mV)
0.7V (DAC: 0x8B)
CPU GTLREF (FSB)
7
Circuitry.
Circuitry.
- =I2C_PCA9557D_SDA
- =I2C_PCA9557D_SCL
- =I2C_VREFDACS_SDA
- =I2C_VREFDACS_SCL
C
4
MEM A VREF CA
3
C
0.000V - 1.501V (0x00 - 0x74)
MEM B VREF DQ
A
1 2
B
MEM A VREF DQ
Margined target:
VRef current:
Nominal value
DAC range:
PCA9557D Pin:
DAC Channel: D
5
1.998V - 1.002V (+/- 498mV)
MEM B VREF CA
1.5V (DAC: 0x3A)
D
+33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced)
soft-resets and sleep/wake cycles.
Addr=0x30(WR)/0x31(RD)
RST* on platform reset so that system
NOTE: Margining will be disabled across all
watchdog will disable margining.
(OD)
Addr=0x98(WR)/0x99(RD)
(RSVD for FBVREF)
VREFMRGN:YES - Stuffs VREF Margining
VREFMRGN:NO - Bypasses VREF Margining
a DAC output, cannot enable
Required zero ohm resistors when no VREF margining circuit stuffed
60
0.1UF
CERM
C3310
402
20%
10V
R3342
PLACE_NEAR=R7320.2:1mm
MF-LF
402
1%
1/16W
22.6K
R3340
402
MF-LF
1/16W
5%
100K
VREFMRGN:YES
R3345
VREFMRGN:YES
5%
1/16W
MF-LF
402
100K
9 72
R3344
VREFMRGN:YES
267
1/16W
1%
402
MF-LF
B4
B1
MAX4253
UCSP
U3320
B4
B1
UCSP
MAX4253
U3320
B4
B1
MAX4253
VREFMRGN:YES
B4
B1
UCSP
B4
B1 U3340
VREFMRGN:YES
UCSP
MAX4253
VREFMRGN:YES
MAX4253
B4
B1 U3340
UCSP
MF-LF
VREFMRGN:YES
1/16W
PLACE_NEAR=J2900.126:2.54mm
R3331
200
402
VREFMRGN:YES
200
R3333
1/16W
1%
402
MF-LF
R3300
SHORT
NONE
402
NONE
NONE
OMIT
SHORT
R3310
OMIT
NONE
NONE
402
NONE
24
1/16W
1%
MF-LF
402
133
1/16W
MF-LF
402
1%
R3323
1/16W
MF-LF
200
402
R3324
MF-LF
1%
1/16W
133
R3325
402
5%
1/16W
100K
MF-LF
402
100K
1/16W
2
1
MF-LF
5%
1/16W
402
R3332
1%
133
402
R3330
MF-LF
1/16W
5%
100K
VREFMRGN:YES
CRITICAL
U3310
PCA9557
QFN
C3330
0.1UF
CERM
402
20%
10V
VREFMRGN:YES
402
MF-LF
R3334
1/16W
1%
133
R3335
MF-LF
402
1/16W
100K
5%
VREFMRGN:YES
42
42
D
A
C
5
5
7
4
U3300
CRITICAL
MSOP 42
42
C3301
10V
20%
402
CERM
0.1UF
C3300
2.2UF
20%
6.3V
CERM
402-LF
C3340
VREFMRGN:YES
20%
10V
402
CERM
0.1UF
0.1UF
402
CERM
20%
10V
CRITICAL RES,MTL FILM,0,5%,0402,SM,LF 116S0004 2
R3321,R3323 CRITICAL 2
FSB/DDR3 Vref Margining
VREFMRGN_MEMVREG_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_SODIMMS_CA
VREFMRGN_CA_SODIMMB_BUF
VREFMRGN_CA_SODIMMA_BUF
PPVREF_S3_MEM_VREFCA_A
VOLTAGE=0.75V
=PP3V3_S3_VREFMRGN
VREFMRGN_SODIMMB_DQ
VREFMRGN_SODIMMA_DQ
=I2C_VREFDACS_SDA
PPVREF_S3_MEM_VREFDQ_B
VOLTAGE=0.75V
VREFMRGN_MEMVREG_FBVREF
VOLTAGE=0.75V
PPVREF_S3_MEM_VREFDQ_A
PPVREF_S3_MEM_VREFCA_B
VREFMRGN_CPUGTLREF_BUF
VREFMRGN_MEMVREG_BUF
PCA9557D_RESET_L
PP3V3_S3_VREFMRGN_CTRL
VOLTAGE=3.3V
PP3V3_S3_VREFMRGN_DAC
VOLTAGE=3.3V
CPU_GTLREF
DDRREG_FB
=I2C_VREFDACS_SCL
=I2C_PCA9557D_SDA
=I2C_PCA9557D_SCL
116S0004 RES,MTL FILM,0,5%,0402,SM,LF
R3331,R3333
VREFMRGN:YES
VOLTAGE=0.75V
MF-LF
VREFMRGN:YES
VREFMRGN_DQ_SODIMMB_BUF
C3320
402
1%
VREFMRGN:YES
R3320
1%
U3330
MAX4253
UCSP
VREFMRGN:YES
U3330
VREFMRGN_CPUGTLREF_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN:YES
R3322
VREFMRGN:YES
VREFMRGN_DQ_SODIMMA_BUF
=PPVTT_S3_DDR_BUF R3321
200
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:YES
VREFMRGN:NO
VREFMRGN:NO
33 OF 109
A.13.0
051-8563
28 OF 80
2
1
1 2
1
2
1
2
1 2
C4
C1
C3
C2
A4
A1
A3
A2
A4
A1
A3
A2
C4
C1
C3
C2
A4
A1
A3
A2
C4
C1
C3
C2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
1
2
15
3
4
5
1
2
6
7
9
12
13
14
1
6
10
11
1
78
2
1
1 2
1
2
8
3
5
4
2
1 6
7
9
10
2
1
2
1
2
1
2
1
25
7
7 60
26
25
26
SYM_VER-1
SYM_VER-1
OUT
OUT
BI
IN
OUT
SYM_VER-1
NC
NC
IN
IN
OUT
RESET*
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE +
-
PAD
(OD)
0.7V
DLY
IN
S
G
D
IN
IN
IN
IN
OUT
OUT
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
(AP_RESET_CONN_L)
Supervisor & CLKREQ# Isolation
CAMERA
ALS
BLUETOOTH
0.8 A (EDP)
(AP_CLKREQ_Q_L)
WF: Need pull-up?
RDS(ON)
CHANNEL
750 mA nominal max 518S0610
5V S3 WLAN FET
LOADING
MOSFET
P-TYPE
TPCP8102
AIRPORT
206 mA nominal max
275 mA peak
1000 mA peak
26 mOhm @4.5V
DLY = 60 ms +/- 20%
C3431
10%
PLACEMENT_NOTE=Place close to J3401.
16V X5R
0.1uF
402
C3430
402 X5R 10%
0.1uF
16V
L3401
CRITICAL
90-OHM-100MA
DLP11S
DLP0NS
CRITICAL
90-OHM
L3402
6 15 74
6 15 74
42
42
6 15 24
DLP0NS
CRITICAL
90-OHM
L3403
J3401
F-RT-SM
CRITICAL
20347-325E-12
10V
0.1uF
402
CERM
20%
C3440
24
18 65
15
R3453
402
MF-LF
1%
392K
1/16W
R3440
1/16W
MF-LF
402
100K
5%
1/16W
MF-LF
402
1%
97.6K
R3454
U3440
CRITICAL
SLG4AP016V
TDFN
65
R3451
402
5%
MF-LF
10K
1/16W
C3451
0.033UF
16V
X5R
10%
402 R3450
1/16W
5%
402
MF-LF
33K
CRITICAL
TPCP8102
23V1K-SM
Q3450
0.1UF
X5R
16V
10%
402
C3450
C3420
20%
X5R
10UF
805
10V
PLACEMENT_NOTE=Place close to Q3450.
C3421
CERM
0.1uF
402
10V
20%
PLACEMENT_NOTE=Place close to Q3450.
0402-LF
FERR-120-OHM-1.5A
L3404
C3422
0.1uF
10V
20%
CERM
402
FERR-120-OHM-1.5A
0402-LF
L3405
15 74
15 74
15 74
15 74
0.1uF
10V
20%
402
CERM
C3452
17 75
17 75
17 75
17 75
RIGHT CLUTCH CONNECTOR
I2C_ALS_SCL
PM_WLAN_EN_L
=PP5V_S3_WLAN
P5VWLAN_SS
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
I2C_ALS_SDA
PCIE_AP_D2R_P
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_N
PP5V_WLAN_F
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_CONN_P
PCIE_CLK100M_AP_CONN_N
PCIE_AP_R2D_P
PP5V_WLAN_F
VOLTAGE=5V
MIN_LINE_WIDTH=1 mm
USB_BT_CONN_N
=PP5V_S3_BTCAMERA
AP_CLKREQ_L
AP_PWR_EN
AP_RESET_L
P3V3WLAN_VMON
AP_CLKREQ_Q_L
AP_RESET_CONN_L
USB_BT_N
=PP3V3_S3_WLAN
PCIE_AP_R2D_N
PCIE_WAKE_L
PP5V_S3_BTCAMERA_F
VOLTAGE=5V
USB_CAMERA_CONN_N
PCIE_CLK100M_AP_CONN_P
VOLTAGE=5V
PP5V_WLAN
MIN_LINE_WIDTH=1 mm
USB_CAMERA_CONN_P
34 OF 109
A.13.0
051-8563
29 OF 80
1 2
1 2
4 3
1 2
4 3
1 2
4 3
1 2
23
21
11
12
13
14
15
16
18
17
19
20
8
9
10
7
6
3
4
5
22
26
27
28
2
1
25
24
31
30
29
32
2
1
1
2
1
2
1
2
4
8
6
3
5 9
7
1
2
1
2
2
1
1 2
7
8
5
6
4
3
1
2
1 2
2
1
2
1
2 1
2
1
2 1
2
1
7
29
6 79
6 79
6 74
29
6 79
7
6
6
7
6 74
6
6 79
6 79
6
6 79
BI
BI
BI
BI
VDD
WRITE_PROTECT_SW
CARD_DETECT_SW
CARD_DETECT_GND
DAT6
DAT7
DAT1
CD/DAT3
DAT2
DAT4
DAT5
VSS
VSS
CLK
CMD
DAT0
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
BI
NC
IN
OUT
OUT
OUT
BI
BI
X2
DP
CS
P
M
O
S
O
D1
V
D
D
5
V
D0
SK
DI
DO
D4
D2
D5
DM
GPIO2
D7
X1
GPIO3
GPIO1
V
D
D
1
8
O
A
V
D
D
EXTRSTZ*
D3
D
V
D
D
TESTMOD
CLK
D6
RREF
SD_CDZ
XD_CDZ
XD_CE
XD_WEZ
XD_RBZ
XD_WPZ
MS_INS
SD_WP
SD_CMD
PDMOD
MS_BS
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
S G
D
S G
IN
IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
MAX CURRENT = 800 MA
NC = DISABLE (DEFAULT)
Caesar IV Support
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
(IPD)
(IPU)
(IPU)
(IPD)
(IPU)
(IPU)
(IPD)
(IPD)
10K LOW = POWER SAVING MODE ENABLE
ADDED SERIES RESISTOR TO SD_CMD, MAX CURRENT NUMBER CHANGED TO 800MA
PDMOD: POWER DOWN MODES
Keep this net short!
516-0225
10K HIGH = REMOTE WAKE UP ENABLE
R3552
BCM57765
MF-LF 1/16W 402 5%
0
R3553
BCM57765
402
0
5% MF-LF 1/16W
31 76
31 76
31 76
31 76
F-RT-TH
J3500
SD-CARD-K19-K24
CRITICAL
31 76
1
2
L3500
GL137
0805-1
0.22UH
31 76
31 76
31
31
R3555
5%
MF-LF
0
BCM57765
1/10W
603
R3502
GL137
0
5%
1/16W
MF-LF
402
R3554
MF-LF 5%
0
402 1/16W
BCM57765
R3556
MF-LF
0
5% 1/16W 402
BCM57765
C3500
GL137
10UF
20%
X5R
603
6.3V
C3501
GL137
BYPASS=U3500.15:16:5 mm
10V
0.1UF
402
CERM
20%
402
5%
MF-LF
1/16W
1M
R3503
NO STUFF
10V
C3505
CERM
402
20%
0.1UF
GL137
20%
CERM
402
0.1UF
10V
C3506
BYPASS=U3500.4:5:5 mm
C3507
6.3V
20%
CERM1
603
2.2UF
C3508
GL137
BYPASS=U3500.11:12:5 mm
10V
20%
CERM
402
0.1UF
GL137
BYPASS=U3500.26:27:5 mm
20%
CERM
402
0.1UF
10V
C3502 C3503
GL137
CERM
402
10V
20%
0.1UF
BYPASS=U3500.35:34:5 mm
C3504
GL137
BYPASS=U3500.6:5:5 mm
0.1UF
20%
402
10V
CERM
17 75
17 75
C3511
GL137
50V
33PF
402
CERM
5%
Y3500
CRITICAL
8X4.5X1.4-SM
12.000M-100PPM
GL137
C3512
GL137
5%
CERM
402
33PF
50V
GL137A
GL137
CRITICAL
U3500
LQFP
C3514
GL137
6.3V
10UF
20%
603
X5R
MF-LF
1/16W
R3505
39K
5%
402
C3513
10V
20%
CERM
402
0.1UF
NO STUFF
715
402
MF-LF
1/16W
1%
GL137
R3506
R3507
GL137
10K
5%
1/16W
MF-LF
402
R3508
402
MF-LF
1/16W
5%
10K
NO STUFF
R3509
NO STUFF
10K
5%
1/16W
MF-LF
402
R3510
GL137
402
MF-LF
1/16W
5%
10K
R3511
GL137
402
5%
MF-LF
1/16W
0
R3512
GL137
5%
MF-LF
402
10K
1/16W
MF-LF
10K
R3513
NO STUFF
5%
1/16W
402
402
MF-LF
0
1/16W
5%
R3504
GL137
C3515
10PF
50V
402-1
CERM
5%
NO STUFF
Q3500
GL137
SSM6N15FEAPE
SOT563
Q3500
GL137
SSM6N15FEAPE
SOT563
18
24
R3550
BCM57765
0
5% 1/16W MF-LF 402
0 R3551
BCM57765
MF-LF 1/16W 5% 402
SecureDigital Card Reader
SD_D<2>
SD_D<1>
SD_WP
SD_D<7>
SD_D<6>
SD_CD_L
SD_CLK
SD_CMD
SD_D<0>
SD_D<3>
SD_D<4>
SD_D<5>
VOLTAGE=3.3V
PP3V3_S3_CARDREADER_DVDD
SDCONN_CMD
SDCONN_DATA<2>
VOLTAGE=3.3V
PP3V3_S3_CARDREADER_AVDD
SDCONN_WP
SD_D<4..7>
MAKE_BASE=TRUE
=PP3V3_S3_CARDREADER
SDCARD_PLT_RST
SDCARD_PLT_RST_L
SD_D<2>
SD_D<1>
SD_D<0>
SD_D<3>
SDCONN_DATA<0>
SD_CLK
SDCONN_DATA<1>
SDCONN_CLK
SDCONN_DATA<4..7>
SDCONN_DATA<3>
GL137_RREF
GL137_TESTMOD
GL137_RESET_L
VOLTAGE=1.8V
PP1V8_S3_CARDREADER
GL137_GPIO1
GL137_CLK12M_X1
GL137_GPIO2
USB_SDCARD_N
USB_SDCARD_P
SDCONN_CD
=PP3V3_S0_SDCONN
SD_CLK_R
GL137_PDMOD
MAKE_BASE=TRUE
SD_WP
MAKE_BASE=TRUE
SD_CMD
SDCARD_RESET
GL137_CLK12M_X2
SD_CD_L
MAKE_BASE=TRUE
PP3V3_SW_SD_PWR
VOLTAGE=3.3V
MAKE_BASE=TRUE
35 OF 109
A.13.0
051-8563
30 OF 80
1 2
1 2
20
19
18
17
3
6
5
2
7
8
9
1
10
11
13
12
16
14
15
4
1 2
1
2
1 2
1 2
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2 1
1 2
14
8
20
3
6
43
2
5
40
19
22
21
28
37
30
7
47
38
13
46
48
3
5
41
1
6
18
29
2
6
1
5
17
39
32
10
23
1
31
42
44
45
24
3
41
2
33
1
2 9 5
3
4
2
7
1
6
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
2
1
3
4
5
6
1
2
1 2
1 2
30 76
30 76
30
30 76
30 76
30
30 76
30 76
30 76
30 76
30 76
30 76
30 76
7 30 76
30 76
30 76
30 76
30 76
7
76
30
30 76
30
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
NC
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
IN
IN
AVDDH
B
I
A
S
V
D
D
H
V
D
D
C
V
D
D
I
O
X
T
A
L
V
D
D
H
V
D
D
I
O
V
D
D
C
AVDDL
SI
SO
CS*
RDAC
VDDC
UART_MODE
SCLK
LOW_PWR
LINKLED*
CLKREQ*
PERST*
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_TXD_P
PCIE_RXD_P
V
D
D
C
V
D
D
C
V
D
D
I
O
P
C
I
E
_
P
L
L
V
D
D
L
G
P
H
Y
_
P
L
L
V
D
D
L
DC2
DC1
NC
VMAIN_PRSNT
VAUX_PRSNT
ENERGY_DET
DC3
DC4
NC
GPIO_2
TRD1_N
TRD1_P
TRD0_N
SMB_DATA TRD0_P
TRD2_N
TRD2_P
TRD3_P
THRM_PAD
XTALI
XTALO
SPD100LED*
TRAFFICLED*
TRD3_N
DC5
PCIE_TXD_N
SPD1000LED*
DC0
W
A
K
E
*
PCIE_VDDL
R
E
G
C
T
L
1
2
V
D
D
I
O
PCIE_RXD_N
GPIO_0/SERIAL_DO
GPIO_1/SERIAL_DI
SMB_CLK
VDDC
VERSION 2
OUT
RESET*
CS*
SCK
SO
WP*
SI
GND
VCC
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
PHY Non-Volatile Memory
ROM contains MAC address, PCIe config
Required for proper PHY operation.
info as well as code for Bonjour proxy.
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
CR_BUS_PWR is not for SD Card power,
just decoupling for BCM57765 CR I/Os.
BCM57765 SR pins are internal 1.2V switching regulator.
(IPD-BCM5764M)
(IPD)
(OD)
(OD)
If PHY is always powered then alias
N-channel FET isolation suggested.
(IPD)
60-ENERGY_DET
13-WAKE*
14-VDDC
06-VDDC
17-VDDC
55-VDDC
396mA (1000base-T, Caesar II)
=ENET_WAKE_L to PCIE_WAKE_L.
(See note)
(See note)
with no stubs.
Keep net short,
86mA (1000base-T, Caesar II)
26-PCIE_VDDL
20-XTALVDDH
59-SMB_CLK
(IPD)
53-VMAIN_PRSNT
16-VDDIO
NOTE: BCM5764M requires SI pull-down instead of SO.
ROM is used then the straps must change.
Atmel AT45DB011D (1Mbit) ROM. If a different
other 3 SPI pins configures BCM57765 for the
NOTE: Pull-down on SO plus internal pull-ups on
(Required ROM size TBD)
WAKE#
Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
(
I
P
U
)
(
I
P
D
)
54-VAUX_PRSNT
58-SMB_DATA
BCM57765 supports both active-levels for WP.
BCM5764M pin-function
All parts below BOMOPTIONed BCM5764M
BCM5764M Support
All resistors above BOMOPTIONed BCM57765
C3921
0.1UF
X7R-CERM
402
16V
10%
C3935
10UF
805
10%
6.3V
X5R
C3925
4.7UF
X5R-CERM
603
10%
6.3V
L3925
FERR-600-OHM-0.5A
SM
CRITICAL
C3920
603
6.3V
10%
X5R-CERM
4.7UF
L3920
FERR-600-OHM-0.5A
SM
CRITICAL
L3900
CRITICAL
SM
FERR-600-OHM-0.5A
L3905
SM
CRITICAL
FERR-600-OHM-0.5A
R3942
BCM57765
402
MF-LF
5%
1K
1/16W
15 74
15 74
24 76
15
24 31
8 18
24
24
C3951
0.1uF
402
X5R
16V
10%
C3950
402
0.1uF
X5R
16V
10%
C3956
16V
10%
0.1uF
X5R
402
C3955
0.1uF
402
X5R
16V
10%
R3965
1.24K
402
1%
1/16W
MF-LF
15 74
15 74
15 74
15 74
32 76
32 76
32 76
32 76
32 76
32 76
32 76
32 76
R3941
MF-LF
1/16W
5%
4.7K
402
BCM57765
R3940
MF-LF
5%
402
1/16W
4.7K
BCM57765
BCM5764M
0 R3980
402 MF-LF 1/16W 5%
R3984
402 1/16W 5%
4.7K
BCM5764M
MF-LF
R3999 0
5% 1/16W 402
BCM5764M
MF-LF
MF-LF
0 R3978
5% 1/16W 402
BCM57765
30 76
R3983
402 1/16W 5%
4.7K
BCM5764M
MF-LF
R3982 1K
5% 1/16W MF-LF
BCM5764M
402
L3999
CRITICAL SM
BCM5764M
PLACE_NEAR=U3900.26:2 mm
FERR-600-OHM-0.5A
C3998
6.3V
4.7UF
X5R-CERM
603
10%
BCM5764M
PLACE_NEAR=L3999.1:1 mm
C3999
0.1UF
X7R-CERM
402
10%
16V
BCM5764M
MF-LF
R3977
BCM57765
0
5% 1/16W 402
1/16W
0 R3976
BCM57765
MF-LF 5% 402
5%
BCM57765
402 MF-LF 1/16W
0 R3975
30 76
30 76
30 76
30 76
30 76
30 76
30 76
30 76
R3974
MF-LF 1/16W 5%
0
BCM57765
402
0 R3973
5% 1/16W MF-LF 402
BCM57765
30
R3943
5%
MF-LF
1/16W
402
BCM57765
0
R3981
MF-LF 1/16W 5%
0
BCM5764M
402
R3986
402 MF-LF 1/16W 5%
0
BCM5764M
R3985
5% 1/16W 402
1K
BCM5764M
MF-LF
R3989
402 1/16W 5%
0
BCM5764M
MF-LF
R3987
402 1/16W 5%
0
BCM5764M
MF-LF
R3988
402 1/16W 5%
0
BCM5764M
MF-LF
R3900
BCM57765
0
402
1/16W
MF-LF
5%
R3915
BCM57765
0
402
1/16W
MF-LF
5%
R3990
BCM57765
1/16W
5%
402
MF-LF
4.7K
R3998
402 1/16W 5%
0
BCM5764M
MF-LF
30 76
30
U3900
CRITICAL
OMIT
BCM5764M
QFN-8X8
C3970
4.7UF
603
X5R-CERM
6.3V
10%
BCM57765
C3971
BCM57765
X7R-CERM
402
10%
16V
0.1UF
C3972
BCM57765
X7R-CERM
402
10%
16V
0.1UF
R3972
402 MF-LF 1/16W 5%
0
BCM57765
17 31
R3910
MF-LF
1/16W
402
4.7K
5%
L3910
SM
FERR-600-OHM-0.5A
CRITICAL
X7R-CERM
C3910
16V
10%
402
0.1UF
C3911
X7R-CERM
16V
10%
402
0.1UF
C3990
X7R-CERM
0.1UF
402
10%
16V
C3900
X7R-CERM
0.1UF
402
10%
16V
C3905
X7R-CERM
0.1UF
402
10%
16V
C3930
10%
6.3V
X5R-CERM
603
4.7UF
C3931
0.1UF
16V
10%
402
X7R-CERM
L3930
FERR-600-OHM-0.5A
SM
CRITICAL
C3915
X5R-CERM
603
6.3V
10%
4.7UF
C3916
10%
X7R-CERM
0.1UF
16V
402
OMIT
SOIC-8S1
AT45DB011D
U3990
R3997
4.7K
MF-LF
402
5%
1/16W
BCM5764M
C3936
10%
402
0.1UF
16V
X7R-CERM
C3926
16V
10%
X7R-CERM
0.1UF
402
Ethernet PHY (Caesar II/IV)
ENET_MDI_N<1>
ENET_MDI_N<3>
BCM57765_MEDIA_SENSE
SDCONN_DATA<0>
SDCONN_CLK
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<6>
PP3V3R1V8_SW_SD_VIO
VOLTAGE=3.3V
SDCONN_WP
SDCONN_CMD
SDCONN_DATA<5>
SDCONN_DATA<7>
=PP3V3_ENET_PHY
=PP1V2_ENET_PHY
BCM57765_CR_DATA<6>
BCM57765_CR_DATA<6>
BCM57765_CR_CMD
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
=ENET_WAKE_L
BCM5764_SCLK
BCM5764_CS_L
BCM5764_MISO
BCM5764_MOSI
BCM57765_SR_VFB =ENET_WAKE_L
=PP3V3_S0_ENETPHY
PP3V3_ENET_PHY_XTALVDDH
BCM57765_SR_LX
BCM57765_CR_DATA<7>
BCM57765_XTALVDDH
BCM57765_VDDO_PIN20
BCM57765_VMAIN_PRSNT
=PP3V3_S0_ENETPHY
BCM57765_CR_CMD
BCM57765_SMB_CLK
BCM57765_SR_VDD
BCM57765_CE_L_MS_INS_L
BCM57765_CR_DATA<5>
BCM57765_CR_LED
BCM57765_SR_VDD
BCM5764_MISO
BCM5764_MOSI
BCM5764_CS_L
BCM5764_RDAC
BCM57765_SMB_CLK
BCM57765_SMB_DATA
BCM5764_SCLK
BCM57765_WAKE_L
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
PCIE_ENET_R2D_N
PCIE_ENET_D2R_C_P
=PP1V2_ENET_PHY
BCM57765_CR_DATA<5>
BCM57765_VMAIN_PRSNT
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_P<3>
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
TP_BCM5764_SPD100LED_L
TP_BCM5764_TRAFFICLED_L
PCIE_ENET_D2R_C_N
BCM57765_SR_VFB
ENET_RESET_L
ENET_CLKREQ_L
BCM57765_CE_L_MS_INS_L
TP_BCM57765_XD_DET
BCM57765_CR_LED
BCM57765_CR_DATA<7>
ENET_LOW_PWR
PCIE_ENET_R2D_P
BCM57765_CR_DATA<4>
ENET_MDI_P<1>
ENET_MDI_N<0>
BCM57765_SR_LX TP_BCM57765_SR_VDDP
BCM57765_SD_DETECT
ENET_ENERGY_DET
ENET_ENERGY_DET
SDCONN_CD
SDCONN_DATA<4>
ENET_MDI_P<0>
=PP3V3_ENET_PHY
=PP3V3_ENET_PHY
PP3V3_ENET_PHY_XTALVDDH
VOLTAGE=3.3V
VOLTAGE=3.3V
BCM57765_XTALVDDH
BCM57765_VDDO_PIN20
VOLTAGE=3.3V
VOLTAGE=1.2V
PP1V2_ENET_PHY_GPHYPLL
PP1V2_ENET_PHY_PCIEPLL
VOLTAGE=1.2V
VOLTAGE=1.2V
PP1V2_ENET_PHY_AVDDL
VOLTAGE=3.3V
PP3V3_ENET_PHY_BIASVDDH
PP3V3_ENET_PHY_AVDDH
VOLTAGE=3.3V
39 OF 109
A.13.0
051-8563
31 OF 80
2
1
2
1
2
1
2 1
2
1
2 1
2 1
2 1
1
2
1 2
1 2
1 2
1 2
1
2
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
2 1
2
1
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
4
2
4
8
3
7
1
7
72
0
6
2
1
4
3
9
4
5
5
1
64
65
63
38
6
10
66
4
3
12
11
30
31
28
33
6
1
3
5
5
6
2
9
3
2
3
6
23
22
52
53
54
60
24
25
1
9
43
44
41
58 40
47
46
50
6
9
18
19
2
67
49
57
27
68
21
1
3
26
1
5
1
6
34
5
8
59
55
2
1
2
1
2
1
1 2
1
2
2 1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2 1
2
1
2
1
7
6
3
4
2
8
5
1
1
2
2
1
2
1
7 24 31 64
7 31
31 76
31
76
31 76
31
31
31
31
31 64 24 31
7 31
31
31 64
31 76
31
31
31
7 31
31 76
31
31 64
31
31 76
31
31 64
31
31
31
31
31
74
74
7 31
31
76
31
74
31 64
31
31
31
76
74
76
31 64 64
17 31
7 24 31 64
7 24 31 64
31 31
31
BI
RX
TX
BI
RX
TX
BI
I
O
N
C
N
C
I
O
N
C
I
O
I
O
N
C
G
N
D
I
O
N
C
N
C
I
O
N
C
I
O
I
O
N
C
G
N
D
BI
BI
BI
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
514-0636
Transformers should be
(NONE)
(NONE)
(NONE)
Page Notes
mirrored on opposite
sides of the board
D4000.1:
D4001.1:
D4000.5:
D4001.5:
31 76
T4000
SM
CRITICAL
TLA-6T213HF
R4000
402
MF-LF
1/16W
5%
75
R4001
402
MF-LF
1/16W
5%
75
R4002
402
MF-LF
1/16W
5%
75
R4003
402
MF-LF
1/16W
5%
75
C4008
CRITICAL
1000PF
1206
CERM
2KV
10%
31 76
C4006
PLACE_NEAR=T4001.4:2.54 mm
0.1UF
402
X5R
16V
10%
C4004
0.1UF
402
X5R
16V
10%
C4002
0.1UF
402
X5R
16V
10%
T4001
CRITICAL
SM
TLA-6T213HF
C4000
0.1UF
402
X5R
16V
10%
31 76
J4000
CRITICAL
RJ45-M97-3
F-RT-TH
3
D4000
PLACE_NEAR=T4000.1:4 mm
SLP2510P8
ENET_ESD
CRITICAL
RCLAMP0524P
3
D4001
SLP2510P8
ENET_ESD
CRITICAL
RCLAMP0524P
31 76
31 76
31 76
31 76
31 76
Ethernet Connector
ENET_MDI_P<3>
ENET_MDI_N<3>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_N<0>
ENET_MDI_P<0>
ENETCONN_P<3>
ENETCONN_N<3>
ENETCONN_N<2>
ENETCONN_P<1>
ENETCONN_N<1>
ENET_CTAP1
ENETCONN_CTAP
ENET_CTAP3
ENET_CTAP2
ENETCONN_P<2>
ENETCONN_P<0>
ENETCONN_N<0>
ENET_CTAP0
ENET_BOB_SMITH_CAP
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1
3
2
12
11
9
8
7
4
5
6
10
1
2
1
2
1
2
1
2
1 2
2
1
2
1
2
1
1
3
2
12
11
9
8
7
4
5
6
10
2
1
1
2
4
12
11
10
9
6
5
3
7
8
1 10 2 9 4 5 7 6 1 10 2 9 4 5 7 6
79
79
79
79
79
79
79
79
DS2
ATBUSH
ATBUSN
VP25
OCR_CTL_V10
VAUX_DETECT
TMS
TCK
REFCLKN
PCIE_TXD0P
TRST*
ATBUSB
TDI
DS1
TPA0N
TPA0P
AVREG
CE
CLKREQN
FW_RESET*
FW620*
JASI_EN
MODE_A
NAND_TREE
OCR_CTL_V12
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PERST*
R0
REFCLKP
REGCLT
REXT
SCIFCLK
SCIFDAIN
SCIFDOUT
SCIFMC
SCL
SDA
SE
SM
TDO
TPA1N
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
TPBIAS0
TPBIAS1
TPBIAS2
TPCPS
VAUX_DISABLE
VBUF
VDDH VP VREG_PWR
WAKE*
XI
XO
DS0
TPA1P
VDD33 VDD10
VREG_VSS VSS
SERIAL EEPROM
MISCELLANEOUS
CONTROLLER
POWER MANAGEMENT
TEST CONTROLLER
PCI EXPRESS PHY
CHIP RESET
SCIF
1394 PHY
NC
NC
NC
NC
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
NC
NC
3 6
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PAGE TITLE
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2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
110 mA Digital Core
WITHOUT PLUG DETECT:
WITH PLUG DETECT:
NT-18 (IPU)
- Alias both signals to drop = prefix
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
- Gate CLKREQ# based on PHY power
- TP (or NC) PME#
NT-13
NT-21 (IPU)
NT-20 (IPU)
FIXME!!! - TYPO IN SYMBOL REGCTL
NT-10 (IPD)
NT-19 (IPU)
(IPU)
NT-17
NAND tree order.
NOTE: NT-xx notes show
(IPU) NT-8
NT-9
(Reserved)
NT-OUT
NT-5
NT-6
NT-7
25 mA PCIe SerDes
7 mA I/O
138 mA
(IPD) NT-3
(IPD) NT-4
NT-16 (IPD)
NT-14 (IPD)
NT-15 (IPD)
(IPD) NT-11
(IPD)
(IPD)
(IPU)
(IPD) NT-1
(IPD)
NT-12 (IPD)
(OD)
(OD)
1394B physical plug detect.
0 mA VReg PWR
17 mA PCIe SerDes
(IPD) NT-2
114 mA FireWire PHY
135 mA
402
MF-LF
1/16W
1%
191
R4170
10%
402
6.3V
0.33UF
CERM-X5R
C4162
470K
MF-LF
402
5%
1/16W
R4162
FW643E
CRITICAL
BGA
U4100
OMIT
402
50V
5%
22PF
CERM
C4151
402
CERM
22PF
5%
50V
C4150
402
1/16W
MF-LF
200K
1%
R4160
412
MF-LF
1%
1/16W
402
R4150
402
1/16W
5%
MF-LF
10K
R4163
402
5%
MF-LF
10K
1/16W
R4164
402
10K
MF-LF
5%
1/16W
FW643_LDO
R4165
402
1/16W
5%
MF-LF
10K
R4166
10%
1UF
402
6.3V
CERM
C4130
10%
1UF
402
6.3V
CERM
C4131
10%
1UF
402
6.3V
CERM
C4100
10%
1UF
402
6.3V
CERM
C4101
10%
402
6.3V
CERM
1UF
C4132
10%
1UF
6.3V
CERM
C4102
402
10%
1UF
402
6.3V
CERM
C4103
10%
1UF
402
6.3V
CERM
C4135
10%
1UF
402
6.3V
CERM
C4136
10%
1UF
402
6.3V
CERM
C4104
10%
1UF
402
6.3V
CERM
C4110
10%
1UF
402
6.3V
CERM
C4105
10%
1UF
402
6.3V
CERM
C4106
10%
1UF
402
6.3V
CERM
C4120
402
10%
1UF
6.3V
CERM
C4121
10%
1UF
402
6.3V
CERM
C4122
10%
1UF
402
6.3V
CERM
C4123
10%
1UF
402
6.3V
CERM
C4124
0.1UF
10V
20%
CERM
402
C4141
10%
1UF
402
6.3V
CERM
C4111
1UF
CERM
6.3V
402
10%
C4140
15 74
15 74
15 74
15 74
15 74
15 74
34
34
MF-LF
2.94K
402
1/16W
1%
R4161
35
35
35
35 77
35 77
35 77
35 77
35
35
35 77
35 77
35 77
35 77
35
35
35
34 35
35
120-OHM-0.3A-EMI
0402-LF
L4130
0402-LF
120-OHM-0.3A-EMI
L4135
34
120-OHM-0.3A-EMI
0402-LF
L4110
CRITICAL
SM-3.2X2.5MM
24.576MHZ
Y4150
PLACEMENT_NOTE=Place C4170 close to U1400
10% 402 X5R 16V 0.1UF
C4170
10% 0.1UF 402 X5R 16V
C4171
10% 0.1UF 402 X5R 16V
C4175
10% 402 X5R 16V 0.1UF
C4176
FireWire LLC/PHY (FW643E)
=PP1V0_FW_FWPHY
=PP3V3_FW_FWPHY
FW_CLK24P576M_XI
PCIE_FW_D2R_P
PCIE_FW_D2R_C_P
PCIE_FW_D2R_N PCIE_FW_D2R_C_N
PCIE_FW_R2D_C_N
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_P
TP_FW643_SCIFCLK
=FW_CLKREQ_L
TP_FW643_SCIFMC
FW_CLK24P576M_XO
TP_FW643_OCR10_CTL
PCIE_CLK100M_FW_N
TP_FW643_AVREG
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_MODE_A
TP_FW643_NAND_TREE
PCIE_CLK100M_FW_P
TP_FW643_SCIFDOUT
TP_FW643_SDA
TP_FW643_SE
TP_FW643_SM
TP_FW643_TDO
FW_P1_TPA_P
FW_P1_TPA_N
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
FW_P0_TPBIAS
FW_P2_TPBIAS
=FW_PHY_DS2
=FW_PHY_DS0
=PP3V3_FW_FWPHY
=FW_PHY_DS1
FW_P1_TPBIAS
FW_P0_TPB_P
FW_P0_TPA_P
FW_P0_TPA_N
FW643_PU_RST_L
FW_RESET_L
FW643_SCL
TP_FW643_VAUX_ENABLE
FW643_VAUX_DETECT
FW643_REGCTL
=FW_PME_L
FW643_TRST_L
TP_FW643_TMS
TP_FW643_SCIFDAIN
FW643_REXT
TP_FW643_JASI_EN
TP_FW643_VBUF
TP_FW643_TDI
TP_FW643_TCK
=PPVP_FW_PHY_CPS
FW_CLK24P576M_XO_R
FW643_TPCPS
FW643_R0
VOLTAGE=3.3V
PP3V3_FW_FWPHY_VDDA
VOLTAGE=3.3V
PP3V3_FW_FWPHY_VP25 PP1V0_FW_FWPHY_AVDD
VOLTAGE=1.0V
FW_P1_TPB_N
41 OF 109
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1
2
2
1
1
2
B
1
2
E13
E
1
0
C
1
3
A13
A11
G
8
G
1
0
G
6
J
9
L
1
1
L
3
K
1
0
K
6
L
9
L
6
D
8
J12
E1
M3
M4
N9
N6
N1
J
5
E
5
E
4
B13
N2
E12
B8
A8
A
1
N
1
1
N
3
A10
L13
L2
K13
D12
D1
J2
K1
J13
N8
N7
N5
N4
B11
N10
D13
L8
G2
G1
H1
F2
N12
M11
M13
N13
M1
B5
B3
A3
B9
A9
B6
A6
B4
A4
B7
C3
A2
B10
D2
H13
B
1
M
2
A
1
2
D
5
D
6
L
5
L
1
0
K
1
2
B
2
D
4
F
7
F
8
F
1
0
G
4
H
4
H
6
D
7
H
7
H
8
H
1
0
J
4
J
1
0
K
4
K
5
K
7
D
9
D
1
0
E
9
F
4
F
6
C2
G13
F13
F12
A5
C
1
2
J
1
G
1
2
F
1
C
1
K
2
M
1
2
L
1
H
2
H
1
2
E
2
L
1
2
L
7
K
9
K
8
G
7
1 2
1 2
1
2
1 2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2 1
2 1 2 1
3
1
2
4
1 2
1 2
1 2
1 2
7 34
7 33 34 35
74
74
74
74
7 33 34 35
35
G
D
S
IN
IN
G
D
S
OUT
IN
S
G
D
(SYM-VER2)
G
S (SYM-VER1)
D
GND
VOUT
ON
VIN
GND
VOUT
ON
VIN
IN
OUT
IN
OUT
IN
IN
D
G S
RESET*
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE +
-
PAD
(OD)
0.7V
DLY
3 6
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REVISION
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PAGE TITLE
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Apple Inc.
PAGE
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3 4 5 6 7 8
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LSI FireWire PHY requires 1.0V.
To avoid an extra power supply,
1.05V is used with a series R
Load Switch
50 mOhm Max
FireWire Port Power Switch
2) FW643 WAKE# (PME#) when PHY is powered.
- =FW_CLKREQ_L
- =FW_PME_L
Pull-up provided on another page.
1) 5K Pull-down Detect when FW_PWR_EN is low.
Dual-purpose output:
FireWire Port 5K Pull-Down Detect
Host can detect as load on TPBIAS signal.
All FireWire devices require 5K pull-down on TPB pair.
Current source only active when FW_PWR_EN is low.
- =PPBUS_FW_FET (FW VP FET Output)
- =PPBUS_S5_FWPWRSW (FW VP FET Input)
Page Notes
- =PP3V3_S0_FWLATEVG
- =PP1V0_FW_FET_R (1.0V FET Output)
(NONE)
- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)
- =PP3V3_FW_FWPHY (PHY 3.3V Power)
- =PP3V3_FW_FET (3.3V FET Output)
- =PP3V3_FW_P3V3FWFET (3.3V FET Input)
- =PP1V05_FW_P1V0FWFET (1.0V FET Input)
- =PP1V0_FW_FWPHY (PHY 1.0V)
- =PP3V3_S0_FWPWRCTL
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
Part
Max Output: 2A
R(on) 18 mOhm Typ
TPS22924C
to reduce voltage.
Type
U4201 & U4202
1.0V FW Switch
FireWire PHY WAKE# Support
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
EDP = 0.14A (85C)
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
Pull-up provided by another page.
Supervisor & CLKREQ# Isolation
3.3V FW Switch
DLY = 60 ms +/- 20%
402
25V
X5R
10%
0.1UF
C4260
1/16W
5%
402
MF-LF
300K
R4260
470K
1/16W
5%
402
MF-LF
R4261
1.1A-24V
MINISMDC110H24
CRITICAL
F4260
CRITICAL
CRS08-1.5A-30V
SM
D4260
CRITICAL
SOT563
BC847CDXV6TXG
Q4270
SOT563
BC847CDXV6TXG
CRITICAL
Q4270
MF-LF
5%
402
1/16W
330K
R4270
56K
MF-LF
402
5%
1/16W
R4271
5%
1/16W
MF-LF
402
12K
R4273
MF-LF
402
5%
1K
1/16W
R4272
CRITICAL
DMB53D0UV
SOT-563
Q4275
CRITICAL
SOT-563
DMB53D0UV
Q4275
10%
0.1UF
402
X5R
16V
C4270
33 35
1/16W
MF-LF
5%
1K
402
R4275
15 34
DMB53D0UV
SOT-563
CRITICAL
Q4276
CRITICAL
DMB53D0UV
SOT-563
Q4276
5%
1/16W
MF-LF
402
100K
R4276
NO STUFF
0.1UF
10%
16V
X5R
402
C4276
MF-LF
5%
1/16W
402
10K
R4277
15
33
SOT-363
BSS8402DW
Q4262
402
1/16W
5%
MF-LF
10K
R4262
BSS8402DW
SOT-363
Q4262
402
25V
X5R
10%
0.1UF
NO STUFF
C4261
10
5%
1/16W
MF-LF
402
R4263
TPS22924
CRITICAL
CSP
U4201
TPS22924
CRITICAL
CSP
U4202
35
402
MF
1/16W
1%
0.549
R4202
33
1/16W
402
MF-LF
5%
10K
R4283
2
1
15 34
15
402
25V
X5R
10%
0.1UF
C4290
24
33
FDC638P_G
SM
CRITICAL
Q4260
SOD-VESM-HF
SSM3K15FV
Q4261
402
CERM
6.3V
10%
1UF
C4201
402
CERM
6.3V
10%
1UF
C4202
CRITICAL
SLG4AP016V
TDFN
U4290 1/16W
MF-LF
402
5%
100K
R4290
FireWire Port & PHY Power
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FW_RESET_L
FW_PWR_EN
FW_CLKREQ_L
=FW_RESET_L
FW_RESET_R_L
=PP3V3_S0_FWPWRCTL
=PP1V0_FW_FWPHY
=FW_CLKREQ_L
VOLTAGE=12.6V
PPBUS_FW_FWPWRSW_D
=PP3V3_FW_FET
FWPORT_PWR_EN
FWPORT_PWREN_L
FWPORT_FASTOFF_L_DIV
=PPBUS_S5_FWPWRSW
=PP3V3_S0_FWLATEVG
FWPORT_FASTOFF_L
FWPORT_PWREN_L_DIV
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
=FW_PME_L
FW_PME_L
FW_PWR_EN
FW_P1_TPBIAS
FW_WAKE
=PP3V3_FW_FWPHY
FW_5KPD_DET_RC
=PP1V05_S0_FWPWRCTL
FW_P1_TPBIAS_R FWDET_EMIT
FW_PWR_EN_L
FWDET_MIRROR
MAKE_BASE=TRUE
FW643_WAKE_L
=PPBUS_FW_FET
=PP1V0_FW_FET_R
PP1V05_FW_FET
VOLTAGE=1.05V
=PP3V3_FW_P3V3FWFET
=PP1V05_FW_P1V0FWFET
MAKE_BASE=TRUE
FW_5KPD_DET_L
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1
2
1
2
1
2
6
2
1
4
5
3
2
1
1
2
4
5
3
6
2
1
1
2
2
1
1
2
3
5
4
1
2
1
6
2
2
1
1
2
C
1
A1
B1
C2
B2
A2
C
1
A1
B1
C2
B2
A2
1
2
2
1
5
6
2
1
4
3
1
2
3
2
1
2
1
4
8
6
3
59
7
1
2
1
2
7
7 33
7
7
7 35
7 33 35
7
7
7
7
7
SC/NC
TPA+ TPA(R)
VG
VP TPB+
TPB(R) TPB-
TPA-
CHASSIS
GND
S
G
D
(
S
Y
M
-
V
E
R
2
)
G
S (SYM-VER1)
D
NC
VCC
VCLMP
D1-
GND
D2-
D2+
D1+
FWPWR_EN OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
IN
3 6
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PAGE TITLE
C
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2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
FW643 has internal leakage path from TPCPS pin to VDD33.
FireWire TPA/TPB pairs to their
Page Notes
- =PPVP_FW_PHY_CPS_FET (From Port)
the necessary aliases to map the
properly terminate unused signals.
FireWire PHY Config Straps
Configures PHY for:
- Port "1" Bilingual (1394B)
Unused FireWire Ports
Disabled per LSI instructions
(All unused port signals TP/NC)
FW643 TPCPS Leakage Protection
FET blocks current to TPCPS until VDD33 is powered.
- =PPVP_FW_PORT1
To FW643
From Port
- =PPVP_FW_PHY_CPS (To PHY)
- =PP3V3_S0_FWLATEVG
- =PP3V3_FW_FWPHY
- =FW_PHY_DS1
- =FW_PHY_DS2
(NONE)
1394b implementation based on Apple
PORT 1
OUTPUT
INPUT
TPB-
TPB<R>
NC
VP
TPB+
BILINGUAL
VG
TPA-
TPA+
TPA<R>
514S0605
AREF needs to be isolated from all
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
(FW_PORT1_BREF)
local grounds per 1394b spec
Note: Trace PPVP_FW_PORT1 must handle up to 5A
(FW_PORT1_TPA_N)
(FW_PORT1_TPA_P)
(FW_PORT1_TPB_N)
Cable Power
(GND)
(FW_PORT1_TPB_N)
Place close to FireWire PHY
Termination
FireWire Design Guide (FWDG 0.6, 5/14/03)
(FW_PORT1_TPB_P)
(FW_PORT1_TPA_P)
(FW_PORT1_TPB_P)
(FW_PORT1_TPA_N)
"Snapback" & "Late VG" Protection
SWAPPED FOR BETTER ROUTING)
(PINS 5/6 AND 7/8 ARE
appropriate connectors and/or to
NOTE: This page is expected to contain
- =FW_PHY_DS0
SIGNAL_MODEL=EMPTY
56.2
MF-LF
402
1%
1/16W
R4363
4.99K
MF-LF
402
1%
1/16W
R4364
1/16W
1%
402
MF-LF
56.2
SIGNAL_MODEL=EMPTY
R4362
5%
402
CERM
220pF
C4364
25V
1%
SIGNAL_MODEL=EMPTY
1/16W
402
MF-LF
56.2
R4361
6.3V
10%
402
CERM-X5R
0.33UF
C4360
1/16W
R4360
SIGNAL_MODEL=EMPTY
56.2
MF-LF
402
1%
PLACE_NOTE=J4310.5:2 mm
0.1uF
X7R
603-1
10%
50V
C4319
R4319
1/16W
5%
402
MF-LF
1M
0.01UF
X7R
402
10%
50V
C4314
CRITICAL
FERR-250-OHM
SM
L4310
CRITICAL
1394B-M97
F-RT-TH
J4310
R4381
1/16W
1%
402
MF-LF
10K
R4382
10K
MF-LF
402
1%
1/16W
R4380
1/16W
1%
402
MF-LF
10K
Q
4
3
0
0
B
S
S
8
4
0
2
D
W
S
O
T
-
3
6
3
Q4300
BSS8402DW
SOT-363
R4312
330K
MF-LF
402
5%
1/16W
R4311
470K
MF-LF
402
5%
1/16W
U4350
TPD4S1394
LLP
CRITICAL
C4350
402
10%
X5R
16V
0.1UF
1/16W
100K
5%
R4350
MF-LF
402
34
33
33
33
33 77
33 77
33 77
33 77
33
33
33
33
33
33
33 77
33 77
33 77
33 77
33 34
FireWire Connector
=PP3V3_S0_FWLATEVG
FWPORT_PWR_EN
TP_FWLATEVG_VCLMP
FW_P1_TPBIAS
FW_PORT1_AREF
FW_P1_TPB_N
FW_P1_TPB_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_PORT1_TPB_C
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS
CPS_EN_L_DIV
=PP3V3_FW_FWPHY
CPS_EN_L
FW_P2_TPA_N
FW_P2_TPB_P
FW_P2_TPB_N
FW_P0_TPB_N
FW_P2_TPA_P
FW_P2_TPBIAS
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPBIAS
=FW_PHY_DS1
=FW_PHY_DS2
=FW_PHY_DS0
=PP3V3_FW_FWPHY
=PPVP_FW_PHY_CPS_FET
PPVP_FW_PORT1_F
VOLTAGE=33V
VOLTAGE=12.6V
MAKE_BASE=TRUE
PPVP_FW_CPS
NO_TEST=TRUE
NC_FW2_TPBN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBP
MAKE_BASE=TRUE
NC_FW2_TPAN
NC_FW2_TPAP
NO_TEST=TRUE
NC_FW2_TPBIAS
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBP
MAKE_BASE=TRUE
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW0_TPBIAS
MAKE_BASE=TRUE
FWPHY_DS1
MAKE_BASE=TRUE
FWPHY_DS2
MAKE_BASE=TRUE
FWPHY_DS0
FW_PORT1_TPB_N
MAKE_BASE=TRUE
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW_PORT1_TPB_P
43 OF 109
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1
2
1
2
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
2 1
13
12
11
10
1
9
2
7
8
6
3
4
5
1
2
1
2
1
2
3
5
4
1
6
2
1
2
1
2
1
3
7
2
5
6
8
4
2
1
1
2
7 34
7
33
7 33 34 35
7 33 34 35
7
S
G
D
SYM_VER-1
SYM_VER-1
OUT
OUT
IN
IN
OUT
NC
IN
IN
OUT
OUT
IN
SYM_VER-1
IN
B_SD
A_SD
A_INP
A_INN A_OUTN
A_OUTP
VDD
GND THRM
I2C_ADDR
I2C_EN
B_INN
B_INP
B_OUTN
B_OUTP
EN
AUTOPW_EN
SCL_CTL
SDA_CTL
PAD
SYM_VER-1
IN
IN
D
S G
D
S G
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
(IPU)
NOTE: Internal pulls are ~150K
PS8515A:
(All 4 Cs)
(All 4 Cs)
(C4514,
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
(All 4 Cs)
- RDRV:8515 stuffs PS8515A & associated parts
18 B_EQ (IPD)
10 B_BST# (IPU)
20 A_BST# (IPU)
8 B_PRE (IPD)
9 A_PRE (IPD)
PIN NAME
PS8511A:
19 A_EQ (IPD)
PS8511A / PS8515A Straps
BOMOPTIONs:
J4500 connection separated to
support debug sense resistor.
ensure the drive is unpowered in S3/S5.
ODD Power Control
516S0616
SATA ODD Port
Alias together if no sense R.
(IPD)
(IPD)
516S0687
- RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)
C4519 & R4510)
SATA Redriver
(IPD)
x_SD pins are outputs (Signal Detect)
338S0778 (PS8515A)
Addr: 0x94(Wr)/0x95(Rd)
(ALL 4 RS & CS)
J5401 PINOUTS ARE DIFFERENT FOR K6, DO NOT SYNC THIS PAGE FROM T27 DIRECTLY
U4510 ADD NO STUFF IN PRODUCTION!!!!
Redriver Bypass Path
Indicates disc presence
- RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)
SATA HDD Port
CRITICAL
TPCP8102
23V1K-SM
Q4590
PLACE_NEAR=L4500.1:2mm
402
CERM
10V
20%
2
1
0.1UF
C4501
10V
20%
2
1
C4502
0.1UF
CERM
402
PLACE_NEAR=J4501.9:3mm
CRITICAL
0603
FERR-70-OHM-4A
L4500
CRITICAL
FL4525
90-OHM-100MA
DLP11S
PLACE_NEAR=J4500.9:4MM
CRITICAL
PLACE_NEAR=J4500.5:4mm
DLP11S
90-OHM-100MA
FL4520
C4525
0.01UF 10% CERM 402 16V
10% 402 CERM 16V
C4526
0.01UF
402 CERM 16V 10% 0.01UF
C4520
C4521
402 16V CERM 10% 0.01UF
17 74
17 74
17 74
17 74
C4532
10%
16V
402
0.1UF
X7R-CERM
10
1/16W
MF-LF
402
R4532
5%
R4531
1/16W
MF-LF
5%
402
4.7
10%
50V
CERM
402
0.001UF
C4531
6 39
R4590
MF-LF
402
5%
1/16W
33K
CRITICAL
J4501
54722-0224
F-ST-SM
F-ST-SM
54722-0164
J4500
CRITICAL
17 74
17 74
17 74
17 74
18
FL4502
CRITICAL
DLP11S
90-OHM-100MA
CERM
10% 0.01UF
C4517
16V
402
RDRV:8511&RDRV:8515
402
16V
CERM
10%
C4518
0.01UF
RDRV:8511&RDRV:8515
16V
402 CERM 0.01UF 10%
RDRV:8511&RDRV:8515
C4513
RDRV:8511&RDRV:8515
0.01UF CERM
16V
402
10%
C4512
402 0
1/16W
RDRV:NO
MF-LF
5%
R4580
0
R4581
MF-LF 402
5%
RDRV:NO
1/16W
1/16W
402 MF-LF
RDRV:NO
34
1%
R4585
1/16W
402 MF-LF
RDRV:NO
1%
R4586
34
C4519
402
CERM
16V
10%
0.01UF
PLACE_NEAR=U4510.16:3mm
RDRV:8511&RDRV:8515
CERM-X5R
C4514
1UF
402
6.3V
10%
RDRV:8511&RDRV:8515
RDRV:8511&RDRV:8515
1
2
MF-LF
1/16W
5%
402
10K
R4510
16
PS8515A-A2
CRITICAL
TQFN
U4510
RDRV:IN_DEVEL
16V
402 CERM
10% 0.01UF
C4515
RDRV:8511&RDRV:8515
402 CERM
10% 0.01UF
C4516
RDRV:8511&RDRV:8515
16V
402
10%
RDRV:8511&RDRV:8515
16V
CERM 0.01UF
C4510
402
16V 10% 0.01UF
RDRV:8511&RDRV:8515
C4511
CERM
RDRV:NO
C4580
402
16V
CERM
10% 0.01UF
RDRV:NO
402
16V
CERM
10% 0.01UF
C4585
RDRV:NO
16V
402 CERM
10% 0.01UF
C4581
RDRV:NO
16V
402 CERM
10% 0.01UF
C4586
90-OHM-100MA
DLP11S
CRITICAL
FL4501
10K
402
5%
1/16W
MF-LF
NO STUFF
R4517
2
1
10K
MF-LF
1/16W
5%
402
RDRV:8515
R4515
2
1
10K
MF-LF
1/16W
5%
402
NO STUFF
R4511
2
1
10K
402
5%
1/16W
MF-LF
NO STUFF
R4518
2
1
10K
MF-LF
1/16W
5%
402
NO STUFF
R4516
2
1
10K
402
5%
1/16W
MF-LF
RDRV:8515
R4512
2
1 5%
1/16W
MF-LF
10K
402
NO STUFF
R4520
MF-LF
1/16W
5%
10K
402
NO STUFF
R4519
0
1/16W
MF-LF
5%
402
RDRV:8515
R4514 402
5%
MF-LF
1/16W
0
RDRV:8515
R4513
42
42
402 47PF 50V
CERM
5%
C4587
C4588
50V 5%
CERM 47PF 402
SOT563
SSM6N15FEAPE
Q4596
402
100K
5%
R4597
MF-LF
1/16W
SOT563
Q4596
SSM6N15FEAPE
402
1/16W
5%
MF-LF
100K
R4596
1/16W
402
MF-LF
100K
R4595
5%
10V
10%
402
0.068UF
C4595
CERM
16V
10%
CERM
402
C4596
0.01UF
SATA Connectors
SYNC_MASTER=T27_MLB
338S0769 1 U4510 CRITICAL SATA 3GB/S REDRIVER, LOW POWER RDRV:8511
SATA_HDD_D2R_C_N
SATA_HDD_D2R_NORDRV_N
SATA_HDD_D2R_NORDRV_P
SATA_HDD_R2D_NORDRV_P
SATARDRVR_A_B_SD
SATA_HDD_D2R_RDRV_OUT_P SATA_HDD_D2R_UF_P
SATARDRVR_A_A_SD
SATA_HDD_D2R_RDRV_IN_P
SATARDRVR_A_I2C_EN
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_RDRV_OUT_P
=PP5V_SW_ODD
=PP5V_S3_IR
PP5V_S3_IR_R
VOLTAGE=5V
PP5V_S0_HDD_FLT
VOLTAGE=5V
SYS_LED_ANODE SYS_LED_ANODE_R
IR_RX_OUT
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATARDRVR_A_I2C_SCL
SATARDRVR_A_I2C_ADDR
SATA_HDD_R2D_UF_N
SATA_HDD_R2D_N
SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_D2R_RDRV_IN_N
SATARDRVR_A_EN
ODD_PWR_SS
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
=PP3V3_S0_ODD
SATA_ODD_D2R_UF_P
SATA_ODD_R2D_N
SATA_ODD_R2D_P
ODD_PWR_EN_L
ODD_PWR_EN_LS5V_L
ODD_PWR_EN
=PP5V_S0_ODD
=PP5V_SW_ODD_FET
=PP3V3_S0_ODD
SMC_ODD_DETECT
SATA_HDD_R2D_P
SATARDRVR_A_I2C_ADDR
SATARDRVR_A_I2C_EN
SATARDRVR_A_A_SD
SATARDRVR_A_B_SD
SATARDRVR_A_I2C_SCL
=PP1V5_S0_SATARDRVR
SATARDRVR_A_I2C_SDA =I2C_HDD_A_SDA
SATA_HDD_D2R_RDRV_OUT_N
SATARDRVR_A_AUTOPWR_EN
=PP5V_S0_HDD
SATA_ODD_D2R_UF_N
=I2C_HDD_A_SCL
SATA_HDD_D2R_C_P
SATA_HDD_R2D_RDRV_IN_P
SATARDRVR_A_I2C_SDA
=PP1V5_S0_SATARDRVR
SATA_HDD_R2D_RDRV_IN_N
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_NORDRV_N
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
45 OF 109
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051-8563
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7
8
5
6
4
3
1
2
2 1
4 3
1 2
4 3
1 2
1 2
1 2
1 2
1 2
2
1
1 2
1 2
2
1
1
2
1
3
7
5
9
11
13
15
19
17
21
2
4
6
8
14
10
12
18
16
20
22
15
13
11
9
7
5
3
1
16
14
12
10
8
6
4
2
4 3
1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
2
1
9
20
1
2 14
15
61
6
1
3 3
2
1
8
10
12
11
4
5
7
17
19
18
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
4 3
1 2
1
2
1
2
1 2
1 2
1 2
1 2
3
4 5
1
2
6
1
2
1
2
1 2
2
1
1 2
6 74
79
79
79
36
79 79
36
79
36
79
79
8
7 38
6
6
40
6 38
36
36
79
6 74
79
79
74
74
79
79
7 36
6 79
6 74
6 74
7
8
7 36
6 74
36
36
36
36
36
7 36
36
79
7
6 79
6 74
79
36
7 36
79
79
79
OUT
BI
BI
SYM_VER-1
IN
OUT
IN
SYM_VER-1
BI
BI
OUT
OUT2
TPAD GND
OUT1
OC1*
EN2
EN1
OC2*
IN
VCC
GND
SEL OE*
D+
D-
Y+
Y-
M+
M-
I
O
I
O
N
C
GND
VBUS
N
C
I
O
I
O
N
C
GND
VBUS
N
C
IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
514-0638
Left USB Port B
Left USB Port A
Port Power Switch
USB/SMC Debug Mux
SEL=0 Choose SMC
SEL=1 Choose USB
(USB_EXTA_MUXED_N)
(USB_EXTA_MUXED_P)
D4600.5
D4600.4
514-0638
D4610.4
D4610.5
PLACE_NEAR=J4600.1:3 mm
0603
FERR-220-OHM-2.5A
CRITICAL
L4605
CRITICAL
CASE-B2-SM
POLY-TANT
6.3V
20%
100UF
C4696
10UF
603
X5R
6.3V
20%
C4695
10V
20%
402
CERM
0.1UF
C4691
17
17 75
17 75
SMC_DEBUG:YES
10V
20%
402
CERM
0.1UF
C4650
1/16W
5%
402
MF-LF
10K
R4650
PLACE_NEAR=D4600.2:2 mm
CRITICAL
90-OHM-100MA
DLP11S
L4600
39 40 41
39 40 41
39
SMC_DEBUG:NO
0
MF-LF
402
5%
1/16W
R4651
SMC_DEBUG:NO
0
MF-LF
402
5%
1/16W
R4652
16V
20%
402
CERM
0.01uF
C4605
16V
20%
402
CERM
0.01uF
C4615
FERR-220-OHM-2.5A
0603
CRITICAL
L4615
DLP11S
90-OHM-100MA
CRITICAL
L4610
10UF
603
X5R
6.3V
20%
C4617
100UF
20%
6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
C4616
17 75
17 75
17
6.3V
20%
603
X5R
10UF
C4690
CRITICAL
F-RT-TH-M97-4
USB
J4600
CRITICAL
F-RT-TH-M97-4
USB
J4610
MSOP
TPS2064DGN
CRITICAL
Q4690
SMC_DEBUG:YES
SIGNAL_MODEL=USB_MUX
CRITICAL
PI3USB102ZLE
TQFN
U4650
CRITICAL
SLP1210N6
RCLAMP0502N
D4610
1
6
PLACE_NEAR=J4600.2:2 mm SLP1210N6
RCLAMP0502N
CRITICAL
D4600
1
6
65
External USB Connectors
SYNC_MASTER=T27_MLB
VOLTAGE=5V
PP5V_S3_RTUSB_B_ILIM
VOLTAGE=5V
PP5V_S3_RTUSB_B_F
PP5V_S3_RTUSB_A_ILIM
VOLTAGE=5V
VOLTAGE=5V
PP5V_S3_RTUSB_A_F
=USB_PWR_EN
USB_LT1_N
USB_LT1_P
=PP5V_S3_RTUSB
=PP3V42_G3H_SMCUSBMUX
USB_DEBUGPRT_EN_L
USB_EXTA_OC_L
USB_EXTB_OC_L
SMC_RX_L
SMC_TX_L
USB_LT2_N
USB_LT2_P
USB_EXTB_N
USB_EXTB_P
USB_EXTA_MUXED_N
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
46 OF 109
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2 1
1
2 2
1
2
1
2
1
1
2
4 3
1 2
1 2
1 2
2
1
2
1
2 1
4 3
1 2
2
1 1
2
2
1
1
2
4
3
5
6
7
8
1
2
4
3
5
6
7
8
6
9 1
7
8
4
3
5
2
9
3
10 8
7
6
1
2
5
4
2 5 3 4
2 5 3 4
79
79
7
7
79
79
75 79
75 79
BI
BI
VCC
P1.0/D+
P1.1/D-
P1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
P0.0
P0.1
INT0/P0.2
INT1/P0.3
TIO1/P0.6
NC
TIO0/P0.5
INT2/P0.4
VSS PAD
THRML
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
I
O
I
O
N
C
GND
VBUS
N
C
NC
NC
NC
NC
NC
NC
IN
IN
3 6
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DRAWING NUMBER SIZE
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
IR Support
860-1287
860-1287
516S0824
K6 NOTES : D4890 CONNECTION IS DIFFERENT,CANNOT DIRECTLY SYNC FROM T27
T57 Connector
17 75
17 75
C4803
10V
10%
402-1
X5R
1UF
U4800
CY7C63803-LQXC
QFN
CRITICAL
OMIT
C4801
16V
402
0.1UF
10%
X7R-CERM
C4804
0.001UF
CERM
402
10%
50V
R4800
402
5%
1/16W
100
MF-LF
6 36
6 75
6 75
T57
16V
C4895
0.01uF
402
CERM
20%
6
1
D4890
RCLAMP0502N
SLP1210N6
T57
CRITICAL
J4890
AXK720427G
T57
F-ST-SM
CRITICAL
C4896
20%
16V
CERM
402
0.01uF
T57
BS4891
STDOFF-3.6OD3.4H-SM
T57
T57
STDOFF-3.6OD3.4H-SM
BS4890
Internal USB Support
NC_T57_PWR_EN
=PP5V_S3_T57
NC_T57_RESET
USB_T57_N
USB_T57_P
=PP5V_S3_IR
IR_RX_OUT_RC IR_RX_OUT
IR_VREF_FILTER
USB_IR_P
USB_IR_N
=PP3V3_S3_T57
38 OF 80
051-8563
A.13.0
48 OF 109
2
1
1
4
12
13
15
16
17
18
19
7
6
5
4
1
8
9
10
20
21
22
23
24
2
3
1
1
2
5
2
1
2
1
1 2
2
1
2 5 3 4
21
22
18
20
16
12
14
10
8
6
2
4
17
19
9
7
1
3
5
11
13
15 2
1
1
1
7
7 36
7
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
BI
IN
IN
OUT
BI
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
OUT
IN
IN
BI
BI
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
OUT
P13
P14
P15
P16 P66
P10
P11
P12
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P60
P61
P62
P63
P64
P65
P67
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P84
P85
P86
P90
P91
P92
P93
P94
P95
P96
P97
P35
P83
P82
(1 OF 3)
PA5
PA4
PA0
PA1
PA2
PA3
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0
PE1
PE2
PE3
PE4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
(2 OF 3)
RES*
NMI
VSS
VCL VCC
NC
MD2
MD1
ETRST
AVSS
AVREF AVCC
EXTAL
XTAL
(3 OF 3)
IN
NC
IN
BI
BI
BI
BI
IN
IN
IN
OUT
BI
IN
IN
IN
BI
BI
IN
3 6
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PAGE TITLE
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A
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2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
NOTE: P94 and P95 are shorted in some platforms.
If SMS interrupt is not used, pull up to SMC rail.
(OC)
(OC)
Otherwise, TP/NC okay.
SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.
H8S2117-R:
(SMC_PECI_VSTP)
(SMC_PECI_VREF)
(SMC_PECI)
(See below)
(EXCARD_OC_L)
(EXCARD_CP)
(EXCARD_PWR_EN)
(OC)
those designated as inputs require pull-ups.
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(DEBUG_SW_1)
(DEBUG_SW_2)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
pins designed as outputs can be left floating,
NOTE: Unused pins have "SMC_Pxx" names. Unused
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
22UF
805
CERM
20%
6.3V
C4902
18 41
40 41 58
40 47
C4907
6.3V
0.47UF
402
10%
CERM-X5R
BYPASS=U4900.E1:D2:5 mm
10V
402
0.1UF
CERM
20%
C4903
BYPASS=U4900.M12:L9:5 mm
0.1UF
10V
402
CERM
20%
C4920
1/16W
402
MF-LF
5%
4.7
R4999
402
0.1UF
10V
CERM
20%
C4904
SM
XW4900
18
61
402
10V
0.1UF
CERM
20%
C4905
18
65
24 65
40
C4906
CERM
10V
402
0.1UF
20%
44
43
40
40
44
43
44
22
40
8 40 57
37 39 40 41
37 39 40 41
6 65
42
10K
402
1/16W
5%
MF-LF
R4909
41
41
R4901
MF-LF
10K
5%
1/16W
402
10K
MF-LF
402
5%
1/16W
R4902
402
1/16W
5%
0
R4903
MF-LF
NO STUFF
402
1/16W
5%
MF-LF
10K
R4998
37
57
18
6 36
18
46
40
40
40
40
40
40
46
49
49
40
49
40
40
40
40 41
40
40 41
40 41
40 41
40 47 57
42
42
42
42
42
42
40
40
40
37 39 40 41
37 39 40 41
40
40
18 41
18 25 26
24
41
18
18 41
40
49
18 40 65
6 40 57
40
40
H8S2117
LGA-HF
OMIT
U4900
OMIT
LGA-HF
H8S2117
U4900
OMIT
LGA-HF
H8S2117
U4900
40
6 18 40 65
18 41 75
18 41 75
18 41 75
18 41 75
18 41 75
24
24 75
48
42
6 18 65 69
18
24 75
42
42
40
SMC
=PP3V3_S5_SMC
SMC_TRST_L
SMC_KBC_MDE
SMC_MD1
PP3V3_S5_AVREF_SMC
SMC_LID
SMB_B_S0_DATA
SMC_RESET_L
SMC_EXTAL
SMC_XTAL
GND_SMC_AVSS
SMC_NMI
SMC_PA5
MEM_EVENT_L
SMC_PA0
SMC_PA1
PM_SYSRST_L
USB_DEBUGPRT_EN_L
SYS_ONEWIRE
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_GFX_OVERTEMP_L
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMS_X_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_ADC15
SMC_TCK
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMC_PROCHOT
RSMRST_PWRGD
SMC_PROCHOT_3_3_L
SMC_RSTGATE_L
ALL_SYS_PWRGD
SMC_BMON_MUX_SEL
LPC_AD<0>
LPC_FRAME_L
LPC_CLK33M_SMC
SMB_MGMT_DATA
SMS_ONOFF_L
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_RX_L
SMB_0_S0_CLK
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_BIL_BUTTON_L
SMC_GPU_ISENSE
SMC_RX_L
SMB_MGMT_CLK
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
SMC_TMS
PM_BATLOW_L
SMC_THRMTRIP
SMC_P10
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
SMC_TX_L
SMC_PB6
SMB_B_S0_CLK
SMC_TDI
SMC_TDO
SMC_SYS_LED
SMC_PB4
SMC_PB3
SMC_PH3
PM_SLP_S4_L
SMC_MCP_SAFE_MODE
PM_CLKRUN_L
SMC_BATT_ISENSE
SMC_PBUS_VSENSE
SMC_DCIN_ISENSE
SMC_GPU_VSENSE
SMC_NB_MISC_ISENSE
SMC_WAKE_SCI_L
LPC_PWRDWN_L
PM_SLP_S3_L
SMC_BS_ALRT_L
SMC_BC_ACOK
SMC_ONOFF_L
SMC_CASE_OPEN
SMC_G3H_POWERON_L
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_ADC14
SMC_NB_DDR_ISENSE
SMS_Z_AXIS
SMS_Y_AXIS
SMC_P24
SMC_TX_L
LPC_SERIRQ
LPC_AD<1>
SMC_P20
LPC_AD<3>
LPC_AD<2>
SMC_P41
SMC_LRESET_L
SMC_VCL
SMC_CPU_ISENSE
SMC_CPU_VSENSE
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
49 OF 109
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051-8563
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2
1
2
1
2
1
2
1
1 2
2
1
1 2
2
1
2
1
1
2
1
2
1
2
1
2
1
2
B13
D11
C13
C12 J11
B12
A13
A12
D10
D13
E11
D12
F11
E13
E12
F13
E10
A9
D9
C8
B7
A8
D7
D6
D4
A5
B4
A1
C2
B2
C1
C3
G2
F3
E4
L13
K12
K11
J12
K13
J10
H12
N10
M11
L10
N11
N12
M13
N13
L12
A7
B6
A6
B5
C6
J4
G3
H2
G1
H4
G4
F4
F1
D8
D5
C7
L1
N2
N3
N1
M3
M2
K3
L2
B8
C9
B9
A10
C10
B10
C11
A11
G11
G13
F12
H13
G10
G12
H11
J13
M10
N9
K10
L8
M9
N8
K9
L7
K1
J3
K2
J1
K4
K5
N5
M6
L5
M5
N4
L4
M4
M8
N7
K8
K7
K6
N6
M7
L6
E2
F2
J2
A4
B3
C4
D3
F
1
0
E3
C
5
B
1
1
L
3
D
2
E
1
H
1
0
M
1
B
1
E5
H1
D1
H3
L9
L
1
1
M
1
2
A2
A3
7 40
40
40
40
22 40 43 44
40
40
40
44
22
40
40
40
40
40
40
40
D
S G
IN
OUT
BI
IN
D
S G
IN
IN
IN
IN
IN OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN OUT
OUT
OUT
OUT
OUT
OUT
IN
E
Q2
C
B D
Q1
G S
OUT
G
D
S
OUT
IN
REFOUT
MR1*
THRM
GND
RESET*
DELAY
MR2*
VIN V+
SN0903048
PAD
IN
IN
OUT
OUT
OUT
3 6
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PAGE TITLE
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A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
(IPU)
Used on mobiles to support SMC reset via keyboard.
MR1* and MR2* must both be low to cause manual reset.
NOTE: Internal pull-ups are to VIN, not V+.
SMC Pull-ups
SMC Pull-downs
PLACEMENT_NOTEs:
SMC Reset "Button", Supervisor & AVREF Supply
Debug Power "Buttons"
Desktops: 5V
Mobiles: 3.42V
(IPU)
TO SMC
SMC FSB to 3.3V Level Shifting
System (Sleep) LED Circuit
TO CPU
SMC Aliases
Unused Pins
SMC Crystal Circuit
Q5059
SSM6N15FEAPE
SOT563
R5070
1/16W 5% 402
10K
MF-LF
R5071
1/16W 5% 402 MF-LF
100K
R5073 10K
MF-LF 402 5% 1/16W
R5074 100K
MF-LF 402 5% 1/16W
R5076
MF-LF 402
100K
1/16W 5%
R5077 10K
MF-LF 402 5% 1/16W
R5078 10K
MF-LF 402 5% 1/16W
R5079
MF-LF
10K
402 5% 1/16W
R5080 10K
MF-LF 402 5% 1/16W
R5085 10K
402 5% MF-LF 1/16W
R5086 10K
MF-LF 402 5% 1/16W
R5088 10K
MF-LF 402 5% 1/16W
R5090 100K
MF-LF 402 1/16W 5%
39
9 13 72
R5015
SILK_PART=PWR_BTN
0
MF-LF
603
5%
1/10W
Place R5015 on BOTTOM side
OMIT
R5062
1/16W
5%
402
MF-LF
3.3K
9 13 61 72
39
Q5059
SSM6N15FEAPE
SOT563
R5091 100K
MF-LF 402 5% 1/16W
R5092 100K
MF-LF 402 5% 1/16W
R5089
1/16W 5% 402 MF-LF
10K
R5081 10K
MF-LF 402 5% 1/16W
C5011
CERM
15pF
402
5%
50V
C5010
50V
5%
402
CERM
15pF
R5087 470K
MF-LF 402 5% 1/16W
R5093
MF-LF 1/16W 402
10K
5%
R5014
5%
Place R5014 on TOP side
SILK_PART=PWR_BTN
0
MF-LF
603
1/10W
OMIT
39
39
39
39
39 18
39
39
39
39
39
39
39
39
39
39
R5096
5%
MF-LF
402
0
1/16W
39 18
39
39
39
R5095
MF-LF 402 5% 1/16W
10K
R5094 10K
MF-LF 402 5% 1/16W
39
39
39
R5032
402
1/16W
1%
MF-LF
1.47K
R5031
402
523
MF-LF
1%
1/16W
R5030
1/16W
20
1%
MF-LF
402
Q5030
DMB54D0UV
SOT-563
36
Q5060
DMB53D0UV
SOT-563
R5061
402
100K
5%
1/16W
MF-LF
Q5060
DMB53D0UV
SOT-563
R5060
MF-LF
10K
402
5%
1/16W
39
18
U5010
DFN
VREF-3.3V-VDET-3.0V
47
39 40 47
R5000
5%
402
MF-LF
1/16W
1K
C5026
16V
CERM
0.01UF
402
10%
C5025
6.3V
20%
603
X5R
10uF
C5001
CERM
402
10%
16V
0.01UF
R5001
SILK_PART=SMC_RST
OMIT
0
MF-LF
603
5%
1/10W
PLACEMENT_NOTE=Place R5001 on BOTTOM side
39 41 58
C5020
CERM-X5R
0.47UF
402
10%
6.3V
39 40
1 2 R5098
402
100K
MF-LF 5% 1/16W
39 40 47
SMC Support
MCP_WAKE_REQ_L
TP_SMC_FAN_1_TACH
MAKE_BASE=TRUE
SMC_FAN_2_TACH
SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC_G3H_POWERON_L
MAKE_BASE=TRUE
SMS_INT_L
MAKE_BASE=TRUE
TP_SMC_FAN_1_CTL
TP_SMC_GPU_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_PH3
TP_SMC_PB3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P41
TP_SMC_P24
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P20
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE
SMC_MCP_VSENSE
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
VOLTAGE=3.3V
PP3V3_S5_AVREF_SMC
VOLTAGE=0V
GND_SMC_AVSS
NO_TEST=TRUE
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
SMC_NB_CORE_ISENSE
SMC_ADC14
SMC_THRMTRIP
PM_THRMTRIP_L
CPU_PROCHOT_L
SYS_LED_ILIM
SYS_LED_ANODE
SYS_LED_L
=PP5V_S3_SYSLED
SMC_PROCHOT
CPU_PROCHOT_L_R
CPU_PROCHOT_BUF
=PP3V3_S0_SMC
SMC_PROCHOT_3_3_L
SMC_SYS_LED
SMC_ONOFF_L
SMC_EXTAL
SMC_XTAL
SMC_FAN_3_TACH
SMC_FAN_2_CTL
=PPVIN_S5_SMCVREF
SMC_ONOFF_L
SMC_MANUAL_RST_L
SMC_RESET_L SMC_TPAD_RST_L
SMC_FAN_1_CTL
SMC_ADC15
SMC_NB_DDR_ISENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
=PP3V3_S0_SMC
SMC_BS_ALRT_L
SMC_ADAPTER_EN
PM_SLP_S4_L
SMC_CASE_OPEN
SMC_G3H_POWERON_L
SMC_PA5
SMC_RSTGATE_L
SMC_P20
SMC_P24
SMC_P41
SMC_PH3
SMC_PB3
SMC_FAN_1_TACH
SMC_GFX_THROTTLE_L
=SMC_SMS_INT
MCP_SPKR SMC_MCP_SAFE_MODE
SYS_LED_L_VDIV
SMC_TDO
SMC_TMS
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMS_INT_L
SMC_BC_ACOK
SMC_GFX_OVERTEMP_L
SMC_ONOFF_L
SMC_LID
SMC_RX_L
SMC_TX_L
=PP3V3_S5_SMC
SMC_PA0
SMC_PA1
SMC_PB4
SMC_PB6
=PP3V3_S5_SMC
SMC_ANALOG_ID
TP_SMC_GPU_VSENSE
MAKE_BASE=TRUE
TP_SMC_GPU_1V8_ISENSE
MAKE_BASE=TRUE
SMC_XTAL_R
CRITICAL
Y5010
20.00MHZ
5X3.2-SM
5%
402
MF-LF
0
1/16W
R5010
50 OF 109
A.13.0
051-8563
40 OF 80
3
4 5
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1 2
6
1
2
1 2
1 2
1 2
1 2
1 2
2
1
1 2
1 2
1 2
1 2
1
2
1 2
1 2
1 2
1
2
1
2
1
2
1 2 3
5 4 6
4
5
3
1
2
6
2
1
1
2
8
6
9 2
5
4
7
3 11
2
2
1
2
1
2
1
1
2
2
1
40
44
44
44
43
39
22 39 43 44
7
7 40
39
39
7
7 40
39
18 39 65
6 18 39 65
39
39 40
39
39
39 41
39 41
39 41
39 41
6 39 57
40
8 39 57
39
39 40 47
39 47 57
37 39 41
37 39 41
7 39 40
39
39
39
39
7 39 40
OUT IN
E0/NC0
SCL
SDA E2
E1
WC*
VCC
VSS
IN
BI
NC
BI
OUT
OUT
OUT
IN
IN
IN
OUT IN
OUT IN
IN
BI
BI
BI
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN OUT
3 6
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D
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
SPI Bus Series Termination
516S0573
LPC+SPI Connector
EFI Debug ROM
Write: 0xAC/0xAE
Read: 0xAD/0xAF
R5126
LPCPLUS
5%
1/16W
MF-LF
402
47
50 75
R5122
402
1/16W
5%
MF-LF
47
R5112
402
MF-LF
5%
1/16W
15
18 75
R5127
402
MF-LF
1/16W
5%
47
LPCPLUS
R5128
LPCPLUS
5%
1/16W
MF-LF
402
0
U5101
EFI_DEBUG
SO8N
CRITICAL
M24M01-R
R5101
0
402
1/16W
5%
MF-LF
EFI_DEBUG
MF-LF
5%
1/16W
402
0
R5104
NO STUFF
R5102
0
402
1/16W
5%
MF-LF
NO STUFF
R5103
1/16W
5%
MF-LF
402
0
EFI_DEBUG
C5101
20%
10V
CERM
402
0.1UF
EFI_DEBUG
42
42
J5100
M-ST-SM
55909-0374
CRITICAL
NO STUFF
18 39 75
39 40
39 40
39
24
37 39 40
39
50 75
R5110
15
5%
1/16W
MF-LF
402
18 75
50 75
15
402
MF-LF
5%
1/16W
R5111
18 75
24 75
18 39 75
18 39 75
18 39 75
6 18 50
18 39
18 39
39 40
39 40 58
39
39 40
37 39 40
18
18 39
18 39 75
50 75
R5123
1/16W
MF-LF
402
15
5%
6 18 75
R5120
MF-LF
5%
1/16W
402
47
R5125
LPCPLUS
5%
1/16W
MF-LF
402
47
R5121
402
5%
MF-LF
47
1/16W
LPC+SPI Debug Connector
SPI_MLB_MISO
=PP3V3_S0_DEBUGROM
DEBUGROM_E1
DEBUGROM_E2
SPI_MOSI
SPI_MISO
SPI_CLK_R
=I2C_DEBUGROM_SDA
=I2C_DEBUGROM_SCL
SPI_MOSI_R
SPI_MLB_CLK SPI_CLK
SPI_MLB_CS_L SPI_CS0_L
SPI_ALT_MOSI
SPI_ALT_CS_L
SMC_RX_L
SMC_NMI
SMC_RESET_L
SMC_TCK
LPC_PWRDWN_L
SPI_ALT_MOSI
LPC_FRAME_L
SMC_TMS
PM_CLKRUN_L
SMC_TDO
LPCPLUS_RESET_L
SMC_TRST_L
SMC_MD1
LPC_AD<0>
=PP5V_S0_LPCPLUS
SPI_ALT_MISO
LPC_AD<1>
=PP3V3_S5_LPCPLUS
SMC_TDI
LPC_AD<3>
LPC_AD<2>
LPC_CLK33M_LPCPLUS
SPIROM_USE_MLB
SPI_ALT_CS_L
LPCPLUS_GPIO
LPC_SERIRQ
SPI_ALT_CLK
SPI_ALT_CLK
SPI_CS0_R_L
SMC_TX_L
SPI_ALT_MISO
SPI_MLB_MOSI
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1
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1 2 1 2
1
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1
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8
4
1
6
5 3
2
7
1
2
1
2
1
2
1
2
2
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
3
1
5
9
7
15
11
13
17
19
21
23
25
27
29
31 32
33 34
1 2
1 2
1 2
1 2
1
2
1 2
7
6 75
6 75
41 75
41 75
41 75
7
41 75
7
41 75
41 75
41 75
41 75
NBC
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
J3100
(Write: 0x12 Read: 0x13)
(MASTER)
U4900
SMC
NOTE:
SMC "0" SMBus Connections
Mikey
MCP Temp MCP89
ALS
(MASTER)
(Write: 0xAC/0xAE
U3310
SMC
Battery Temp - (Write: 0x90 Read: 0x91)
(MASTER)
ISL6259 - U7000
Battery Charger
U3300
J5800
J3401
SMC "Battery A" SMBus Connections
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
(MASTER)
U4900
SMC
(MASTER)
U4900 U1400 J2900
SO-DIMM "A" SMC
U6880
(Write: 0xA0 Read: 0xA1)
Vref DACs
U9701
LP8545 (Bklt)
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC "A" SMBus Connections
EFI Debug Serial
U5101
Read: 0xAD/0xAF)
(Write: 0x?? Read: 0x??)
U1400
MCP89 SMBus 1 is slave port to
access internal thermal diodes.
U4510
HDD Margin Ctrl.
Margin Control
(Write: 0x98 Read: 0x99) (MASTER)
U4900
(Write: 0xA2 Read: 0xA3)
EMC1412-A: U5535
(WRITE: 0X98 READ: 0X99)
EMC1413: U5515
MCP89 SMBus "0" Connections
SO-DIMM "B"
U4900
Battery LED Driver - (Write: 0x36 Read: 0x37)
SMC
R5290/91 (VREF DAC, MARGIN CONTROL)WAS 4.7K ON K24, VALUE NEEDS TO BE CHECKED
R5280/81 WAS 2K ON K24, VALUE NEEDS TO BE CHECKED
MCP89
MCP89 SMBus "1" Connections
CPU Temp
SMC "B" SMBus Connections
Trackpad
The bus formerly known as "Battery B"
SMC "Management" SMBus Connections
Battery & BIL
J6950 & J6955
(See Table)
R5280
1/16W
402
2.61K
1%
MF-LF
R5281
MF-LF
1/16W
402
2.61K
1%
R5261
MF-LF
1/16W
5%
402
4.7K
R5260
402
1/16W
MF-LF
5%
4.7K
R5271
1K
1/16W
MF-LF
5%
402
R5270
1K
1/16W
5%
402
MF-LF
R5251
402
5%
1/16W
MF-LF
4.7K
R5250
MF-LF
402
5%
1/16W
4.7K
NO STUFF
MF-LF
1/16W
2.0K
5%
402
R5231
NO STUFF
2.0K
402
1/16W
MF-LF
5%
R5230
402
1K
5%
MF-LF
R5200
1/16W
R5201
402
5%
1/16W
1K
MF-LF
0
MF-LF
1/16W
5%
402
R5236
0
402
1/16W
MF-LF
5%
R5235
R5291
4.7K
5%
1/16W
402
MF-LF
R5290
1/16W
4.7K
MF-LF
5%
402
K6 SMBUS CONNECTIONS
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
=PP3V3_S5_SMBUS_SMC_MGMT
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
=I2C_MCPTHMSNS_SDA
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE MAKE_BASE=TRUE
SMBUS_MCP_1_CLK
=I2C_VREFDACS_SDA
SMB_B_S0_DATA
SMB_B_S0_CLK
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_0_S0
=I2C_PCA9557D_SDA
=I2C_HDD_A_SCL
=I2C_HDD_A_SDA
=I2C_VREFDACS_SCL
SMB_A_S3_DATA
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
=I2C_MIKEY_SDA
I2C_ALS_SDA
=I2C_BKL_1_SDA
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=I2C_BKL_1_SCL
=I2C_MCPTHMSNS_SCL SMB_0_S0_CLK
SMB_0_S0_DATA SMB_BSA_DATA
SMB_BSA_CLK
=PP3V42_G3H_SMBUS_SMC_BSA
=I2C_TPAD_SDA
I2C_ALS_SCL
SMB_A_S3_CLK
=I2C_PCA9557D_SCL
=I2C_DEBUGROM_SCL
=I2C_DEBUGROM_SDA
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
=I2C_TPAD_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
=I2C_MIKEY_SCL
SMB_MGMT_CLK
SMB_MGMT_DATA
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL
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2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
78
78
57
57
7
78
45
6 78
78
78 18 75
28
39
39
45
45
7
7
28
36
36
7
28
39
26
26
56
29
70
7
25
25
70
45 39
39 39
39
7
48
29
39
28
41
41
58
58
48
7
56
39
39
12 18 75
18 75
78
12 18 75
6 78
OUT
IN
OUT
S
S
D
N-CHANNEL
G
D
G
P-CHANNEL
OUT
3 6
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D
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
Enables PBUS VSense
Place RC close to SMC
divider when high.
PBUS Voltage Sense Enable & Filter
RTHEVENIN = 4573 Ohms
CPU Voltage Sense / Filter
MCP Voltage Sense / Filter
40
20%
6.3V
X5R
402
0.22UF
C5359
4.53K
1/16W
MF-LF
1%
402
R5359
65
402
MF-LF
1/16W
1%
100K
R5316
402
MF-LF
1/16W
1%
100K
R5315
39
20%
6.3V
X5R
402
0.22UF
C5385
402
MF-LF
1/16W
1%
27.4K
R5385
402
MF-LF
1/16W
1%
5.49K
R5386
SOT-963
NTUD3169CZ
Q5315
XW5359
SM
PLACE_NEAR=R7525.2:5 MM
39
4.53K
1/16W
MF-LF
1%
402
R5309
20%
6.3V
X5R
402
0.22UF
C5309
SM
XW5309
PLACE_NEAR=L7400.2:5 MM
Voltage Sensing
MCPVSENSE_IN
PBUS_G3H_VSENSE
PPVCORE_S0_MCP
PPVCORE_S0_CPU
CPUVSENSE_IN
GND_SMC_AVSS
SMC_CPU_VSENSE
GND_SMC_AVSS
SMC_PBUS_VSENSE
GND_SMC_AVSS
SMC_MCP_VSENSE
PPBUS_G3H
PBUSVSENS_EN_L_DIV
PBUSVSENS_EN_L
=PBUSVSENS_EN
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1
1 2
1
2
1
2 2
1
1
2
1
2
6
2
1
3
5
4
1 2
1 2
2
1
1 2
6 7
6 7
22 39 40 43 44
22 39 40 43 44
22 39 40 43 44
6 7
OUT
V+
REF IN+
IN- OUT
GND
OUT
OUT IN
V+
REF IN+
IN- OUT
GND
IN
OUT
IN OUT
VER 1
VCC
A
1
0
B1
GND
B0
SEL
IN
IN
IN
IN
OUT
IN
OUT IN-
IN+ REF
V+
GND
IN
IN
IN
+IN
-IN
V+
V-
3 6
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REVISION
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
For engineering, stuff BMON_ENG
Battery (BMON) Current Sense, MUX & Filter
PLACEMENT_NOTEs:
(For Rs and C)
PLACEMENT_NOTEs:
Charger/Load side
MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter
(Sense R "input")
Max Vdiff = 24.8mV
Sense R is R7525, 1mOhm
Gain: 100x
(Sense R "output")
Scale: 10A / V
Max VOut: 2.48V
R7593 at the same time!
NOTE: Do not stuff R5415 and
PLACEMENT_NOTEs:
(For R and C)
MCP VCore Current Sense Filter
CPU VCore Load Side Current Sense / Filter
(50V/V)
MCP MEM VDD Current Sense / Filter
PLACEMENT_NOTEs:
(For R and C)
(For R and C)
(For R and C)
Battery side
From charger
DC-IN (AMON) Current Sense Filter
PLACEMENT_NOTEs:
(For R and C)
NOTE: Monitoring current from
For production, stuff BMON_PROD
battery to PBUS (battery discharge)
PLACEMENT_NOTEs:
(100V/V)
(50V/V)
ISL6259 Gain: 36x
INA213 Gain: 50x
across R7008
40
C5472
Place close to SMC
0.22UF
X5R
402
20%
6.3V
C5417
0.1uF
CERM
20%
10V
402
INA213
SC70
U5402
40
Place close to SMC
C5436
0.22UF
X5R
402
20%
6.3V
39 58
4.53K
MF-LF
402
1%
1/16W
Place close to SMC
R5418
R5416
Place close to SMC
4.53K
MF-LF
402
1%
1/16W
C5418
BMON:ENG
0.1uF
CERM
402
20%
10V
U5403
BMON:ENG
PLACEMENT_NOTE=Place near sense resistor
INA213
SC70
58 1 2
R5431
BMON:PROD
402
0
MF-LF
5%
1/16W
PLACEMENT_NOTE=Place R5431 next to U5413
R5423
BMON:ENG
1/16W
5%
402
MF-LF
100K
C5459
BMON:ENG
10V
20%
402
CERM
0.1uF
1/16W
1%
MF-LF
Place close to SMC
R5401
45.3K
402
402
Place close to SMC
16V
CERM-X5R
0.022UF
10%
C5490
39
Place close to SMC
C5470
6.3V
20%
402
X5R
0.22UF
61
R5480
Place close to SMC
1/16W
1%
402
MF-LF
17.4K
R5471
Place close to SMC
6.19K
MF-LF
402
1%
1/16W
39
R5481
1/16W
1%
402
MF-LF
4.53K
Place close to SMC
C5487
0.22UF
X5R
402
20%
6.3V
Place close to SMC
NC7SB3157P6XG
U5413
BMON:ENG
SC70
39
58 78
R5412
1/16W
1%
402
MF-LF
118
Q5401
2SA2154MFV-YAE
SOD
20
20
MF-LF
1/16W
5%
402
0
R5410
X5R
402
16V
10%
C5434
0.1UF
NO STUFF
2
5%
MF-LF
0
1/16W
R5411
4021
C5400
0.1uF
10V
20%
402
CERM
R5417
1/16W
1%
402
MF-LF
4.53K
Place close to SMC
402
6.3V
20%
X5R
0.22UF
Place close to SMC
C5435
40
58 78
CRITICAL
R5492
0612-1
1 W 0.5%
MF
0.01
U5420
SC70
INA214
C5420
0.1uF
CERM
10V
20%
402 R5415
402
0
1/16W
MF-LF
5%
62
8
8
OPA330
U5400
SC70-5
Current Sensing
GND_SMC_AVSS
BMON_AMUX_OUT
=PP3V42_G3H_BMON_ISNS
ISNS_CPUVTT_P
=PPBUS_S5_CPUREGS_ISNS
=PPBUS_S5_CPUREGS_ISNS_R
ISNS_CPUVTT_N
CHGR_AMON SMC_DCIN_ISENSE
IMVP6_IMON
SMC_MCP_CORE_ISENSE
GND_SMC_AVSS
SMC_CPU_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
CHGR_CSO_R_N
CHGR_CSO_R_P BMON_INA_OUT
CPUVTT_IOUT
SMC_BMON_MUX_SEL
SMC_BATT_ISENSE
SMC_CPU_FSB_ISENSE
CHGR_BMON
=PP3V3_S0_CPUVTTISNS
GND_SMC_AVSS
GND_SMC_AVSS
SMC_MCP_DDR_ISENSE MCPDDR_SENSE_C
MCPCORES0_IMON =PP3V3_S0_MCPCOREISNS
MCPCORE_IOUT =MCPCOREISNS_N
=MCPCOREISNS_P
MCPDDR_SENSE_AMP
=PP3V3_S0_MCPDDRISNS
MCPDDRFET_KELVIN
MCPDDRFET_SENSE
MCPDDR_SENSE_E
MCPDDR_SENSE_B
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1
2
1
2
3
1 4
5 6
2
1
1 2
1 2
2
1
2
3
1 4
5 6
1
2
2
1
1 2
2
1
2
1
1
2
1 2
1 2
2
1
2
3
1
4
6
5
1
2
2
1
3
1
2
2
1
2
1
1 2
2
1
4
3
2
1
6 5
4 1
3
2
2
1
1 2
2
5
4
1
3
22 39 40 43 44
7
79
7
7
79
22 39 40 43 44
22 39 40 43 44
22 39 40 43 44
7
22 39 40 43 44
22 39 40 43 44
7
7
BI
BI
BI
BI
BI
BI
SMCLK
SMDATA
DP
DN
VDD
GND
ALERT*
THERM*/ADDR
THRM_PAD
DN2/DP3
DP2/DN3
VDD
SMDATA
SMCLK
GND
DN1
DP1 THERM*/ADDR
ALERT*
BI
BI
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
MCP Thermal Diode
CPU Thermal Diode
Fin-Stack Temperature
CPU T-Diode Thermal Sensor
Local sensor for MCP Proximity
MCP T-Diode Thermal Sensor
Local sensor for CPU Proximity
C5515
10V
20%
402
CERM
0.1uF
42
42
10V
20%
402
CERM
0.1uF
C5535
Q5501
PLACEMENT_NOTE=Place Q5501 near Fin Stack
CRITICAL
BC846BMXXH
SOT732-3
C5520
0.0022uF
CERM
402
10%
50V
R5515
1/16W
5%
402
MF-LF
47
47
MF-LF
402
5%
1/16W
R5535
C5522
0.0022uF
CERM
402
10%
50V
18 79
18 79
C5521
CERM
402
50V
0.0022uF
10%
9 79
9 79
MSOP
CRITICAL
PLACEMENT_NOTE=Place U5535 near MCP
U5535
EMC1412-A
U5515
DFN
CRITICAL
PLACEMENT_NOTE=Place U5515 near CPU
EMC1413
R5517
1/16W
5%
MF-LF
10K
402
1%
402
1/16W
MF-LF
10K
R5516
42
42
R5536
10K
MF-LF
1/16W
402
1%
R5537
402
10K
MF-LF
5%
1/16W
Thermal Sensors
VOLTAGE=3.3V
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
PP3V3_S0_MCPTHMSNS_R
CPUTHMSNS_ALERT_L
CPUTHMSNS_D2_N
CPUTHMSNS_D2_P
CPU_THERMD_P
CPU_THERMD_N
MCPTHMSNS_THERM_L
MCPTHMSNS_ALERT_L
MCP_THMDIODE_P
MCP_THMDIODE_N
=I2C_MCPTHMSNS_SDA
=I2C_MCPTHMSNS_SCL
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
CPUTHMSNS_THERM_L
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_MCPTHMSNS
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1
2
3
2
1
1 2
1 2
2
1
2
1
8
7
2
3
1
5
6
4
11
5
4
1
9
10
6
3
2 7
8
1
2
1
2
1
2
1
2
79
7
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NC
NC
518S0521
GND
MOTOR CONTROL
TACH
5V DC
R5665
402
MF-LF
5%
1/16W
47K
R5660
47K
1/16W
MF-LF
402
5%
R5661
100K
402
MF-LF
1/16W
5% Q5660
SOD-VESM-HF
SSM3K15FV
J5601
M-RT-SM
78171-0004
CRITICAL
Fan
FAN_RT_PWM
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
SMC_FAN_0_CTL
FAN_RT_TACH SMC_FAN_0_TACH
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7
39
6 39
D
G S
P
2
_
4
P
2
_
6
V
D
D
P
0
_
4
P
0
_
2
P2_0
P2_2 P
0
_
0
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
P
1
_
1
P
1
_
3
P
1
_
5
P
1
_
7
P
7
_
7
V
S
S
D
+
D
-
V
D
D
P
7
_
0
P
1
_
0
P
1
_
2
P
1
_
4
P
1
_
6
P5_0
P5_2
P5_4
P5_6
P3_0
P3_2
P3_4
P4_0
P4_2
P4_4
P4_6
P3_6
P
2
_
5
P
2
_
7
P
0
_
3
V
S
S
P
0
_
5
P
0
_
7
P
0
_
6
PAD
THRML
(SYM-VER2)
P
0
_
1
IN
NC
NC
OUT
NC
NC
IN_A1
OUT_B
IN_A3_B2
GND
THRM
OUT_A
VDD
IN_A2
IN_B1
PAD
(IPD)
(IPD)
(IPD)
(IPD)
OUT
D
G S
IN_B1
IN_A2
VDD
THRM
GND
IN_A3_B2
OUT_B
IN_A1
OUT_A*
(IPD)
(IPD)
(IPD)
(IPD)
PAD
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3V3 LDO
PSOC
18V BOOSTER
LID CLOSE => SMC_LID_LC < 0.50V
337S2983
ISSP SCLK/I2C SCL
(PP3V3_S3_PSOC)
ISSP SDATA/I2C SDA
VDD
VIN 0.0188 V
0.021 V
0.012 V
0.012 V
0.6 V
0.204 V
0.0255 V
POWER V_SNS R_SNS CURRENT IC
10UA
- USB INTERFACES TO MLB
TMP102 V+
80UA
VOUT
VDD 60MA (MAX)
60MA (MAX)
8MA (TYP)
4MA (MAX)
14MA (MAX)
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
4.7 OHM
0.255E-6 W
16.32E-6 W
0.72E-3 W
294E-6 W
75.2E-6 W
96E-6 W
TPAD Buttons Disable
WHEN THE LID IS CLOSED
- SPI HOST TO Z2
- TRACKPAD PICK BUTTONS
- KEYBOARD SCANNER
518S0637
Keyboard Connector
36E-3 W
PIN NAME
PSOC USB CONTROLLER
THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
SMC Manual Reset & Isolation
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
Keys ANDed with PSOC power to isolate when PSOC is not powered.
LID OPEN => SMC_LID_LC ~ 3.42V
THE TPAD BUTTONS WILL BE DISABLE
PLACE THESE COMPONENTS CLOSE TO J5800 Q5701
SOD-VESM-HF
SSM3K15FV
C5706
BYPASS=U5701.49:50:11 mm
4.7UF
603
X5R
6.3V
20%
C5705
BYPASS=U5701.49:50:8 mm
0.1UF
402
X7R-CERM
16V
10%
C5704
BYPASS=U5701.49:50:5 mm
5%
50V
CERM
402
100PF
BYPASS=U5701.22:19:8 mm
0.1UF
402
X7R-CERM
16V
10%
C5703 C5702
100PF
BYPASS=U5701.22:19:5 mm
402
CERM
50V
5%
C5701
BYPASS=U5701.22:19:11 mm
20%
6.3V
603
4.7UF
X5R
R5702
24
1/16W
MF-LF
5%
402
U5701
CRITICAL
OMIT
CY8C24794
MLF
R5701
402
5%
MF-LF
1/16W
24
39 40 57
C5710
20%
0.1UF
PLACEMENT_NOTE=NEAR J5713
402
10V
CERM
R5710
1K
402
5%
MF-LF
1/16W
R5714
470
1/16W
MF-LF
1%
402
R5715
402
1%
MF-LF
1/16W
10K
J5713
CRITICAL
FF14-30A-R11B-B-3H
F-RT-SM
39 40
R5704
1 2
402
5%
MF-LF
1/16W
1.5
0.1UF
X7R-CERM
C5755
16V
10%
402
C5750
X7R-CERM
16V
10%
402
0.1UF
SLG4AP006
TDFN
U5750
CRITICAL
5%
R5720
1/16W
402
MF-LF
0
40
SOD-VESM-HF
SSM3K15FV
Q5702
NO STUFF
TDFN
CRITICAL
U5755
SLG4AP015V
WELLSPRING 1
BUTTON_DISABLE
=PP3V3_S3_TPAD
WS_LEFT_OPTION_KBD
=PP3V42_G3H_TPAD
WS_CONTROL_KBD
WS_CONTROL_KEY
WS_LEFT_SHIFT_KBD
SMC_TPAD_RST
WS_KBD15_C
WS_LEFT_OPTION_KBD
PICKB_L
TP_ISSP_SDATA_P1_0
VOLTAGE=3.3V
PP3V3_S3_PSOC
WS_LEFT_OPTION_KEY
WS_KBD16_NUM
WS_KBD15_C
WS_KBD16N
WS_KBD15_CAP
WS_KBD8
WS_KBD7
WS_KBD23
WS_KBD22
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD9
WS_KBD10
WS_KBD12
WS_KBD11
WS_KBD13
WS_KBD14
WS_KBD17
WS_KBD18
WS_KBD5
WS_KBD4
WS_KBD3
WS_KBD2
WS_KBD1
=PP3V3_S3_TPAD
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD22
WS_KBD18
WS_KBD23
WS_LEFT_OPTION_KEY
WS_LEFT_SHIFT_KEY
Z2_HOST_INTN
WS_KBD5
WS_KBD4
WS_KBD6
WS_KBD17
WS_KBD16N
WS_KBD14
WS_KBD12
WS_KBD13
WS_KBD11
WS_KBD10
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
WS_CONTROL_KEY
PSOC_MOSI
USB_TPAD_P
USB_TPAD_N
=PP3V3_S3_TPAD
BUTTON_DISABLE
SMC_LID
Z2_CLKIN
=PP3V42_G3H_TPAD
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_CONTROL_KBD
WS_KBD9
USB_TPAD_R_P
SMC_ONOFF_L
WS_KBD6
Z2_KEY_ACT_L
Z2_RESET
Z2_DEBUG3
PSOC_F_CS_L
TP_PSOC_SDA
TP_P4_5
TP_P7_7
USB_TPAD_R_N
TP_ISSP_SCLK_P1_1
TP_PSOC_P1_3
TP_PSOC_SCL
PSOC_SCLK
Z2_CS_L
Z2_MISO
Z2_MOSI
Z2_SCLK
SMC_TPAD_RST_L
PSOC_MISO
WS_LEFT_SHIFT_KEY
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57
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8
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2
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1
5
0
4
9
42
41
39
40
37
38
36
35
34
33
32
31
30
29
2
8
2
6
2
7
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
2
4
3
7
5
6
8
9
10
11
12
14
13
4
5
4
6
4
3
5
3
5
4
5
5
5
6
1 2
2
1
1 2
1 2
1 2
21
22
32
31
1
2
5
4
3
6
7
10
9
8
20
19
17
18
16
15
14
13
12
11
23
24
25
26
27
28
29
30
2
1
2
1
2
8
7
59
4
1
3
6
1 2
1
2
3
6
3
1
9 5
7
8
2
4
47
7 47 48
6 47
7 47
6 47
47
6 47
47
6 47
6 48
47
6
47
47
6
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
7 47 48
6 47
6 47
6 47
6 47
6 47
6 47
47
47
6 48
6 47
6 47
6 47
6 47
47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
6 47
47
6 48
17 75
17 75
7 47 48
47
6 48
7 47
6
6 47
6 47
6 47
79
6 47
6 48
6 48
6 48
6 48
79
6 48
6 48
6 48
6 48
6 48
6 48
47
CTRL
P
G
N
D
THRML
L
VIN
DO
FB
SW
PAD G
N
D
BI
THRML
CAP
SW
LED
VIN
CTRL
PAD GND
NC
NC
3 6
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K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNCED FROM T27
516S0689
IPD Flex Connector
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
If HIGH, keyboard backlight not present
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
518S0691
on keyboard backlight flex
J5815 pin 1 is grounded
Keyboard Backlight Connector
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- R5812,R5813,C5818 MODIFIED
- STARTUP TIME LESS THAN 2MS
- 100-300 KHZ CLEAN SPECTRUM
If LOW, keyboard backlight present
(SMC_KBDLED_PRESENT_L)
Keyboard Backlight Driver & Detection
CRITICAL
55560-0228
M-ST-SM
J5800
B0520WSXG
SOD-323
CRITICAL
D5802
25V
1UF
603-1
X5R
10%
C5819
1/16W
MF-LF
5%
402
0
R5806
10%
X7R-CERM
402
0.1UF
16V
C5816
0
1/16W
MF-LF
5%
402
R5805
2 1
16V
2.2UF
603
X5R
10%
C5817
TPS61045
QFN
CRITICAL
U5805
3.3UH-870MA
VLF3010AT-SM-HF
CRITICAL
L5801
402
MF-LF
1/16W
1%
100K
R5811
39
4.7K
KB_BL
402
MF-LF
1/16W
5%
R5854
MF-LF
470K
5%
1/16W
402
R5853
LT3491
DFN
U5850
CRITICAL
KB_BL
1/16W
5%
NO STUFF
402
MF-LF
10K
R5852
10%
X5R
402-1
1UF
10V
KB_BL
C5850
BYPASS=U5850.1:2:2 MM
KB_BL
402
MF-LF
1/16W
1%
10
R5855
KB_BL
1098AS-SM
L5850
10UH-0.58A-0.35OHM
CRITICAL
KB_BL
35V
1UF
603
X5R
10%
C5855
CRITICAL
KB_BL
FF18-4A-R11AD-B-3H
F-RT-SM
J5815
5%
CERM
402
39PF
50V
C5818
402
MF-LF
1/16W
1%
1M
R5812
71.5K
1%
1/16W
MF-LF
402
R5813
WELLSPRING 2
SMC_KDBLED_PRESENT_L
SMC_SYS_KBDLED
P18V5S3_FB
=PP5V_S3_TPAD
=PP5V_S0_KBDLED
=PP3V3_S0_TPAD
Z2_BOOST_EN
=PP3V3_S3_TPAD
Z2_CLKIN
Z2_HOST_INTN
Z2_BOOST_EN
Z2_SCLK
Z2_MISO
Z2_MOSI
Z2_DEBUG3
Z2_CS_L Z2_KEY_ACT_L
PP18V5_S3
=I2C_TPAD_SCL
=I2C_TPAD_SDA
PSOC_SCLK
PSOC_MOSI
PSOC_MISO
PICKB_L
PSOC_F_CS_L
Z2_RESET
SWITCH_NODE=TRUE
P18V5S3_SW
VOLTAGE=18.5V
PP18V5_S3_R
PP18V5_S3
VOLTAGE=18.5V
PP5V_S3_P18V5S3
VOLTAGE=5V
PP5V_S3_P18V5S3_VIN
VOLTAGE=5V
KBDLED_ANODE
KBDLED_CAP
SWITCH_NODE=TRUE
KBDLED_SW
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22
20
18
16
14
12
10
8
6
4
2
3
21
19
17
15
13
11
9
7
5
1
1 2
2
1
1 2
2
1
2
1
5
76 9
1
2
3
4
8
2 1
1
2
1
2
1
2
27
4
3
5
1
6
1
2
2
1
1
2
2 1
2
1
1
4
3
2
2
1
1
2
1
2
6
7
7
7
6 48
7 47
6 47
6 47
6 48
6 47
6 47
6 47
6 47
6 47 6 47
6 48
42
42
6 47
6 47
6 47
6 47
6 47
6 47
6 48
6
OUT
FS
PD
ST
RES
RES
GND
NC
NC
NC
NC
NC
NC
VOUTX
VOUTY
VOUTZ
VDD
IN
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
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+Y
+X
+Z (up)
Front of system
Circle indicates pin 1 location when placed
placed on board top-side:
Desired orientation when
in correct orientation
R5921 pulls up SMS_PWRDN
to turn off SMS when pin
is not being driven by SMC
Analog SMS
39
0.01UF
CERM
402
10%
16V
C5925
16V
10%
402
CERM
0.01UF
C5924
0.01UF
CERM
402
10%
16V
C5923
10K
MF-LF
402
5%
1/16W
R5921
AP344ALH
LGA
CRITICAL
U5920
10K
MF-LF
402
5%
1/16W
R5922
39
10UF
X5R
603
20%
4V
C5926
16V
10%
402
X5R
0.1UF
C5922
39
39
Sudden Motion Sensor (SMS)
SYNC_MASTER=T27_MLB
SMS_ONOFF_L
SMS_SELFTEST
=PP3V3_S3_SMS
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMS_PWRDN
MAKE_BASE=TRUE
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4
7
9
3
6
16
11
13
12
10
8
1
2
2
1
2
1
7
OUT
IN
IN IN
IN
GND
VCC
WP*/ACC
CE*
SI/SIO0
HOLD*
SCLK
SO/SIO1
3 6
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Frequency
0
0
1
1
SPI_MOSI SPI_CLK
0
1
0
1
MCP89 SPI Frequency Select
62.5 MHz
41.7 MHz
25.0 MHz
31.2 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
ROM will ignore SPI cycles.
NOTE: If HOLD* is asserted
20%
10V
CERM
402
0.1UF
C6100
3.3K
5%
1/16W
MF-LF
402
R6101
41 75
41 75
41 75 41 75
6 18 41
32MBIT
MX25L3205DM2I-12G
SOP
OMIT
CRITICAL
U6100
402
MF-LF
1/16W
5%
10K
SPI:41MHZ&SPI:62MHZ
R6151
402
MF-LF
1/16W
5%
10K
SPI:25MHZ&SPI:31MHZ
R6153
10K
5%
1/16W
MF-LF
402
SPI:25MHZ&SPI:41MHZ
R6152
10K
5%
1/16W
MF-LF
402
SPI:31MHZ&SPI:62MHZ
R6150
SPI ROM
SPI_MLB_MOSI
=PP3V3_S5_ROM
SPI_MLB_CLK
SPI_WP_L
SPI_MLB_MISO
SPI_MLB_CS_L
SPIROM_USE_MLB
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1
1
2
4
8
3
1
5
7
6
2
1
2
1
2
1
2
1
2
7
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT OUT
NR/FB
NC
IN
EN
GND
OUT
OUT
OUT
IN
IN
IN
OUT
VL_HD
SENSE_A
GPIO1/DMIC_SDA2
GPIO0/DMIC_SDA1
VHP_FILT+
GPIO2
RESET*
LINEOUT_L1-
VBIAS_DAC
FLYP
VA_REF VD
GPIO3
VHP_FILT-
LINEOUT_R1-
LINEOUT_R1+
LINEOUT_R2-
SPDIF_OUT
LINEIN_C-
FLYC
FLYN
SPDIF_IN
LINEOUT_L1+
THRM_PAD
VA_HP
HPOUT_R
HPREF
VCOM
AGND
VA
LINEIN_R+
LINEIN_L+
MICIN_L+
MICIN_L-
MICBIAS
SYNC
DGND
DMIC_SCL
HPOUT_L
SDI
SDO
VL_IF
BITCLK
MICIN_R-
MICIN_R+
VREF+_ADC
LINEOUT_L2+
LINEOUT_L2-
LINEOUT_R2+
/SPDIF_OUT2
OUT
IN
3 6
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Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
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8 7 5 4 2 1
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2355
AUDIO CODEC
NC
NC
NC
NC
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
EXT MIC CODEC INPUT
BI MIC CODEC INPUT
DIFF FSINPUT= 2.45VRMS
DAC1 FSOUTPUT= 1.34VRMS
APPLE P/N 353S2456
SE FSINPUT= 1.22VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
NOTES ON CODEC I/O
GPIO0 = ANALOG SW CONTROL
GPIO1 = HP AMP CONTROL
GPIO3 = SPKR AMP SHDN CONTROL
NC
NC
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL
603-1
X5R
20%
CRITICAL
6.3V
10UF
C6221
XW6201
SM
6.3V
20%
CERM
2.2UF
C6222
402-LF
6.3V
CERM
20%
C6223
2.2UF
402-LF
C6220
X5R
603-1
6.3V
20%
10UF
CRITICAL
0603-SM
1UF
C6224
TANT
20%
16V
X5R-1
C6210
4.7UF
20%
402
4V
18 75
18 75
18 75
18 75
18 75
56
54
53
53
54
54
54
56
56
56
56
56
20%
603-1
X5R
6.3V
10UF CRITICAL
C6213
402
X5R
10V
10%
1UF
C6201 1UF
X5R
402
10V
10%
C6203
0402
FERR-220-OHM
L6200
2.21K
1/16W
402
MF-LF
1%
R6200
402
X5R
C6200
10V
10%
1UF
16V
C6215
X5R
402
0.1UF
10%
0.1UF
C6211
X5R
16V
402
10%
X5R
0.1UF
16V
10%
402
C6214
1%
MF-LF
402
1/16W
R6210
2.67K
NOSTUFF
MF-LF
1/16W
5%
402
100K
R6213
402
R6211
MF-LF
1/16W
5%
22
0.1UF
C6218
X5R
10%
402
16V
10UF
16V
C6225
2012-LLP
20%
TANT-POLY
10UF
16V
20%
TANT-POLY
C6217
2012-LLP
C6219
16V
2012-LLP
10UF
TANT-POLY
20%
7 51 53 55
7 51 55 56
55
6 51
7
6 51
55
6 51
X5R
402-1
10V
10%
1UF
C6216
TPS71745
SON
CRITICAL
U6200
402
X7R-CERM
16V
10%
0.1UF
C6202
54
54
54
XW6200
SM
NOSTUFF
R6201
5%
MF-LF
0
1/16W
402
L6201
FERR-220-OHM
0402
MF-LF
39
5%
1/16W
402
R6212
52
52
52
53
CRITICAL
QFN
U6201
CS4206ACNZC
55
16V
X5R
10%
0.1UF
C6226
402
7 51 55 56
AUDIO: CODEC/REGULATOR
SYNC_DATE=08/31/2009 SYNC_MASTER=AUDIO
HDA_SDOUT
TP_AUD_SPDIF_IN
AUD_SPDIF_OUT_CHIP
HDA_BIT_CLK
HDA_RST_L
AUD_SPDIF_OUT
VOLTAGE=1.5V
PP1V8R1V5_S0_AUDIO_DIG
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
4V5_REG_IN
VOLTAGE=5V
VOLTAGE=0V
GND_AUDIO_HP_AMP MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM GND_AUDIO_CODEC
AUD_HP_PORT_L MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM AUD_HP_PORT_REF
MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM AUD_HP_PORT_R
PP4V5_AUDIO_ANALOG
CS4206_FN
=PP3V3R1V5_S0_AUDIO
TP_AUD_DMIC_CLK
CS4206_VCOM
AUD_MIC_INP_R
AUD_MIC_INN_L
AUD_LI_REF
AUD_LI_P_L
GND_AUDIO_CODEC
TP_AUD_LO1_N_L
=PP5V_S3_AUDIO
AUD_CODEC_MICBIAS
TP_AUD_LO1_P_L
CS4206_FLYN
CS4206_FLYC
AUD_GPIO_3
TP_AUD_GPIO_2
AUD_GPIO_0
CS4206_FLYP
GND_AUDIO_HP_AMP
PP4V5_AUDIO_ANALOG
HDA_SYNC
AUD_SDI_R
CS4206_FP
GND_AUDIO_HP_AMP
CS4206_VREF_ADC
AUD_LO2_P_L
AUD_LO1_P_R
AUD_LI_P_R
VBIAS_DAC
AUD_LO1_N_R
AUD_MIC_INP_L
AUD_MIC_INN_R
AUD_LO2_N_L
HDA_SDIN0
=PP3V3_S0_AUDIO
4V5_REG_EN
=PP5V_S3_AUDIO
4V5_NR
GND_AUDIO_CODEC
AUD_LO2_P_R
AUD_LO2_N_R
=PP1V8R1V5_S0_AUDIO
AUD_GPIO_1
AUD_SENSE_A
=PP3V3_S0_AUDIO
62 OF 109
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051-8563
51 OF 80
2
1
1 2
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2 1
1 2
2
1
2
1
2
1
2
1
1
2
1
2
1 2
2
1
1
2
1
2
1
2
2
1
1
3
5
2
6
4
2
1
1 2
1 2
2 1
1 2
3
13
12
2
44
14
11
34
29
45
2
4
9
15
41
37
36
33
48
22
43
42
47
35
4
9
4
6
40
39
28
2
6
2
5
23
21
18
17
16
10
7
4
38
8
5
1
6
20
19
27
31
30
32
2
1
51 53 55
51 52 55 56
8
51 52 55 56
7 51 53 55
51 53 55
51 53 55
51 52 55 56
IN
IN
IN
OUT
OUT
OUT
IN
3 6
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PAGE TITLE
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FC_LP = 43KHZ
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
CODEC RIN = 20K OHMS
LINE INPUT VOLTAGE DIVIDER
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
55
55
55
51
51
51
51 55 56
402
10V
2.2UF
CRITICAL
X5R-CERM
20%
C6301
20%
10V
2.2UF
X5R-CERM
402
CRITICAL
C6302
20%
402
10V
2.2UF
CRITICAL
X5R-CERM
C6312
2.2UF
402
10V
20%
X5R-CERM
CRITICAL
C6311
MF-LF
1/16W
402
1%
7.87K
R6301
MF-LF
1/16W
402
1%
7.87K
R6311
MF-LF
1/16W
402
1%
21.5K
R6302
MF-LF
1/16W
402
1%
21.5K
R6312
NOSTUFF
50V
CERM
402
820PF
10%
C6303
NOSTUFF
50V
CERM
402
820PF
10%
C6313
10
1%
402
MF-LF
1/16W
R6300
AUDIO: LINE INPUT FILTER
GND_AUDIO_CODEC
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_L
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_R
AUD_LI_P_L
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
63 OF 109
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1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
2
2
1
2
1
1
2
S
V
S
S
INL
SHDN*
INR
VDD
P
V
S
S
P
G
N
D
S
G
N
D
T
H
R
M
OUTR
OUTL
C1P
C1N
P
A
D
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
3 6
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REVISION
DRAWING NUMBER SIZE
D
R
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
APN: 353S1637
MAX9724 GAIN/FILTER COMPONENTS
NC
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
HP/LO AMP
AV_PB = -1V/V, FC_LPF = 35.2KHZ
NC
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).
16V
CRITICAL
X7R-CERM
402
10%
0.1UF
C6500
5%
1/16W
MF-LF
402
39
R6500
CRITICAL
C6510
402
X7R-CERM
16V
10%
0.1UF
1/16W
MF-LF
402
39
5%
R6510
CRITICAL
TQFN
MAX9724A
U6500
CRITICAL
C6522
10%
1UF
X5R
10V
402
10V
10%
1UF
C6523
CRITICAL
X5R
402
CRITICAL
C6524
10V
X5R
10%
1UF
402
6.3V
20%
10UF
X5R
C6521
603
C6520
10%
X7R-CERM
0.1UF
16V
402
FERR-120-OHM-1.5A
L6520
0402-LF
5%
MF-LF
1/16W
R6522
100K
402
1/16W
MF-LF
13.7K
R6531
1%
402
1/16W
R6530
1%
13.7K
MF-LF
402
MF-LF
1/16W
R6533
13.7K
1%
402
R6532
MF-LF
1/16W
13.7K
1%
402
5%
330PF
C6530
CRITICAL
COG
50V
402
C6531
50V
COG
330PF
5%
CRITICAL
402
0
R6520
MF-LF
402
1/16W
5%
R6521
0
MF-LF
1/16W
NO STUFF
5%
402
51 53
51 53
51
53 55
53 55
53 55
53 55
R6523
1%
2.21K
1/16W
MF-LF
402
R6524
1%
2.21K
1/16W
MF-LF
402
51 53
51 53 55
51 53
SYNC_DATE=07/17/2009 SYNC_MASTER=AUDIO
AUDIO: HEADPHONE FILTER
GND_AUDIO_HP_AMP
AUD_GPIO_1_R
AUD_LO_AMP_INR_M
AUD_LO_AMP_OUTL
AUD_LO_AMP_OUTR
AUD_PP5V_F
MAX9724_SVSS
MAX9724_C1N
MAX9724_C1P
AUD_LO_AMP_INR_M
AUD_HP_ZOBEL_L
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_HP_ZOBEL_R
GND_AUDIO_HP_AMP
AUD_LO_AMP_OUTR AUD_HP_PORT_R
AUD_HP_PORT_L
AUD_LO_AMP_INL_M
=PP5V_S3_AUDIO
AUD_LO_AMP_OUTL
AUD_LO_AMP_INL_M
AUD_GPIO_1
65 OF 109
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2
1
1
2
2
1
1
2
9
6
5
8
1
2
4 2 7
1
3
10
11
1
3
2
1
2
1
2
1
2
1
2
1
2 1
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
2 1
2
51 53 55
53
53
53
7 51 55
53
IN
IN
IN
IN
IN
IN
IN
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
3 6
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REVISION
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D
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PAGE TITLE
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A
D
2 1
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PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
6DB
80 HZ < FC < 132 HZ
SATELLITE & SUB TWEETER AMPLIFIER
SATELLITE
GAIN
SUB
APN:353S2524
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
169 HZ < FC < 282 HZ
C6610
10%
402
CRITICAL
0.0027UF
CERM
50V
51
51
402
10V
10%
X5R
C6607
1UF
FERR-1000-OHM
0402
L6620
FERR-1000-OHM
0402
L6610
FERR-1000-OHM
0402
L6630
51
402
C6609
10%
10V
X5R
1UF
402
1UF
C6608
10V
10%
X5R
20%
6.3V
TANT1
CRITICAL
C6601
47UF
2012-LLP
CASE-AL1
TANT
6.3V
C6603
100UF
20%
CRITICAL
TANT1
47UF
20%
6.3V
CRITICAL
C6605
2012-LLP
0
MF-LF
402
1/16W
5%
R6610
51
402
5%
R6611
1/16W
100K
MF-LF
FERR-1000-OHM
0402
L6611
51
FERR-1000-OHM
0402
L6621
51
FERR-1000-OHM
0402
L6631
51
CRITICAL
SSM2315
U6610
WLCSP
U6620
CRITICAL
WLCSP
SSM2315
U6630
CRITICAL
SSM2315
WLCSP
10%
CRITICAL
0.0027UF
CERM
50V
C6611
402
0.0027UF
C6630
50V
CERM
CRITICAL
10%
402
10%
CRITICAL
0.0027UF
CERM
50V
C6631
402
CRITICAL
10%
0.022UF
X7R
25V
C6621
0402
CRITICAL
C6620
10%
0.022UF
X7R
25V
0402
SYNC_MASTER=AUDIO SYNC_DATE=07/17/2009
AUDI0: SPEAKER AMP
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SHDN
=PP5V_S3_AUDIO_AMP
AUD_LO2_P_L
AUD_LO1_P_R
AUD_LO1_N_R
AUD_LO2_N_L
SPKRAMP_INR_N
SPKRAMP_INR_P
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SSM2315_R_N
SSM2315_R_P
SPKRAMP_SHDN
AUD_GPIO_3
SSM2315_L_P
SPKRAMP_INL_P
SSM2315_L_N SPKRAMP_INL_N
SSM2315_SUB_P
SPKRAMP_INSUB_P
AUD_LO2_P_R
AUD_LO2_N_R
=PP5V_S3_AUDIO_AMP
SPKRAMP_SHDN
=PP5V_S3_AUDIO_AMP
SSM2315_SUB_N SPKRAMP_INSUB_N
66 OF 109
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1 2
2
1
2 1
2 1
2 1
2
1
2
1
1
2
1
2
1
2
1 2
1
2
2 1
2 1
2 1
C2
C3
B
2
A
2
B
1
B
3
A1
C1
A3
C2
C3
B
2
A
2
B
1
B
3
A1
C1
A3
C2
C3
B
2
A
2
B
1
B
3
A1
C1
A3
1 2
1 2
1 2
1 2
1 2
6 55
6 55
6 55
6 55
54
7 54
6 55
6 55
54
7 54
54
7 54
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
BI
BI
BI
BI
RIGHT
MIC
AUDIO
GND
LEFT
SWITCH
DETECT
B - VCC
POF
SHIELD
SHELL
PINS
C - GND
A - VIN
OPERATING VOLTAGE 3.3
IN
IN
OUT
OUT
IN
VCC
COM1
COM2
EN*
NC1
CB
NO1
NEG
GND
NO2
NC2
IN
OUT
OUT
3 6
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REVISION
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PAGE
A
B
C
3 4 5 6 7 8
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B
8 7 5 4 2 1
(AUD_CONN_GND)
GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
GND STUFFING OPTIONS FOR CMOS SWITCH
CHASSIS GND STITCHES
APN:514-0671
APN:518S0520
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX
APN:518S0519
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
APN: 353S2803
ANALOG AUDIO IO SWITCH
SPEAKER CONNECTOR
MIC CONNECTOR
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
APN:518S0521
1UF
402
10%
6.3V
CERM
C6700
6 54
6 54
6 54
6 54
6 54
6 54
78171-0004
M-RT-SM
J6703
CRITICAL
CRITICAL
J6702
M-RT-SM
78171-0002
402
DZ6704
6.8V-100PF
CRITICAL
CRITICAL
DZ6703
6.8V-100PF
402
DZ6700
402
CRITICAL
6.8V-100PF
CRITICAL
DZ6705
6.8V-100PF
402
CRITICAL
J6701
78171-0003
M-RT-SM
C6761
CERM
5%
402
50V
33PF
NO STUFF
CERM
50V
33PF
402
5%
C6760
NO STUFF
CERM
402
C6762
33PF
5%
50V
NO STUFF
NO STUFF
C6763
5%
50V
CERM
402
33PF
402
0
5%
1/16W
R6760
MF-LF
0402
L6702
FERR-1000-OHM
L6701
FERR-1000-OHM
0402
56
56
6.8V-100PF
DZ6701
CRITICAL
402
51
402
CERM
50V
0.0033UF
10%
C6711
SM
XW6700
SM
XW6701
55
55
402
MF-LF
1/16W
R6714
5%
0
5%
0
R6715
402
MF-LF
1/16W
SM
XW6711
SM
XW6710
402
R6717
MF-LF
1/16W
5%
0
MF-LF
402
1/16W
5%
R6718
0
MF-LF
1/16W
0
R6719
5%
402
R6716
402
0
5%
1/16W
MF-LF
55
55
402
5%
MF-LF
1/16W
R6721
100K
10%
10V
1UF
C6710
X5R
402
J6700
CRITICAL
F-RT-TH
SPDIF-TXRX-K24
402
5%
MF-LF
24K
R6712
1/16W
402
1/16W
MF-LF
24K
5%
R6713
402
1/16W
0
5%
MF-LF
R6727
NOSTUFF
52
52
53
53
51
SM
XW6702
CRITICAL
WLP
MAX14560EWC+
U6700
51
CRITICAL
L6703
0402-LF
FERR-120-OHM-1.5A
0402
CRITICAL
L6705
FERR-220-OHM
FERR-220-OHM
0402
L6704
CRITICAL
56
56
1/16W
MF-LF
5%
402
10K
R6700
402
4.7
MF-LF
5%
1/16W
R6701
50V
CERM
5%
402
C6701
100PF
AUDIO: JACK
SYNC_MASTER=AUDIO
=PP5V_S3_AUDIO
AUD_SWITCH_GND
VOLTAGE=0V
AUD_GPIO_0
AUD_LO_AMP_OUTR
AUD_LO_AMP_OUTL
AUD_CONN_L
AUD_CONN_R MIN_NECK_WIDTH=0.15MM
SPKRAMP_R_N_OUT
AUD_CONNJ1_SLEEVE
GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V
=PP3V3_S0_AUDIO
AUD_CONNJ1_RING
AUD_J1_SLEEVEDET_R
AUD_LI_L
AUD_LI_R
AUD_CONN_L
AUD_CONNJ1_TIP
AUD_CONNJ1_TIPDET
AUD_CONNJ1_SLEEVEDET
AUD_LO_AMP_OUTL_SWITCH
GND_AUDIO_CODEC
AUD_J1_TIPDET_R
AUD_CONN_R
AUD_HP_PORT_REF
GND_AUDIO_HP_AMP
SPKRAMP_R_P_OUT
SPKRAMP_L_P_OUT
AUD_LI_GND
AUD_CONN_GND
BI_MIC_HI
BI_MIC_SHIELD
BI_MIC_LO
HS_MIC_HI
HS_MIC_LO
SPKRAMP_L_N_OUT
SPKRAMP_SUB_N_OUT
AUD_CONNJ1_MIC
AUD_LO_AMP_OUTR_SWITCH
AUD_LI_R_SWITCH
SWITCH_CP
AUD_LI_L_SWITCH
AUD_SPDIF_OUT
AUD_CONN_GND
SPKRAMP_SUB_P_OUT
67 OF 109
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051-8563
55 OF 80
2
1
5
1
2
4
6
3
4
2
1
3
1
2
1
2
1
2 1
2
5
1
3
2
4
2
1
2
1
2
1
2
1
1 2
2 1
2 1
1
2
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
2
1
10
11
12
13
6
5
2
1
3
9
8
7
4
1
2
1
2
1 2
1 2
A
3
C
3
B4
B1
B2
C4
C2
A4
A2
B
3
A1
C1
2 1
2 1
2 1
1 2
1 2
2
1
7 51 53
7 51 56
51 52 56
51 53
52
55
6 56
6 56
6 56
55
IN
OUT
IN
D
S G
D
S G
D
S G
D
S G
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
BI
IN
OUT
OUT
IN
GND THM
ENABLE
AVDD
SDA
MICBIAS
DETECT
BYPASS INT*
SCL
D
S G
D
S G
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
PORT B RIGHT(BUILT-IN MIC)
CODEC OUTPUT SIGNAL PATHS
0X02 (2)
0X04 (4)
0X05 (5)
MIKEY
MIC_BIAS (80%)
MUTE CONTROL
GPIO_0 AND GPIO_1
PIN COMPLEX
PIN COMPLEX
0X09 (9,A)
0X0C (12)
0X08 (8)
GPIO_3
GPIO_3
N/A
GPIO_0 AND GPIO_1
0X0A (10) N/A
VREF
HP/LINE OUT
SUB
SPDIF OUT N/A
0X04 (4)
0X03 (03)
0X10 (16)
0X0B (11)
PORT B DETECT(SPDIF DELEGATE)
FUNCTION
NC
HP=80HZ
FUNCTION
DRC MIKEY
PORT B LEFT(HEADSET MIC) CONVERTER
CONVERTER
0X06 (6) BUILT-IN MIC
HP=80HZ, LP=8.82KHZ
HEADSET MIC
PULLUPS ON MCP PAGE
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
EXTRACTION NOTIFICATION CKT
APN:376S0613
NC
DET ASSIGNMENT
0X09 (A)
0X09 (A)AND UI ELEMENT
N/A
N/A
MIKEY
PORT A DETECT (HEADPHONES)
0X0D (13,V22,B,LEFT)
0X0D (13,B,RIGHT)
0X06 (6)
DET ASSIGNMENT
0X0D (B)
CODEC INPUT SIGNAL PATHS
0X02 (2)
VOLUME
0X05 (5)
0X03 (3)
SATELLITES
LINE IN
APN:353S2256
C6801
402
0.1UF
CERM
20% 10V
47K
1/16W
MF-LF
402
5%
R6802
55 56
R6806
402
39.2K
1/16W
1%
MF-LF
1/16W
5%
220K
402
MF-LF
R6803
R6804
220K
1/16W
MF-LF
5%
402
C6802
10%
402
0.01UF
CERM
16V
51
55 56
20.0K
1/16W
MF-LF
1%
R6805
402
SOT563
SSM6N15FEAPE
Q6800
Q6800
SSM6N15FEAPE
SOT563
SSM6N15FEAPE
Q6801
SOT563 SOT563
SSM6N15FEAPE
Q6801
2.4K
R6851
1/16W
1%
402-1
MF
C6854
CERM 402
5%
27PF
50V
CRITICAL
10%
25V
402
CRITICAL
0.1UF
X5R
C6850
402
50V
CERM
CRITICAL
10%
0.001UF
C6853
402
100K
R6852
5%
1/16W
MF-LF
SM
XW6851
51
51
51
6 55
6 55
6 55
CRITICAL
C6852
2.2UF
402
6.3V
TANT
20%
L6851
FERR-1000-OHM
0402
FERR-1000-OHM
0402
L6850
55
55
402
5%
MF-LF
1/16W
2.2K
MIKEY
R6882
C6885
CERM 402
50V 5%
27PF
MIKEY
CRITICAL
25V
402
10%
0.0082UF
CRITICAL
X7R
C6884
MIKEY R6883
5%
100K
402
MF-LF
1/16W
MIKEY
X5R
CRITICAL
C6883
0.1UF
10%
25V
402
MIKEY
XW6880
SM
51
MIKEY
402
1%
MF-LF
R6881
1K
1/16W
5%
1/16W
402
MF-LF
100K
R6880
NOSTUFF
0.01UF
16V 10%
402 CERM
MIKEY
C6881
0402
FERR-1000-OHM
MIKEY
L6880
TANT
6.3V
402
2.2UF
MIKEY
20%
CRITICAL
C6882
18
42
42
18
1/16W
5%
2.2K
R6884
MIKEY
402
MF-LF
CRITICAL
MIKEY
C6886
0.1UF
X5R
10%
25V
402
51
C6851
CRITICAL
0.1UF
25V
X5R
402
10%
MF-LF
1/16W
1%
402
R6850
100
2.4K
MF
1%
1/16W
R6853
402-1
16
1/16W
0
MF-LF
5%
R6861
402
CERM
0.1UF
402
20% 10V
C6861
L6862
FERR-1000-OHM
0402
7 51 55 56
U6880
CD3275
DRC
MIKEY
CRITICAL
CERM
1UF
10%
6.3V
C6880
MIKEY
402
SSM6N15FEAPE
SOT563
Q6802
SOT563
Q6802
SSM6N15FEAPE
5%
15K
1/16W
MF-LF
R6860
402
10V
CERM
0.1UF
20%
C6860
402
220K
5%
1/16W
MF-LF
R6864
402
MF-LF
1/16W
5%
100K
R6865
402
300K
R6801
5%
1/16W
MF-LF
402
NOSTUFF
R6885
MF-LF
1/16W
10K
5%
402
AUDIO: JACK TRANSLATORS
SYNC_MASTER=AUDIO SYNC_DATE=08/27/2009
AUD_IPHS_SWITCH_EN
=I2C_MIKEY_SDA
=I2C_MIKEY_SCL
=PP3V3_S0_AUDIO
HS_RX_BP
HS_MIC_LO
HS_MIC_HI
HS_MIC_BIAS
HS_SW_DET
GND_AUDIO_CODEC AUD_SENSE_A
AUD_J1_TIPDET_R
AUD_PORTB_DET_L AUD_PORTA_DET_L
PP3V3_S0_AUDIO_F
AUD_J1_TIPDET_R
GND_AUDIO_CODEC
=PP3V3_S0_AUDIO
AUD_IP_PERIPHERAL_DET AUD_PERPH_DET_R
TIPDET_FILT
AUD_J1_TIPDET_INV
AUD_J1_SLEEVEDET_R
AUD_MIC_INN_L
AUD_MIC_INP_L
BI_MIC_HI_F
PP3V3_S0_AUDIO_F
GND_AUDIO_CODEC
BI_MIC_LO
AUD_MIC_INP_R
AUD_MIC_INN_R
AUD_CODEC_MICBIAS
GND_AUDIO_CODEC
BI_MIC_HI
GND_AUDIO_CODEC
AUD_J1_DET_RC
AUD_J1_SLEEVEDET_R
GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_INV
BI_MIC_SHIELD
BI_MIC_LO_F
MIC_BIAS_FILT
GND_AUDIO_CODEC
AUD_OUTJACK_INSERT_L
HS_MIC_HI_RC
AUD_I2C_INT_L
GND_AUDIO_CODEC
PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
PP3V3_S0_HS_RX
VOLTAGE=3.3V
68 OF 109
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1 2
1
2
1 2
1
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2
1
1
2
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4 5
6
1 2
3
4
5
6
1
2
1 2
2
1
1 2
2
1
1
2
1 2
1
2
2 1
2 1
1
2
2
1
2
1
1
2
1 2
1 2
1
2
1
2 2
1
2 1
1
2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
2 1
9
1
1
8
4
3
5
1
2
10 7
6
2
1
6
1
2
3
4
5
1 2
2
1
1
2
1
2
1
2
1
2
7 51 55 56
51 52 55 56
56
55 56
51 52 55 56
56
51 52 55 56
51 52 55 56
51 52 55 56
55 56
51 52 55 56
51 52 55 56
51 52 55 56
56
NC
VCC
EXT INT
NC GND
BI
Y
B
A
BI
BI
P3
P4
P5
P6
P7
P8
P1
P2
P9
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
SW
BOOST VIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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PAGE TITLE
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A
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Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
1-Wire OverVoltage Protection
TO SMC
3.425V "G3Hot" Supply
518-0359
NC
BIL CONNECTOR
NC
516S0523
Vout = 1.25V * (1 + Ra / Rb)
<Rb>
<Ra>
Supply needs to guarantee 3.31V delivered to SMC VRef generator
(Switcher limit)
250MA MAX OUTPUT
Vout = 3.425V
NC
518S0656
BATTERY CONNECTOR
MagSafe DC Power Jack
C6905
50V
0.01UF
603
20%
CERM
6.3V
20%
CERM
805
22UF
C6999
CRITICAL
CDPH4D19FHF-SM
L6995
33UH
CRITICAL
C6994
X5R
6.3V
402
20%
0.22uF
1/16W
MF-LF
348K
1%
R6995
402 402
CERM
50V
22pF
C6995
5%
MF-LF
R6996
1/16W
200K
1%
402
10UF
C6990
805
X5R
10%
25V
R6905
805
5%
1/8W
1
MF-LF
J6900
CRITICAL
78048-0573
M-RT-SM
CERM
C6954
10%
402
0.001UF
50V
X5R
402
10%
25V
C6950
0.1UF
0.1UF
X5R
C6951
10%
25V
402
CRITICAL
F6905
6AMP-24V
1206-1
RCLAMP2402B
CRITICAL
D6950
SC-75
PLACEMENT_NOTE=PLACE NEAR U6901 20%
10V
CERM
402
0.1UF
C6908
U6900
MAX9940
SC70-5
39
U6901
SOT665
TC7SZ08AFEAPE
MF-LF
402
1/16W
5%
R6950
10K
CRITICAL
CPB6312-0101F
J6955
F-ST-SM
CERM
402
47PF
5%
C6952
50V
47PF
5%
C6953
50V
CERM
402
42 57
42 57
50V
402
C6955
0.001UF
10%
CERM
402 1/16W
R6961
5%
100
MF-LF
CRITICAL
M-RT-TH
J6950
BAT-K24
LT3470A
DFN
U6990
CRITICAL
2.0K
R6929
402
5%
1/16W
MF-LF
R6900
NOSTUFF
MF-LF
402
5%
1/16W
100K
10%
X5R
25V
603-1
1UF
C6960
DC-In & Battery Connectors
SYS_ONEWIRE
P3V42G3H_BOOST
DIDT=TRUE
=PP3V42_G3H_REG
PPVBAT_G3H_CONN
SYS_DETECT_L
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
SMC_BIL_BUTTON_L
ADAPTER_SENSE
=PP3V42_G3H_ONEWIRE
SMC_BC_ACOK
PPDCIN_G3H_OR_PBUS
P3V42G3H_FB
=PP3V42_G3H_BATT
SMC_LID_R SMC_LID
=SMBUS_BATT_SDA
SMC_BC_ACOK_VCC
=PP18V5_DCIN_CONN
PPDCIN_G3H_OR_PBUS_R
VOLTAGE=18.5V
VOLTAGE=18.5V
MIN_LINE_WIDTH=1mm
PP18V5_DCIN_FUSE
P3V42G3H_SW
DIDT=TRUE SWITCH_NODE=TRUE
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2 1
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1
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1 2
3
2
1
4
5
2
1
2
1
2
1
2 1
3
2 1
2
1
1
5 4
23
3
5
1
4
2
1
2
12 11
10 9
8
6 5
4 3
7
15 16
1 2
14 13
2
1
2
1
2
1
1 2
3
4
5
6
7
8
1
2
9
10
11
12
13
4
3 6
2
8
5
7
1
9
1
2 1
2
2
1
7
6 58
6
42 57
42 57
6 39
40
6
7
8 39 40
58
7
6 39 40 47
7 6
OUT
OUT
IN
BI
OUT
IN
D
G
S
S
D
G
D
G
S
D
G
S
IN
AMON
BMON
ACOK
LGATE
PHASE
BOOT
SGATE
AGATE
CSIP
CSIN
DCIN
VNEG
CSOP
CSON
T
H
R
M
_
P
A
D
P
G
N
D
VDDP VDD
BGATE
UGATE
ICOMP
VCOMP
ACIN
SDA
VFRQ
CELL
VHST
SCL
SMB_RST_N
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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Apple Inc.
PAGE
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C
3 4 5 6 7 8
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B
8 7 5 4 2 1
3% TOLERANCE
20V/V
353S2929
(
A
G
N
D
)36V/V
(OD)
(CHGR_SGATE)
(CHGR_DCIN)
ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Input impedance of ~40K meets
sparkitecture requirements
Float CELL for 1S
f = 400 kHz
Reverse-Current Protection
Max Current = 8A
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
(CHGR_CSO_P)
(PPVBAT_G3H_CHGR_R)
30mA max load
(CHGR_BGATE)
(GND)
(CHGR_CSO_N)
TO SYSTEM
This node is powered
Q7055.
Inrush Limiter
(CHGR_AGATE)
(PPVBAT_G3H_CHGR_R)
Charger TOP FETs and
* PBUS through Q7085,
through body diodes:
* DCIN through Q7080.
TO/FROM BATTERY
FROM ADAPTER
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
1%
402
MF-LF
9.31K
1/16W
R7011
0.033UF
16V
X5R
10%
402
C7042
402
10%
CERM
50V
470PF
C7016
1/16W
402
MF-LF
1%
3.01K
R7016
CERM
470PF
50V
10%
402
C7015
220K
5%
MF-LF
1/16W
402
R7015
402
10V
1UF
X5R
10%
C7002
X5R
402-1
1UF
10%
10V
C7000
4.7
402
5%
1/16W
MF-LF
R7001
1%
402
R7010
30.1K
1/16W
MF-LF
XW7000
SM
X5R
1UF
10%
402
C7001
10V
10%
402
X5R
25V
0.1UF
C7021
10%
C7022
X5R
402
25V
0.1UF
C7020
10%
10V
CERM
402
0.047UF
0.22UF
C7025
10V
CERM
10%
402
LFPAK-HF
CRITICAL
Q7035
RJK0305DPB
5%
MF-LF
10
402
1/16W
R7022
402
1/16W
5%
MF-LF
10
R7021
CASE-D2-SM
CRITICAL
C7030
22UF
POLY-TANT
20%
25V
CASE-D2-SM
CRITICAL
22UF
25V
POLY-TANT
20%
C7031
8AMP-24V
F7040
CRITICAL
1206
5% 402
2.2
1/16W MF-LF
R7051
0
1/16W 5% MF-LF 402
R7052
MF-LF
402
1/16W
1%
332K
R7086
402
62K
1/16W
MF-LF
5%
R7081
25V
X5R
603
0.22UF
20%
C7005
44
44
42
42
0.01UF
16V
CERM
402
10%
C7011
402
1UF
10%
16V
X5R
C7050
0.001UF
10%
402
CERM
50V
C7026
8
1W
R7050
0.01
0.5%
MF
0612-1
0.020
0.5%
MF-LF
0612
CRITICAL
1W
R7020
X7R
402
10%
0.001UF
50V
C7037
50V
470PF
CERM
10%
NO STUFF
402
C7039
R7039
603
180
1/10W
MF-LF
5%
NO STUFF
C7045
X7R
402
50V
10%
0.001UF
NO STUFF
5%
1/16W
MF-LF
100K
402
R7002
65
SI7137DP
Q7055
CRITICAL
SO-8
NO STUFF
1/16W
1K
402
1%
MF-LF
R7013
SOT-323
CRITICAL
BAT30CWFILM
D7005
0.1UF
402
X5R
10%
25V
C7085
402
100K
5%
R7080
MF-LF
1/16W
402
MF-LF
1%
470K
1/16W
R7085
R7012
1/16W
MF-LF
402
1K
1% RJK0332DPB-01
CRITICAL
Q7030
LFPAK-SM
C7040
CASE-D2-SM
22UF
20%
25V
POLY-TANT
CRITICAL
R7005
MF-LF
1/16W
5%
20
402
603-1
1UF
10%
25V
X5R
C7035 C7036
603-1
1UF
10%
25V
X5R
IHLP4040DZ-SM
CRITICAL
L7030
4.7UH-9.5A
CRITICAL SO-8
Q7085
SI7149DP SI7149DP
Q7080
CRITICAL
SO-8
R7000
0
MF-LF
1/16W
5%
402
39 40 41
CRITICAL
U7000
I
S
L
6
2
5
9
TQFN
PBus Supply & Battery Charger
GND_CHGR_AGND
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
VOLTAGE=18.5V
PPDCIN_G3H_INRUSH
CHGR_SGATE_DIV
CHGR_AGATE_DIV
VOLTAGE=12.6V
PPVBAT_G3H_CONN
DIDT=TRUE
CHGR_PHASE_RC
CHGR_VNEG_R
CHGR_CSO_R_P
CHGR_DCIN_D_R
CHGR_CSI_R_N
CHGR_CSI_R_P
CHGR_CSO_R_N
PPDCIN_G3H_CHGR
VOLTAGE=18.5V
=PPBUS_G3H
CHGR_VCOMP_R
SMC_RESET_L
=PPDCIN_S5_CHGR
VOLTAGE=18.5V
PPDCIN_G3H_OR_PBUS
PPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
CHGR_RST_L
=SMBUS_CHGR_SCL
=PP3V42_G3H_CHGR
CHGR_CELL
CHGR_VFRQ
=SMBUS_CHGR_SDA
CHGR_ACIN
CHGR_VCOMP
CHGR_ICOMP
CHGR_UGATE
GATE_NODE=TRUE DIDT=TRUE
CHGR_BGATE
PP5V1_CHGR_VDD
VOLTAGE=5.1V
VOLTAGE=5.1V
PP5V1_CHGR_VDDP
GND_CHGR_AGND
VOLTAGE=0V
CHGR_CSO_N
CHGR_CSO_P
CHGR_VNEG
CHGR_DCIN
CHGR_CSI_N
CHGR_CSI_P
CHGR_AGATE
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
CHGR_SGATE
CHGR_BOOT
DIDT=TRUE
CHGR_PHASE
SWITCH_NODE=TRUE
DIDT=TRUE
CHGR_LGATE
GATE_NODE=TRUE DIDT=TRUE
=CHGR_ACOK
CHGR_BMON
CHGR_AMON
70 OF 109
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1 2
1
2
1 2
2
1
2
1
2
1
2
1
2
1
1 2 3
5
4
1 2
1 2
1
2
1
2
2 1
1 2
1 2
1
2
1
2
2
1
2
1
2
1
2
1
4 3
2 1
2
1 3
4
2
1
2
1
1
2
2
1
1
2
4
3
5 2
1
1
2
3
1
2
2
1
1
2
1
2
1
2
4
3 2 1
5
1
2
1 2
2
1
2
1
2 1
4
3
5 2
1
4
3
52
1
1 2
9
15
14
21
23
25
26
1
28
27
2
8
18
17
2
9
2
2
2
0
1
9
16
24
5
7
3
10
4
6
12
11
13
58
6 57
44 78
78
78
44 78
7
7
57
7 65
58
78
78
78
78
IN
IN
D
S G
D
S G
S
D
G
G
D
S
D1
G1
S2
G2
S1/D2
DRVH1
SKIPSEL
VBST1
GND THRM_PAD
ENTRIP1
VFB1
VO1
DRVL1
LL1
EN0
VCLK
ENTRIP2
PGOOD
VO2
VFB2
DRVL2
LL2
DRVH2
VBST2
VREG5
VREG3
VREF VIN
TONSEL
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
MAX CURRENT = 13.3A
ROUTING NOTE:
NC
Place XW7201 between Pin 15 and Pin 25 of U7200.
NOTE: DONT SYNC THIS PAGE FROM T27
ROUTING NOTE:
ROUTING NOTE:
<RC>
VOUT = (2 * RC / RD) + 2
<RB>
ROUTING NOTE:
<RD>
Place XW7203 by Pin1 OF L7260. Place XW7204 by Pin 2 of L7220.
PWM FREQ. = 300 KHZ
Place XW7205 by C7252.
<RA>
VOUT = (2 * RA / RB) + 2
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
5V_S3/3.3V_S5 POWER SUPPLY
ROUTING NOTE:
PWM FREQ. = 375 KHZ
MAX CURRENT = 9.1A
6.3V
X5R
20%
603
10UF
C7273
PLACE_NEAR=U7200.25:1 MM
XW7201
SM
65
65
SSM6N15FEAPE
SOT563
Q7221
SOT563
Q7221
SSM6N15FEAPE
XW7202
SM
SM
XW7203
XW7205
SM
SM
XW7204
100K
R7273
1/16W
5%
MF-LF
402
C7220 10%
16V
X5R
402
0.1UF
DIDT=TRUE
CERM
0.001UF
20%
C7282
402
50V
402
CERM
0.001UF
20%
50V
C7242
0.001UF
C7293
402
20%
CERM
50V 20%
402
CERM
50V
0.001UF
C7253
CRITICAL
39UF-0.027OHM
C7240
B1A-SM
20%
16V
POLY
220UF
C7291
20%
6.3V
ELEC
D1A-SM
CRITICAL
B1A-SM
150UF
20%
6.3V
POLY
CRITICAL
C7251
C7280
39UF-0.027OHM
B1A-SM
POLY
16V
20%
CRITICAL
PWRPK-1212-8-SM
CRITICAL
SIS424DN
Q7260
Q7261
SIS426DN
PWRPK-12128
CRITICAL
R7220
0
MF-LF 1/16W 5% 402
Q7220
RJK0384DPA
CRITICAL
WPAK
L7220
CRITICAL
4.7UH-10A
PCMC063T-SM
C7250
6.3V
603
X5R
10UF
20%
4.7UH-13A-15MOHM
PCMB104E4R7-SM
L7260
CRITICAL
1/16W
MF-LF
402
1%
6.49K
R7270
1/16W
MF-LF
1%
10K
402
R7269
1UF
C7241
603-1
X5R
25V
10%
10%
16V
402
C7260
0.1UF
X5R
15.0K
1%
MF-LF
402
1/16W
R7267 R7268
1/16W
MF-LF
402
1%
10K
25V
X5R
10%
1UF
603-1
C7281
6.3V
20%
C7290
10UF
603
X5R
3V3S5_VFB
QFN
T
P
S
5
1
1
2
5
U7200
CRITICAL
1%
86.6K
402
MF-LF
1/16W
R7271
75K
MF-LF
1%
1/16W
402
R7272
C7272
1UF
25V
603-1
X5R
10%
C7270
1UF
CERM
20%
603
10V
CERM
10V
10%
0.22UF
402
C7271
5V/3.3V SUPPLY
=PP3V3_S5_REG
MIN_NECK_WIDTH=0.2 MM DIDT=TRUE
3V3S5_LL
3V3S5VO2
=P5V3V3_REG_EN
=PPVIN_S3_5VS3
=PPVIN_S5_3V3S5
DIDT=TRUE
3V3S5DRVL
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
3V3S5_DRVH
5V3V3S5_REG3
5V3V3_REG_EN
DIDT=TRUE
5V_S3_DRVH
DIDT=TRUE
5V_S3_VBST
5V_S3_LL
DIDT=TRUE
DIDT=TRUE 3V3S5_VBST
3V3S5_VBST_R
PP5V_S5_LDO
MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V
5V_S3_VFB
=P3V3S5_EN_L
3V3S5_VFB_R7270
GND_5V3V3S5_SGND
5V_S3_VFB_XW7203
=PPVIN_S3_5VS3
5V_S3_ENTRIP
=P5VS3_EN_L
=PP5V_S3_REG
5V_S3_VO1
5VS3_3V3S5_VREF
5V_S3_DRVL
DIDT=TRUE
3V3S5_ENTRIP
P5V3V3_PGOOD
VOLTAGE=0V
GND_5V3V3S5_SGND
72 OF 109
A.13.0
051-8563
59 OF 80
2
1
1 2
6
1
2
3
4
5
1 2
1 2
1 2
1 2
1
2
1 2
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
4
3 2 1
5
4
1 3 2
5
1 2
2
1
345
6
7
2 1
2
1
2 1
1 2 1 2
2
1
1 2
1 2 1 2
2
1
2
1
21
14
22
1
5
2
5
1
2
24
19
20
13
18
6
23
7
5
12
11
10
9
17
8
3 1
6
4
1
2
1
2
2
1
2
1
2
1
7
65
7 59
7
59
7 59
7
65
59
MODE
VDDQSNS COMP
NC0
NC1
VTTSNS
VTT
VTTREF
PGOOD
S3
S5
VTTGND THRM_PAD GND CS_GND PGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOIN V5FILT V5IN
SYM (2 OF 2)
IN
IN
OUT
NC
NC
D
G S
IN
S
D
G
G
D
S
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
f = 400 kHz
19A MAX OUTPUT
Vout = 0.75V * (1 + Ra / Req)
SEL_1V5=0: Req = Rb
Use LVDDR3 for 1.5V/1.35V support or LVDDR3_NOT for fixed 1.5V operation.
SEL_1V5=1: Req = Rb || Rc
(DDRREG_DRVL)
(DDRREG_CSGND)
(DDRREG_FB)
(DDRREG_VDDQSNS)
(DDRREG_DRVH)
Vout = VTTREF
<Ra>
VTT Enable
VDDQ PGOOD
Vout = VDDQSNS/2
Vout = 1.501V / 1.352V
(DDRREG_LL)
<Rb>
NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS
(GND_DDRREG_SGND)
10mA max load
<Rc>
VDDQ/VTTREF Enable
402
0.1UF
10%
16V
X5R
C7325
MF-LF
402
1/16W
1%
15.0K
R7320
LVDDR3:YES
18.7K
402
1/16W
1%
R7321
MF-LF
C7332
1UF
603-1
X5R
25V
10%
CRITICAL
U7300
TPS51116
QFN
R7305
402
5%
MF-LF
1/16W
4.7
22UF
603
X5R-CERM
6.3V
20%
CRITICAL
C7361
CRITICAL
22UF
603
X5R-CERM
6.3V
20%
C7360
SM
XW7360
SM
XW7335
C7350
10%
16V
X5R
402
0.033UF
65
805
10%
X5R
10V
C7300
4.7UF
65
R7310
10K
1%
402
MF-LF
1/16W
PCMB065T-SM
1.0UH-13A-5.6MOHM
L7330
CRITICAL
SM
XW7345
PLACE_NEAR=L7330.2:1 MM
C7355
20%
6.3V
X5R
603
10UF
CRITICAL
CASE-B2-SM
2.5V
TANT
C7341
330UF
20%
2.5V
TANT
20%
C7340
CASE-B2-SM
330UF
CRITICAL
C7345
10UF
20%
6.3V
603
X5R
10%
50V
X7R
402
0.001UF
C7333
402
10%
50V
X7R
0.001UF
C7346
C7305
1UF
10%
10V
X5R
402-1
LVDDR3:YES
R7322
402
MF-LF
1/16W
1%
75K
LVDDR3:YES
SSM3K15FV
SOD-VESM-HF
Q7322
18
SM
XW7300
PLACE_NEAR=U7300.3:1 mm PLACE_NEAR=U7300.25:1 mm
PWRPK-1212-8-SM
Q7330
SIS424DN
CRITICAL
CRITICAL
SIS426DN
Q7335
PWRPK-12128
16V
POLY
B1A-SM
CRITICAL
20%
C7330
39UF-0.027OHM
B1A-SM
POLY
16V
20%
C7331
39UF-0.027OHM
CRITICAL
R7325
0
402
MF-LF
1/16W
5%
50V
0.001UF
C7320
LVDDR3:YES
402
X7R
10%
402
MF-LF
1/16W
R7380
100K
5%
LVDDR3:NO R7321 1 114S0331 RES,15K,1%,1/16W,MF-LF,0402
1.5V/1.35V LVDDR3 Supply
DIDT=TRUE
DDRREG_LL
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
DDRREG_VDDQSNS
VOLTAGE=5V
PP5V_S3_DDRREG_V5FILT
DDRREG_VBST
DIDT=TRUE MIN_NECK_WIDTH=0.17 mm
DDRREG_DRVH
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
DDRREG_VBST_R
DDRREG_DRVL
DIDT=TRUE
GATE_NODE=TRUE
DDRREG_PGOOD
=PP3V3_S3_PDCISENS
=PP5V_S3_DDRREG
=PPDDR_S3_REG
DDRREG_P1V5_L
=PPVIN_S3_DDRREG
=PPVTT_S0_DDR_LDO
=PPVTT_S3_DDR_BUF
=DDRREG_EN
=DDRVTT_EN
MCP_MEM_VDD_SEL_1V5
=PPVIN_S0_DDRREG_LDO
DDRREG_VTTSNS
DDRREG_CS
DDRREG_FB
VOLTAGE=0V
GND_DDRREG_SGND
DDRREG_CSGND
73 OF 109
A.13.0
051-8563
60 OF 80
1 2
1
2
1
2
2
1
4
8 6
7
12
2
24
5
13
10
11
1
2
53
1
7
1
8
16
20
19
21
9
22
2
3
1
4
1
5
1 2
2
1
2
1
1 2
1 2
2
1
2
1
1
2
2 1
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
1
2
1
2
3
1 2
4
3 2 1
5
4
1 3 2
5
1
2
1
2
1 2
2
1
1
2
7
7
7
7
7
7 28
7
28
IN
IN
IN
OUT
IN
VID0
DPRSTP*
NC
VW
COMP
FB
FB2
RBIAS
VR_TT*
NTC
VR_ON
PGOOD
PSI*
RTN
VSEN
DFB
DROOP
VO
OCSET
VSUM
ISEN2
VID1
VID3
VID2
VID4
VID5
VID6
PGND2
VIN VDD PVCC
LGATE2
PHASE2
UGATE2
ISEN1
PGND1
LGATE1
UGATE1
PHASE1
BOOT1
BOOT2
3V3
VDIFF
SOFT
DPRSLPVR
TPAD GND
CLK_EN*
IMON OUT
G
D
S
G
D
S
S
D
G
S
D
G
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
LOAD LINE SLOPE = -2.1 MV/A
(IMVP6_ISEN2)
K6 NOTES : Q7400-Q7403 CHANGED BACK TO K24 FETS DUE TO LAYOUT
(IMVP6_VO)
(KEEP THIS NET AS SHORT AS POSSIBLE)
MAX CURRENT = 65.2A
PWM FREQ. = 300 KHZ
0
0
TO U7400.33 WITH MIN LOOP AREA)
(THIS NET SHOULD CONNECT
(KEEP THIS NET AS SHORT AS POSSIBLE) (GND)
(GND)
(NC)
1
(IMVP6_PHASE1)
1
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
1-PHASE DCM
(IMVP6_VW)
MIN_NECK_WIDTH
1
0
1
1
MIN_LINE_WIDTH MIN_NECK_WIDTH
0
(IMVP6_COMP)
FROM SMC
0
DPRSTP*
0
DPRSLPVR
1
1-PHASE DCM
MIN_LINE_WIDTH
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
ERT-J1VR103J
MIN_LINE_WIDTH
ERT-J0EV474J
K6 NOTES : BOM OPTION ADDED TO NTC
(IMVP6_ISEN1)
(IMVP6_VO)
1-PHASE CCM
2-PHASE CCM
OPERATION MODE PSI*
(IMVP6_FB)
(IMVP6_PHASE2)
(THIS NET SHOULD CONNECT
TO U7400.29 WITH MIN LOOP AREA)
IMVP6 CPU VCORE REGULATOR
(IMVP6_VSUM)
MIN_NECK_WIDTH
SM
OMIT
XW7400
PLACE_NEAR=U7400.21:1 MM
MF-LF
R7400
402
10K
1%
1/16W
1%
402
1/16W
3.65K
R7401
MF-LF
X5R
25V
402
10%
C7415
0.1UF
13.7K
402
MF-LF
1%
1/16W
R7416
1%
11K
1/16W
MF-LF
402
R7415
R7405
MF-LF
1%
10K
1/16W
402
C7404
402
10%
10V
CERM
0.22UF
1/16W
R7443
MF-LF
3.65K
402
1%
X5R
C7427
10%
0.1UF
25V
402
5%
10
1/16W
MF-LF
402
R7420
402
10
1/16W
R7412
5%
MF-LF
C7426
402
10%
1UF
X5R
16V
10%
402
X5R
16V
C7496
1UF
5%
402
MF-LF
10
R7421
1/16W
C7430
10V
10%
402
X5R
1UF
402
1K
1%
MF-LF
R7413
1/16W
1/16W
R7409
402
1%
1K
MF-LF
R7411
402
1%
1/16W
MF-LF
255
C7414
10%
402
470PF
50V
CERM
97.6K
402
1%
1/16W
MF-LF
R7414
C7413
402
CERM
25V
5%
220PF
0.001UF
402
CERM
10%
50V
C7407 R7410
MF-LF
1%
6.81K
1/16W
402
4.02K
1/16W
MF-LF
R7417
1%
402
R7418
MF-LF
1%
402
1/16W
1K
CERM
180pF
C7429
50V
5%
402
0.22UF
CERM
C7428
402
10%
10V
C7431
10%
402
CERM
50V
0.001UF
10%
CERM
402
50V
0.001UF
C7432
C7433
CERM
402
10%
50V
0.001UF
MF-LF
1/16W
R7422
402
10
1%
R7423
402
1/16W
MF-LF
10
1%
X5R
16V
10%
402
C7434
0.033UF
R7427
1%
402
MF-LF
1/16W
CPU_NTC:YES
4.02K
10%
16V
CERM
402
0.01uF
C7410
CPU_NTC:YES
X7R
402
10%
16V
C7405
0.015uF
1/16W
402
MF-LF
1%
R7408
147K
10%
C7406
0.001UF
CERM
402
50V
C7416
402
CERM
NO STUFF
50V
10%
0.001UF
1/16W
1%
2.61K
R7430
402
MF-LF
CERM-X5R
0.22uF
402
6.3V
10%
C7421
0.22UF
CERM
10V
402
C7403
10%
CRITICAL
R7431
0603-LF
10KOHM-5%
499
MF-LF
1/16W
1%
402
R7445
470K
R7426
CRITICAL 402
CPU_NTC:YES
402
MF-LF
1/16W
0
5%
R7425
1/16W
5%
402
0
MF-LF
R7424
0
402
5%
MF-LF
1/16W
R7406
CPU_NTC:YES
603-1
X5R
25V
10%
1UF
C7418
C7411
603-1
X5R
10%
25V
1UF
QFN
I
S
L
9
5
0
4
B
C
R
Z
CRITICAL
U7400
R7447
2.0K
5%
1/16W
MF-LF
402
50V
0.001UF
402
CERM
C7420
10%
C7419
0.001UF
402
50V
CERM
10%
402
C7422
10%
50V
CERM
0.001UF
0.001UF
402
C7423
50V
CERM
10%
CRITICAL
L7400
MPCG1040-SM
0.36UH-26A-1.05MOHM
CRITICAL
MPCG1040-SM
L7401
0.36UH-26A-1.05MOHM
R7499
68
5%
MF-LF
402
1/16W
CPU_NTC:YES
10%
10V
4.7UF
805
X5R
C7435
Q7401
RJK0208DPA
CRITICAL
WPAK
CRITICAL
WPAK
Q7403
RJK0208DPA
Q7400
WPAK
CRITICAL
RJK0365DPA-02
WPAK
CRITICAL
Q7402
RJK0365DPA-02
SM
XW7410
SM
XW7411
R7404
MF-LF
1/16W
5%
1
402
SM
XW7412
SM
XW7413
MF-LF
5%
402
R7407
1
1/16W
C7409
CRITICAL
20%
68UF
16V
POLY-TANT
CASE-D2E-SM
C7417
CRITICAL
20%
68UF
16V
POLY-TANT
CASE-D2E-SM
C7401
CRITICAL
20%
68UF
16V
POLY-TANT
CASE-D2E-SM
CRITICAL
20%
68UF
16V
CASE-D2E-SM
C7408
POLY-TANT
IMVP6 CPU VCore Regulator
IMVP6_ISEN2
IMVP6_VO
IMVP6_OCSET 0.25 MM 0.20 MM
IMVP6_VSUM
0.20 MM IMVP6_DFB 0.25 MM
IMVP6_DROOP 0.25 MM 0.20 MM
0.25 MM IMVP6_VO 0.20 MM
GND_IMVP6_SGND 0.50 MM 0.20 MM
1.5 MM IMVP6_PHASE1 0.25 MM
=PPVIN_S5_CPU_IMVP
IMVP6_ISEN1
DIDT=TRUE
IMVP6_PHASE2
IMVP6_COMP
IMVP6_OCSET
IMVP6_DROOP
VOLTAGE=0V
GND_IMVP6_SGND
IMVP6_FB
IMVP6_IMON
IMVP6_UGATE1
DIDT=TRUE
IMVP6_BOOT1_RC
DIDT=TRUE
CPU_VID<3>
IMVP6_VDIFF 0.25 MM 0.20 MM
0.25 MM 0.20 MM IMVP6_COMP
0.20 MM IMVP6_VSEN 0.25 MM
0.20 MM 0.25 MM IMVP6_RTN
IMVP6_FB 0.25 MM 0.20 MM
PM_DPRSLPVR
VR_PWRGOOD_DELAY
VOLTAGE=3.3V
PP3V3_S0_IMVP6_3V3
IMVP_DPRSLPVR
CPU_PSI_L
CPU_DPRSTP_L
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
IMVP6_SOFT
IMVP6_NTC
IMVP6_VR_TT
0.25 MM 0.25 MM IMVP6_PHASE2
0.20 MM IMVP6_BOOT2 0.25 MM
IMVP6_UGATE2 0.25 MM 0.25 MM
IMVP6_LGATE2 0.25 MM 0.25 MM
0.20 MM IMVP6_ISEN2 0.25 MM
CPU_VCCSENSE_N
PP5V_S0_IMVP6_VDD
VOLTAGE=5V
=PP3V3_S0_IMVP
IMVP6_LGATE1
DIDT=TRUE
IMVP6_BOOT2_RC
DIDT=TRUE
0.20 MM 0.25 MM IMVP6_VW
PPVIN_S5_IMVP6_VIN
VOLTAGE=12.6V
IMVP6_BOOT1
DIDT=TRUE
DIDT=TRUE
IMVP6_BOOT2
IMVP6_SOFT 0.20 MM 0.25 MM
0.20 MM IMVP6_FB2 0.25 MM
1.5 MM 0.25 MM IMVP6_UGATE1
IMVP6_RBIAS 0.20 MM 0.25 MM
0.25 MM IMVP6_VSUM 0.20 MM
IMVP6_LGATE1 0.25 MM 1.5 MM
I
M
V
P
6
_
R
T
N
IMVP6_FB2
CPU_VID<4>
IMVP_VR_ON
I
M
V
P
6
_
V
S
E
N
IMVP6_NTC_R
IMVP6_VW
IMVP6_VDIFF_RC
=PP1V05_S0_CPU
CPU_PROCHOT_L
IMVP6_COMP_RC
IMVP6_VO_R
CPU_VCCSENSE_P
IMVP6_VDIFF
=PPVIN_S5_CPU_IMVP
IMVP_VO2
=PP5V_S0_CPU_IMVP
CPU_VID<6>
CPU_VID<5>
IMVP6_RBIAS
IMVP6_DFB
GND_IMVP6_SGND
IMVP6_UGATE2
DIDT=TRUE
DIDT=TRUE
IMVP6_LGATE2
IMVP_VSUM1
IMVP_VSUM2
IMVP6_BOOT1 0.25 MM 0.25 MM
0.20 MM IMVP6_ISEN1 0.25 MM
=PPVCORE_S0_CPU_REG
=PPVIN_S5_CPU_IMVP
DIDT=TRUE
IMVP6_PHASE1
IMVP_VO1
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2
1
1 2
1
2
2
1
1
2
1
2
1 2 1 2
1
2
2
1
1 2
1 2
2
1
2
1
1 2
2
1
1 2
1
2
1
2
2
1
1
2
2
1
2
1
1
2
1 2
1
2
2
1
2
1
1 2
1 2
1 2
1
2
1
2
2
1
1 2
1 2
1 2
1 2
2
1
2
1
1
2
1 2
1 2
2
1
1
2
2 1
1 2
1 2
1 2
2
1
2
1
37
46
25
9
10
11
12
4
5
6
44
1
2
15
14
17
16
18
8
19
23
38
40
39
41
42
43
29
20 22 31
30
28
27
24
33
32
35
34
36
26
48
13
7
45
49 21
47
3
1
2
2
1
2
1
2
1
2
1
2 1
2 1
1
2
2
1
5
3 2 1
4
5
3 2 1
4
4
3 2 1
5
4
3 2 1
5
1 2
1 2
1
2
1 2
1 2
1
2
61
61
61
61
61
61
61
61
61
7 61
61
61
61
61
61
61
61
44
61 10 72
61
61
61
61
61
13 72
24
72
9
9 13 72
10 72
10 72
10 72
61
61
61
61
61
61
10 72
7
61
61
61
61
61
61
61
61
61
61
61
61
10 72
39
61
61
7 9 10
11 12
9 13 40
72
10 72
61
7 61
7
10 72
10 72
61
61
61
61
61
61
61
7
7 61
61
IN
IN
IN
OUT
OUT
IN
IN
NC
IN
IN
G
D
S
S
D
G
NC
ISP
OCSET
ISN
ICOMP
LGATE
COMP
VDIFF
AF_EN
IMON
VID3
VID2
VDD
BOOT
FB
FDE
PGND
PGOOD PHASE
PVCC
RTN
THRM_PAD
VID0
VID1
VO
VSEN
VSS
VW
UGATE
VIN RBIAS
SOFT
VR_ON
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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PAGE TITLE
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2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
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1011 0.7875V
(MCPCORES0_VW)
(MCPCORES0_VSEN)
(MCPCORES0_RTN)
VID<3:0> VOLTAGE
MAX CURRENT: 30.4A
f = 300 kHz
K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27
1110 0.9500V
1101 0.9625V
0000 0.9250V
0001 0.9125V
1111 0.9375V
0011 0.8875V
1100 0.9750V
0100 0.8750V
1010 0.8000V
0101 0.8625V
0110 0.8500V
0111 0.8375V
(MCPCORES0_ISN)
(MCPCORES0_ICOMP)
0010 0.9000V
(MCPCORES0_FB)
(MCPCORES0_COMP)
(Q7560 Limit)
(MCPCORES0_VO)
1001 0.8125V
1000 0.8250V
(MCPCORES0_PHASE)
(MCPCORES0_VDIFF)
(MCPCORES0_UGATE)
18
18
R7568
20
MF-LF
1%
402
1/16W
1/16W
402
R7566
MF-LF
1%
20
0.001UF
10%
C7570
402
X7R
50V
1%
100
402
1/16W
MF-LF
R7563
C7576
0.1UF
10%
402
16V
X7R-CERM
150K
R7572
1%
402
MF-LF
1/16W
65
65
R7561
1K
1/16W
5%
402
MF-LF
SM
XW7561
1/16W
1%
402
MF-LF
R7575
22.1K
1/16W
402
10K
1%
R7573
MF-LF
9.76K
MF-LF
402
1/16W
1%
R7569
5%
603
2
1
R7565
1/10W
MF-LF
0
603
5%
10V
CERM-X7R
0.22UF
C7564
402
16V
X5R
C7550
1UF
10%
1/10W
5%
603
MF-LF
R7560
2.2
402
X5R
16V
10%
C7562
1UF
MF-LF
1/16W
1%
402
200
R7578
1/16W
1%
402
MF-LF
3.01K
R7579
150K
R7577
1%
402
MF-LF
1/16W
C7580
50V
COG
402
5%
330PF
100PF
CERM
402
50V
5%
C7581
1%
100
1/16W
MF-LF
402
R7571
C7582
CERM
402
10%
100V
4700PF
0.001UF
50V
10%
402
X7R
C7579
1/16W
402
6.98K
MF-LF
1%
R7576
X5R
20%
603
4V
10UF
C7566
CASE-B4-SM
2V
TANT
270UF
20%
CRITICAL
C7568
10%
402
50V
X7R
0.001UF
C7569
20%
2V
TANT
CASE-B4-SM
CRITICAL
C7565
270UF
C7567
20%
X5R
10UF
603
4V
1UF
10%
25V
C7561
X5R
603-1
C7563
0.001UF
10%
50V
X7R
402
100
402
MF-LF
1/16W
1%
R7500
47PF
CERM
5%
50V
402
C7573
47PF
5%
CERM
402
50V
C7575
CRITICAL
R7525
1%
MF
0612
0.001
1W
L7560
CRITICAL
FDU1040D-SM
0.56UH-31A
CASE-D2E-SM
POLY-TANT
16V
CRITICAL
C7540
20%
68UF 68UF
CASE-D2E-SM
C7560
CRITICAL
20%
POLY-TANT
16V
44
CRITICAL
C7541
20%
68UF
16V
POLY-TANT
CASE-D2E-SM
21 79
21 79
NO STUFF
MF-LF
R7593
402 5% 1/16W
0
MF-LF
R7590
5%
0
1/16W 402
MF-LF
R7591
1/16W
0
402 5%
0.001UF
50V
X7R
402
10%
C7578
402
X7R
50V
10%
0.001UF
C7577
1/16W MF-LF 5%
R7592 0
402
MF-LF 402
R7594
5%
0
1/16W
18
18
WPAK
CRITICAL
Q7565
RJK0208DPA
RJK0365DPA-02
WPAK
Q7560
CRITICAL
QFN
CRITICAL
U7500
I
S
L
9
5
6
3
B
MCP VCore Regulator
MCPCORES0_VSEN_N
MCPCORES0_FB
MCPCORES0_PGOOD
MCP_VID0_REG
MCP_VID1_REG
MCPCORES0_VSEN
=PPVIN_S0_MCPCORE
MCPCORES0_ISP_R
PPMCPCORE_S0_R
VOLTAGE=1V
MCPCORES0_UGATE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
MCPCORES0_PHASE
MCPCORES0_OCSET
MCPCORES0_ISN
MCPCORES0_FDE
MCPCORES0_IMON_R
MCP_VID3_REG
=PP5V_S0_MCPREG
MCPCORES0_VW
MCPCORES0_RBIAS
MCPCORES0_SOFT
MCP_VID<0>
MCP_VID<2>
MCP_VID<1>
MCPCORES0_VSEN_P
MCPCORES0_COMP_C
=PPMCPCORE_S0_REG
MCPCORES0_IMON
MCPCORES0_VDIF_C
=PPMCPCORE_S0_REG
DIDT=TRUE
MCPCORES0_BOOT_R
DIDT=TRUE
MCPCORES0_BOOT
PP5V_S0_MCPREG_VDD
VOLTAGE=5V
DIDT=TRUE
MCPCORES0_LGATE
GATE_NODE=TRUE
MCPCORES0_ISP
MCPCORES0_ICOMP
MCP_VID<3>
MCP_VID2_REG
=MCPCORES0_EN
MCPCORES0_RTN
MCPCORES0_COMP
MCPCORES0_VDIFF
GND_MCPCORES0_AGND
VOLTAGE=0V
MCPCORES0_VO
75 OF 109
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1 2
1 2
2
1
1
2
2
1
1
2
1
2
1 2
1
2
1
2
1 2
2
1
2
1
1 2
2
1
1 2
1 2
1 2
1 2
1 2
1
2
1 2
2
1
1
2
2
1
1
2 2
1
1
2
2
1
2
1
2
1
1 2
2
1
2
1
4 3
2 1 2 1
1
2
1
2
1
2
1 2
1 2
1 2
2
1
2
1
1 2
1 2
5
3 2 1
4
4
3 2 1
5
23
13
3
11
10
21
5
7
30
28
27
26
1
6
17
6
32
2
0
31 19
2
2
9
3
3
24
25
12
8
1
5
4
18
14 1
2
29
7
8
7
7 62
7 62
8
VBST
TON
LL
DRVH
DRVL
V5FILT V5DRV
PGND GND
EN_PSV
VOUT
TRIP
VFB
THRM_PAD
PGOOD
SYM 2
IN
OUT
D1
G1
S2
G2
S1/D2
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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VOUT = 1.066V
(CPUVTTS0_VFB)
K6 NOTES : Q7620 CHANGED BACK TO K24 FETS DUE TO LAYOUT
F = 360 KHZ
(=PPCPUVTT_S0_REG)
(=PPCPUVTT_S0_REG)
ROUTING NOTE:
(GND)
<Rb>
<Ra>
CPUVTT POWER SUPPLY
Vout = 0.75V * (1 + Ra / Rb)
15A MAX OUTPUT
X5R
10UF
6.3V
603
20%
C7665
XW7665
SM
P
L
A
C
E
M
E
N
T
_
N
O
T
E
=
P
l
a
c
e

X
W
7
6
6
5

n
e
x
t

t
o

L
7
6
2
0
100PF
402
C7670
5%
50V
NO STUFF
CERM
402
1/16W
1%
R7670
8.45K
MF-LF
MF-LF
R7671
20.0K
1/16W
402
1%
R7603
MF-LF
1%
402
226K
1/16W
C7695
1UF
25V
10%
603-1
X5R
4.7UF
C7604
X5R
10%
805
10V
CRITICAL
U7600
QFN
TPS51117RGY_QFN14
XW7600
PLACE_NEAR=U7600.7:1MM
PLACE_NEAR=U7600.15:1MM
SM
10%
C7601
10V
1UF
402-1
X5R
65
65
8.87K
R7604
402
MF-LF
1/16W
1%
R7601
1%
MF-LF
402
1/16W
301
402
C7696
0.001UF
50V
CERM
20%
C7661
50V
0.001UF
CERM
20%
402
L7620
PCMB065T-SM
2.2UH-8.0A
CRITICAL
XW7601
SM
CASE-B2-SM
CRITICAL
TANT
2.5V
20%
C7660
330UF
10%
0.1UF C7603
16V
X5R
402
402
R7680
0
1/16W
5%
MF-LF
C7630
CRITICAL
20%
16V
POLY-TANT
CASE-D2E-SM
68UF
WPAK
Q7620
RJK0384DPA
CPU VTT(1.05V) SUPPLY
=PPVIN_S0_CPUVTTS0
CPUVTTS0_PGOOD
=CPUVTTS0_EN
CPUVTTS0_VOUT
CPUVTTS0_VFB
CPUVTTS0_TON
CPUVTTS0_TRIP
=PP5V_S0_CPUVTTS0
=PPCPUVTT_S0_REG
GND_CPUVTTS0_SGND
VOLTAGE=0V
VOLTAGE=5V
PP5V_S0_CPUVTTS0_V5FILT
CPUVTTS0_VBST_R
DIDT=TRUE
DIDT=TRUE
CPUVTTS0_VBST
MIN_LINE_WIDTH=0.6MM GATE_NODE=TRUE DIDT=TRUE
CPUVTTS0_DRVL
CPUVTTS0_DRVH
GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM
SWITCH_NODE=TRUE
CPUVTTS0_LL
DIDT=TRUE
CPUVTTS0_VSNS
76 OF 109
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2
1 2
1
2
1
1
2
1
2
1
2
2
1
2
1
14
2
12
13
9
410
8 7
1
3
11
5
15
6
1 2
2
1
1
2
1 2
2
1
2
1
2 1
2
1
1
2
1 2 1 2
1
2
2
1
345
6
7
7
7 7
VI
SW EN
FB
GND
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND THRM_PAD
IN
OUT
IN
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND THRM_PAD
OUT
V
I
N
EN SW
G
N
D
FB/VO
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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PAGE TITLE
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PAGE
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1.05V S0 MCP PLL LDO
MCP 0.9V S5 (AUXC) Switcher
Vout = 1.8V
K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNCED FROM T27
1.5V S0 Regulator
Vout = 0.8V * (1 + Ra / Rb)
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
1.2V ENET Switcher
PLACEHOLDER!
BCM57765 Internal Switcher Support
(This may be required to use BCM57765)
Max Current = 0.7A
Vout = 1.2V
1.8V S0 Switcher
<Rb>
<Ra>
Vout = 0.902V
f = 1.6MHZ
Vout = 1.508V
f = 1.6MHZ
<Ra>
TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.
BOMOPTIONs:
TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.
MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER.
353S2769
F = 1.7MHZ
MAX CURRENT = 0.3A
F = 1MHZ
MAX CURRENT = 1.5A
MAX CURRENT = 1.5A
PCAA031B-SM
CRITICAL
10UH-0.55A-330MOHM
L7760
10uF
603
X5R
6.3V
20%
C7762
10uF
603
X5R
6.3V
20%
C7760
CRITICAL
SOT23-5
TPS62202
U7760
805
CERM
20%
6.3V
22UF
C7750
CRITICAL
402
MF-LF
1/16W
1%
25.5K
R7751
402
MF-LF
1/16W
1%
200K
R7752
47PF
402
CERM
50V
5%
C7751
IHLP1616BZ-SM
2.2UH-3.25A
CRITICAL
L7750
65
ISL8009B
CRITICAL
DFN
U7750
MCPPLL_R:REG
402
5%
MF-LF
1/16W
0
R7745
65
65
65
SM
XW7721
PCAA031B-SM
BCM5764M
CRITICAL
2.2UH-1.2A
L7720
CERM
22UF
BCM5764M
805
6.3V
20%
C7721
C7720
BCM5764M
22UF
805
CERM
6.3V
20%
65
ISL8009B
U7710
DFN
CRITICAL
CERM
805
6.3V
20%
22UF
C7710
CRITICAL
402
113K
1%
1/16W
MF-LF
R7712
402
50V
5%
CERM
47PF
C7711
100K
1%
1/16W
MF-LF
402
R7711
20%
CERM
22UF
CRITICAL
6.3V
805
C7715
CRITICAL
2.2UH-3.25A
IHLP1616BZ-SM
L7710
0.1UF
402
CERM
10V
20%
BCM57765
C7731
0
1/16W
MF-LF
5%
402
BCM57765
R7731
0
1/16W
MF-LF
5%
402
BCM57765
R7730
X5R
20%
6.3V
603
10uF
BCM57765
C7735
10V
CERM
402
20%
0.1UF
BCM57765
C7736
603
CERM
20%
4.7UF
BCM57765
6.3V
C7730
2.2UH-1.2A
PCAA031B-SM
CRITICAL
BCM57765
L7735
0
1/16W
MF-LF
5%
402
BCM57765
R7735
65
CRITICAL
BCM5764M
U7720
ST1S12G12R
TSOT23-5L
805
6.3V
CERM
CRITICAL
22UF
20%
C7755
Misc Power Supplies
P1V2ENET_FB
P1V5S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
P0V9S5_SW
SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
P1V2ENET_SW
BCM57765_SR_LX
SWITCH_NODE=TRUE
DIDT=TRUE
PP3V3_ENET_PHY_VDDP
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_ENET_PHY_VDD
MAKE_BASE=TRUE
VOLTAGE=1.2V
PP1V2_ENET_PHY_VFB
P1V8S0_SW
DIDT=TRUE
SWITCH_NODE=TRUE
=PP1V5_S0_REG
=PP1V05_S0_MCP_PLL_OR
=PP1V05_S0_MCP_PLL_UF_R
=P0V9S5_EN
P0V9S5_PGOOD
=PP3V3_S0_P1V8S0
BCM57765_SR_VFB
BCM57765_SR_VDD
TP_BCM57765_SR_VDDP
=P1V8S0_EN
=P1V2ENET_EN
=PP3V3_ENET_PHY
=PP1V2_ENET_REG
=PP1V2_ENET_PHY_REG
P0V9S5_FB
=PP0V9_S5_REG
P1V5S0_FB
=PP1V8_S0_REG
=PP3V3_S5_P0V9S5
P1V5S0_PGOOD
=P1V5S0_EN
=PP3V3_S0_P1V5S0
=PP3V3_ENET_P1V2ENET
77 OF 109
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051-8563
64 OF 80
1
2
2
1 2
1
2
1
4
3 5
2
1
1
2
1
2
2
1
2 1
1
8
6
5
2
3
4
7 9
1 2
1 2
2 1
2
1
2
1
1
8
6
5
2
3
4
7 9
2
1
1
2
2
1
1
2
2
1
2 1
2
1
1 2
1 2
2
1
2
1
2
1
2 1
1 2
4
1 3
2
5
2
1
31
7
7
7
7
31
31
31
7 24 31
7
7
7
7
7
7
7
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
D
S G
D
S G
D
S G
OUT
NC
D
S G
IN
OUT
D
G S
OUT
VDD
OUT_A*
OUT_A
THRM
GND
IN_A
DLY_1C
IN_B
OUT_B DLY (OD,IPU)
(OD,IPU)
(OD,IPU) (IPD)
1.3V
PAD
2:1
-
+
OUT IN
OUT
OUT IN
OUT
IN
THRM_PAD GND
V3MON
V4MON RST*
MR*
VDD VDDA
V2MON
Q3
Q2
Q4
Q1
NC
NC
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
S0 Rail PGOOD (ISL Version)
S0 Rail PGOOD Circuitry
the same time as MEMVDD rail (Q2300).
K6 HAS A PULL UP ON DDRREG_PGOOD. REMOVED ALIAS TO TP SIGNAL
V4MON: 0.610V
VTT rail must ramp up in about
VTT Rail Enable
ENET Rail Enables
S0 Rail PGOOD (BJT Version)
S3 Rail Enables
3.3V w/Divider: 2.345V
Worst-Case Thresholds:
S5 Rail Enables & PGOOD
Internal pull-ups 100K +/- 20%
S0 Rail Enables
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
WLAN Enable Generation
Q4: 0.660V
Q3: 0.640V
Q2: 0.XXXV
PM_SLP_S3_L PM_SLP_S4_L
1
0
0
0
1
0
0
1
State
0
1
1
1
SMC_PM_G2_ENABLE
Battery Off (G3Hot)
Run (S0)
Soft-Off (S5)
Sleep (S3)
Pull-up is with power FET.
Worst-Case Thresholds:
V2MON: 3.000V
V3MON: 0.610V
(IPU)
353S2718
Power Control Signals
VDD: 2.9140V
353S2809
ISL6259 Frequency Select
DLY > 10 ms
Threshold: ??
59
24 39
MF-LF
1/16W
5%
402
68K
R7813
2
1
NO STUFF
C7813
402
CERM
10V
10%
0.068UF
0
1/16W
MF-LF
5%
402
R7812
NO STUFF
C7812
10%
6.3V
CERM-X5R
402
0.47UF
59
37
402
5%
MF-LF
1/16W
100
R7859
66
1/16W
402
MF-LF
5%
5.1K
R7884
2
1
10%
6.3V
CERM-X5R
402
0.47UF
C7884
66
6 18 39 65 69
18 39 40
18 29
SOT563
SSM6N15FEAPE
Q7890
SSM6N15FEAPE
SOT563
Q7891
SSM6N15FEAPE
SOT563
Q7890
29
0.1uF
S0PGOOD_ISL
20%
10V
CERM
402
C7870 20.0K
1%
1/16W
MF-LF
402
S0PGOOD_ISL
R7871
S0PGOOD_ISL
10K
1%
1/16W
402
MF-LF
R7870
SOT563
SSM6N15FEAPE
Q7891
64
60
0
5%
1/16W
402
MF-LF
VFRQ:SLPS4
R7864
MF-LF
1/16W
5%
0
402
VFRQ:SLPS3
R7863
SSM3K15FV
SOD-VESM-HF
VFRQ:SLPS4&VFRQ:SLPS3
Q7860
10K
5%
1/16W
MF-LF
402
VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
R7861
402
MF-LF
1/16W
5%
10K
VFRQ:LOW
R7860
58
CRITICAL
TDFN
SLG4AP012
U7840
402
CERM
5%
25V
220PF
C7841
402
CERM
10V
20%
0.1uF
C7840
39 64
64
59
10%
402
16V
X5R
0.033UF
C7801
6 39
59
18 20
ISL88042IRTJJZ
TDFN
S0PGOOD_ISL
CRITICAL
U7870
ASMCC0179
S0PGOOD_BJT
CRITICAL
DFN2015H4-8
Q7820
1/16W
S0PGOOD_BJT
15.0K
402
MF-LF
1%
R7821
S0PGOOD_BJT
1%
7.15K
MF-LF
1/16W
402
R7822
MF-LF
402
1/16W
S0PGOOD_BJT
1K
5%
R7823
S0PGOOD_BJT
5%
402
1/16W
MF-LF
1K
R7824
S0PGOOD_BJT
1/16W
402
MF-LF
5%
1K
R7825
402
MF-LF
100
5%
1/16W
S0PGOOD_BJT
R7827
402
5%
1/16W
MF-LF
10
S0PGOOD_BJT
R7828
NO STUFF
402
10
MF-LF
1/16W
5%
R7872
MF-LF
S0PGOOD_BJT
150K
1%
1/16W
402
R7826
18
66
64
66
15K
5%
402
1/16W
MF-LF
R7850
15K
5%
402
1/16W
MF-LF
R7851
66
6 18 39 40 65
402
5%
MF-LF
1/16W
5.1K
R7811
402
CERM-X5R
6.3V
10%
0.47UF
C7810
60
43
402
MF-LF
1/16W
5%
100K
R7810
64
10K
5%
1/16W
MF-LF
402
R7883
2
1 402
1/16W
MF-LF
15K
5%
R7882
2
1 402
33K
5%
1/16W
MF-LF
R7881
2
1
1/16W
402
MF-LF
5%
22K
R7880
2
1
10%
6.3V
CERM-X5R
402
0.47UF
C7883
0.47UF
402
CERM-X5R
6.3V
10%
C7882
0.47UF
402
CERM-X5R
6.3V
10%
C7881
10%
6.3V
CERM-X5R
402
0.47UF
C7880
63
6 18 39 65
69
402
MF-LF
1/16W
5%
100K
R7879
62
5%
1/16W
MF-LF
402
10K
R7820
62
63
64
Power Sequencing
S5PGOOD_DLY
PM_SLP_S3_L
PM_SLP_S4_L
CHGR_VFRQ_GATE
P0V9S5_PGOOD
PM_SLP_S3_R_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
P1V5S0_EN
=PP3V3_S0_PWRCTL PP5V_S0
PP1V5_S0
PP3V3_S0
S0PGOOD_RST_L PP1V05_S0
PP3V3_S0_VMON
VOLTAGE=3.3V
CHGR_VFRQ
=PP3V42_G3H_CHGR
PP1V05_S0
PP1V5_S0
S0PGOOD_BJT
CPUVTTS0_PGOOD
MCPCORES0_PGOOD
P1V5S0_PGOOD
P5V3V3_PGOOD
PP3V3_S0
=PP3V3_S5_VMON
S0PGOOD_BJT_L
VMON_Q4_BASE
VMON_EMITTER
SMC_ADAPTER_EN
AP_PWR_EN
PM_SLP_S3_L
PM_WLAN_EN_L
AC_OR_S0_L
=DDRVTT_EN MCP_MEM_VDD_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
P3V3S0_EN
PM_SLP_S3_L
MAKE_BASE=TRUE
CPUVTTS0_EN =CPUVTTS0_EN
MCPCORES0_EN
MAKE_BASE=TRUE
=MCPCORES0_EN
MAKE_BASE=TRUE
P1V8S0_EN =P1V8S0_EN
=P1V5S0_EN
=P3V3S0_EN
=P5VS0_EN
=PBUSVSENS_EN
PM_SLP_S4_L
=P3V3S3_EN
=P5VS3_EN_L
=P0V9S5_EN
=DDRREG_EN
P3V3S5_EN_L
MAKE_BASE=TRUE
P0V9S5_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
P3V3S3_EN
SMC_PM_G2_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
RSMRST_PWRGD
MAKE_BASE=TRUE
P5VS3_EN_L
MAKE_BASE=TRUE
DDRREG_EN
=P3V3S5_EN_L
=P5V3V3_REG_EN
=USB_PWR_EN
PP3V3_S5
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_PWRCTL
VMON_Q2_BASE VMON_3V3_DIV
PM_SLP_RMGT_L
MAKE_BASE=TRUE
=P3V3ENET_EN
=P0V9ENET_EN
P1V2ENET_EN
MAKE_BASE=TRUE
=P1V2ENET_EN
=PP3V3_ENET_PWRCTL
VMON_Q3_BASE
ALL_SYS_PWRGD
MAKE_BASE=TRUE
MCPPLLLDO_PGOOD
65 OF 80
051-8563
A.13.0
78 OF 109
2
1
1 2
2
1
1 2
2
1
3
4
5
6
1
2
6
1
2
2
1
1
2
1
2
3
4 5
1 2
1 2
1
2
3
1
2
1
2
1
4
3
9 5
2
7
6
8
2
1
2
1
2
1
9 4
5
6 8
1
27
3
2
7
8
5
1
64
3
1
2
1
2
1 2
1 2
1 2
1
2
1 2
1 2
1
2
1
2
1
2
1 2
2
1
1
2
2
1
2
1
2
1
2
1
1
2
1
2
6 18 39 65 69
6 18 39 40 65
7 6 7
6 7 65 79
6 7 65 79
6 7 65
7 58
6 7 65
6 7 65 79
6 7 65 79
7
6 7 79
7 65
7 65
7
GND
VOUT
ON
VIN
IN
D
S G
D
S G
D
S
G
IN
IN
D
G S
D
G S
S
G
D
D
G S
IN
S
G
D
IN
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
Loading
Type
ID(max)
MOSFET
Rds(on)
N-Channel
Q7990
SI2312BDS
37 mOhm @2.5V
3.25 A @85C
0.9V ENET FET
Rds(on)
Loading
ID(max)
FDC638P
2.0 A @85C
Type P-Channel
35 mOhm @2.5V Rds(on)
MOSFET FDC606P
ID(max)
Q7930
2.7 A @85C
Loading
3.3V S0 FET
65 mOhm @2.5V
P-Channel Type
MOSFET
Q7910
3.3V S3 FET 3.3V ENET Switch
Loading
Part
Type
Rds(on)
Q7940
TPCP8102
P-Channel
14 mOhm @4.5V
U7980
18 mOhm Typ
TPS22924C
Load Switch
2 A
0.4 A (EDP)
50 mOhm Max
Loading
I(max)
R(on)
Type
Part
0.140 A (EDP)
0.606 A (EDP)
1.895 A (EDP)
1.675 A (EDP)
5V S0 FET
Q7910
CRITICAL
FDC638P_G
SM U7980
CRITICAL
CSP
TPS22924
C7980
10%
6.3V
CERM
402
1UF
65
Q7991
SOT563
SSM6N15FEAPE
R7992
69.8K
1%
1/16W
MF-LF
402
R7991
402
1%
MF-LF
1/16W
10K
Q7991
SOT563
SSM6N15FEAPE
R7990
402
5%
MF-LF
1/16W
100K
C7991
0.01UF
402
CERM
16V
10%
20%
C7990
0.1UF
402
CERM
10V
C7911
10%
16V
X5R
402
0.033UF
SOT23
SI2312BDS
Q7990
CRITICAL
R7910
47K
1/16W
MF-LF
5%
402
R7912
402
MF-LF
1/16W
5%
10K
C7930
10%
16V
CERM
402
0.01UF
C7931
10%
16V
X5R
402
0.033UF
R7930
47K
1/16W
MF-LF
5%
402
R7932
402
MF-LF
1/16W
5%
100K
65
65
SSM3K15FV
Q7903
SOD-VESM-HF
Q7905
SSM3K15FV
SOD-VESM-HF
Q7930
FDC606P_G
SOT-6
CRITICAL
C7940
10%
16V
CERM
402
0.01UF
C7941
10%
16V
X5R
402
0.033UF
C7910
10%
16V
CERM
402
0.01UF
R7940
47K
1/16W
MF-LF
5%
402
R7942
402
MF-LF
1/16W
5%
47K
Q7945
SOD-VESM-HF
SSM3K15FV
65
Q7940
CRITICAL
TPCP8102
23V1K-SM
65
Power FETs
=PP0V9_ENET_P0V9ENETFET
P3V3S3_SS
=P3V3ENET_EN
=PP3V3_ENET_FET
=P5VS0_EN
=P3V3S0_EN
=P3V3S3_EN
P3V3S3_EN_L
P3V3S0_EN_L
P5VS0_EN_L
=PP3V3_S5_P3V3S3FET
=PP3V3_S0_FET
=PP3V3_S5_P3V3S0FET
P3V3S0_SS
=PP5V_S0_FET
=PP5V_S3_P5VS0FET
P5VS0_SS
=PP3V3_S3_FET
P0V9ENET_SS
P0V9ENET_EN_L
=P0V9ENET_EN
=PP0V9_ENET_FET
P0V9ENET_EN_L_RC
79 OF 109
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051-8563
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5
6
2
1
4
3
C
1
A1
B1
C2
B2
A2
2
1
3
4 5
1
2
1 2
6
1 2
1 2
2
1
2
1
2
1
2
1
3
1 2
1
2
1 2
2
1
1 2
1
2
1
2
3
1 2
3
6
5
2
1
4
3
1 2
2
1
1 2
1 2
1
2
1
2
3
7
8
5
6
4
3
1
2
7
8 7
7
7
7
7
7
7
7
7
SYM_VER-1
NC
NC
NC
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED
ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
GND THRM
ON
VIN_1
VIN_2
VOUT_1
VOUT_2
PAD
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
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PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
LCD CONNECTOR
LED BKLT I/F
(LVDS DDC POWER)
LVDS CONNECTOR:518S0650
LVDS I/F
C9012
20%
6.3V
X5R
603
10UF
402
X5R
16V
0.1UF
C9011
10%
CRITICAL
L9008
0402-LF
120-OHM-0.3A-EMI
MF-LF
1K
402
R9014
1/16W
5%
402
X7R
10%
0.001UF
50V
C9015
402
50V
X7R
C9010
10%
0.001UF
CRITICAL
L9080
AMC2012-SM
90-OHM-200MA
0.1UF
X5R
16V
C9009
402
10%
402
X7R
50V
10%
0.001UF
C9020
20474-030E-11
J9000
F-RT-SM
CRITICAL
MFET-2X2-8IN
U9000
CRITICAL
FPF1009
100K
R9009
402
1/16W
MF-LF
5%
402
100K
MF-LF
R9008
5%
1/16W
FERR-120-OHM-1.5A
L9004
0402-LF
LVDS CONNECTOR
SYNC_MASTER=K24_MLB
LCD_IG_PWR_EN
=PP3V3_S5_LCD
VOLTAGE=3.3V
PP3V3_LCDVDD_SW
LVDS_DDC_DATA
LVDS_DDC_CLK
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
PPVOUT_SW_LCDBKLT
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
BKL_VSYNC
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
=PP3V3_S0_LCD
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_6
LED_RETURN_4
LED_RETURN_5
PP3V3_S0_LCD_F
MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM
90 OF 109
A.13.0
051-8563
67 OF 80
2
1
2
1
2 1
1
2
2
1
2
1
4
3 2
1
2
1
2
1
30
29
28
27
26
25
24
23
21
11
16
9
10
6
5
31
33
34
12
13
20
22
17
19
18
8
7
15
14
4
3
2
1
32
6 7
1
2
3
4
5
1
2
1
2
2 1
16
7
6 8
6 8
6 79
6 79
6 70
8 74
8 74
6 8 74
6 8 74
6 8 74
6 8 74
6 70
6 8 74
6 8 74
7
6 70
70
70
6 70
6 70
6 70
6
6
IN
D
G
S
D
G
S
D
G
S
D
G
S
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
SHEET
PAGE TITLE
C
A
D
2 1
Apple Inc.
PAGE
A
B
C
3 4 5 6 7 8
D
B
8 7 5 4 2 1
376S0857
376S0857
402
X5R
10%
0.1UF
C9300
16V
C9301
402
X5R
10%
0.1UF
16V
8
SIGNAL_MODEL=DP_AUXCH_FET
Q9300
SSM6N16FE
SOT563
OMIT
Q9300
SSM6N16FE
SOT563
OMIT
Q9302
SOT563
SSM6N16FE
OMIT
Q9302
SOT563
SSM6N16FE
OMIT
C9303
0.0033UF
CERM
402
10%
50V
2 Q9300,Q9302 CRITICAL 376S0859 XSTR,FT,N-CH,DUAL,SOT-563
DISPLAYPORT SUPPORT
DP_EXT_DDC_DATA
DP_EXT_DDC_CLK
DP_AUX_CH_C_P DP_IG_AUX_CH_P
DP_CA_DET
DP_IG_AUX_CH_N DP_AUX_CH_C_N
93 OF 109
A.13.0
051-8563
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1 2
1 2
5
4 3
2
16
2
16
5
4 3
8 8 74
8 74 8
OUT
BI
IN
IN
IO
NC NC
IO
G
N
D
OUT
IO
NC NC
IO
G
N
D
IO
NC NC
IO
G
N
D
IO
NC NC
IO
G
N
D
IN
IN
IN
IN
IN
IN
G
D
S
G
D
S
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
G
D
S
G
D
S
BI
IN
IN
OC*
OUT
EN
GND
GND
GND
ML_LANE0N
ML_LANE0P
ML_LANE1P
GND
ML_LANE1N
GND
GND
DP_PWR
ML_LANE2P AUX_CHP
RETURN
HOT_PLUG_DETECT
AUX_CHN
ML_LANE3P
ML_LANE3N
ML_LANE2N
CONFIG1
CONFIG2
BOT ROW TOP ROW
TH PINS SM PINS
SHIELD PINS
3 6
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
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Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
Port Power Switch
down HPD input with
514-0637
Cable Adapter
DP to DVI/HDMI
DP Source must pull
greater than or equal
to 100K (DPv1.1a).
(CA) has 100k
pull-up to DP_PWR.
DP_EXT_ML_F_P<0>
8
8 79
8 79
8 79
R9421
402
5%
1/16W
100K
MF-LF
RCLAMP0524P
SLP2510P8
DP_ESD
3
D9411
CRITICAL
C9415
402 10% X5R
0.1uF
16V
16V
0.1uF
X5R 10% 402
C9414
8
C9411
X5R
0.1uF
402 16V 10%
C9410
0.1uF
X5R 402 10% 16V
402
R9420
100K
5%
1/16W
MF-LF
RCLAMP0524P
SLP2510P8
3
D9410
CRITICAL
DP_ESD
CRITICAL
D9400
RCLAMP0504F
DP_ESD
SC70-6-1
2 5
RCLAMP0524P
D9411
DP_ESD
SLP2510P8
3
CRITICAL
402
MF-LF
5%
1/16W
1M
R9425
DP_ESD
SLP2510P8
CRITICAL
3
RCLAMP0524P
D9410
402 X5R
C9417
0.1uF
10% 16V
C9416
402 16V
0.1uF
X5R 10%
0.1uF
C9413
X5R 402 10% 16V
0.1uF
C9412
10% X5R 402 16V
8 79
8 79
8 79
8 79
C9400
402
20%
16V
CERM
0.01UF
0603
FERR-120-OHM-3A
L9400
5%
MF-LF
1/16W
402
R9423
100K
8 79
8 79
SOT-363
2N7002DW-X-G
Q9440
2N7002DW-X-G
Q9440
SOT-363
100K
5%
MF-LF
402
1/16W
R9443
MF-LF
5%
402
1/16W
R9442
100K
FL9401
12-OHM-100MA
TCM1210-4SM
TCM1210-4SM
12-OHM-100MA
FL9402
12-OHM-100MA
FL9400
TCM1210-4SM
FL9403
12-OHM-100MA
TCM1210-4SM
10K
R9444
MF-LF
5%
402
1/16W
10K
MF-LF
402
1/16W
5%
R9445
Q9441
2N7002DW-X-G
SOT-363
R9422
1M
5%
402
1/16W
MF-LF
Q9441
2N7002DW-X-G
SOT-363
CERM
20%
10V
C9481
0.1UF
402
8 79
6 18 39 65
U9480
CRITICAL
SOT23
TPS2051B
CRITICAL
J9400
DSPLYPRT-M97-1
F-RT-THSM
CRITICAL
6.3V
POLY-TANT
100UF
C9487
CASE-B2-SM
20%
C9485
0.1UF
10V
CERM
20%
402
C9480
X5R-CERM-1
CRITICAL
6.3V
22UF
603
20%
603
X5R
6.3V
20%
10UF
C9486
DisplayPort Connector
DP_EXT_AUX_CH_C_P
DP_EXT_AUX_CH_C_N
DP_EXT_ML_F_P<0>
DP_CA_DET_Q
DP_EXT_ML_F_N<0>
DP_EXT_ML_F_P<1>
DP_EXT_ML_F_N<1>
VOLTAGE=3.3V
PP3V3_S0_DPPWR
DP_EXT_ML_F_P<2>
DP_HPD_Q
DP_EXT_ML_F_P<3>
DP_EXT_ML_F_N<3>
DP_EXT_ML_F_N<2>
HDMI_CEC
DP_EXT_ML_C_P<2>
DP_EXT_ML_C_N<2>
TP_DPPWR_OC_L PM_SLP_S3_L
DP_HPD_Q_L
DP_EXT_ML_C_N<0>
DP_EXT_ML_C_P<3>
DP_EXT_ML_C_N<3>
DP_EXT_ML_P<0>
DP_EXT_ML_N<0>
DP_EXT_ML_P<1>
DP_EXT_ML_N<1>
DP_EXT_ML_P<2>
DP_EXT_ML_N<2>
DP_EXT_ML_P<3>
DP_EXT_ML_C_P<0>
=PP3V3_S5_DP_PORT_PWR
DP_CA_DET_Q_L
DP_EXT_ML_N<3>
DP_EXT_CA_DET
DP_EXT_HPD
=PP5VR3V3_S0_DPCADET
=PP3V3_S0_DPCONN
=PP3V3_S0_DPCONN
VOLTAGE=3.3V
PP3V3_S0_DPILIM
DP_EXT_ML_C_P<1>
DP_EXT_ML_C_N<1>
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4
4
7
5
6
1
2
1
10
2
9
1 2
1 2
1 2
1 2
2
1
2 1
1
2
3
5
4
6
2
1
1
2
1
2
4
3 2
1
4
3 2
1
4
3 2
1
4
3 2
1
1
2
1
2
3
5
4
1
2
6
2
1
2
1
5
3
1
2
4
22
1
7
5
3
9
13
11
8
14
21
20
15 16
19
2
18
10
12
17
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1
2 2
1
2
1
2
1
79
79
79
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79
79
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79
79
79
79
79
79
79
7
7
7 69
7 69
79
79
OUT
OUT
OUT
OUT
OUT
OUT
NC
OUT1
FSET
GD
FILTER
ISET
PWM
EN
FAULT
THRM
G
N
D
_
L
G
N
D
_
S
W
OUT6
VIN VDDIO VLDO
FB
SW
OUT2
OUT4
OUT5
VSYNC
OUT3 SCLK
SDA
G
N
D
_
S
PAD
IN
IN
BI
IN
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Fpwm=9.62kHz
see spec for others
measurement on LED strings.
10.2 ohm resistors for current
NO STUFF R9740, C9740, C9741, R9754
I_LED=610*1.23/Riset
STUFF R9741
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
(EEPROM should set EN_I_RES=1)
FOR LP8543:
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
I_LED=23.2mA
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
10K
402
5%
MF-LF
1/16W
R9755
402
MF-LF
1/16W
5%
R9741
10K
50V
10%
X5R
1210
C9799
OMIT
10UF
X5R
10UF
10%
1210
50V
OMIT
C9797
1UF
C9741
10%
NO STUFF
402
X5R
6.3V
CRITICAL
L9701
33UH-1.8A-110MOHM
1217AS-2SM
C9740
6.3V
20%
X5R
NO STUFF
10UF
603
R9704
1/16W
MF-LF
402
5%
33
1/16W
5%
R9757
0
MF-LF
402
CRITICAL
25V
10%
X5R
805
C9712
10UF
C9713
0.1UF
X5R
402
10%
25V
402
50V
10%
X7R-CERM
220PF
C9796
BOOST_VOL:HI
D9701
CRITICAL
RB160M-60G
SOD-123
R9722
0
1/16W
MF-LF
5%
402
BKLT:PROD
R9721
0
1/16W
MF-LF
5%
402
BKLT:PROD
R9720
402
5%
MF-LF
1/16W
0
BKLT:PROD
6 67
6 67
MF-LF
5%
1/16W
0
402
R9753
6 67
67
67
6 67
R9718
0
5%
MF-LF
402
1/16W
BKLT:PROD
R9719
BKLT:PROD
1/16W
MF-LF
402
5%
0
R9717
0
1/16W
5%
402
MF-LF
BKLT:PROD
100K
1
2
402
1%
1/16W
MF-LF
R9715 402
R9731
301K
MF-LF
1%
1/16W NO STUFF
25V
402
X5R
0.1UF
C9723
10%
X5R
25V
1UF
10%
C9710
603-1
C9711
16V
10%
0.1UF
X5R
402
XW9710
SM
CRITICAL
OMIT
L
P
8
5
4
5
S
Q
X
LLP
U9701
16V
CERM
402
10%
0.01UF
C9714
R9703
NO STUFF
5%
1/16W
MF-LF
0
402
1/16W
R9702
0
5%
402
MF-LF
8
33PF
C9704
CERM
5%
402
50V
402
MF-LF
1/16W
1%
R9714
16.2K
R9701
MF-LF
5%
1/16W
0
402
42
42
NO STUFF
1/16W
MF-LF
402
1%
R9740
47.0K
402
R9716
1%
90.9K
1/16W
MF-LF
6 67
NO STUFF
R9754
0
402
MF-LF
1/16W
5%
BKLT:ENG 103S0198 3 R9720,R9721,R9722 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
138S0673 CRITICAL C9797,C9799 CAP, 50V, 1210, X5R, 10UF+/-10% 2
BOOST_VOL:LOW 1 371S0580 SCHOTTKY BARRIER DIODE RB160M-40 D9701
R9717,R9718,R9719 103S0198 BKLT:ENG 3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
LCD Backlight Driver
=PP3V3_S0_BKL_VDDIO
BKL_FLTR_R
PPVOUT_SW_LCDBKLT
VOLTAGE=50V
BKL_ISET
PPBUS_SW_LCDBKLT_PWR_SW
DIDT=TRUE
VOLTAGE=50V
SWITCH_NODE=TRUE
TP_BKL_FAULT
BKL_VSYNC
BKL_VSYNC_R
=PP5V_S0_BKL
=I2C_BKL_1_SDA
BKL_ISEN5
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
VOLTAGE=5V
PPVIN_SW_BKL_R
=I2C_BKL_1_SCL
BKL_ISEN4
BKL_ISEN2
BKL_ISEN1
BKL_ISEN3
=PPBUS_SW_BKL
BKL_FLTR
GND_BKL_SGND
VOLTAGE=0V
VOLTAGE=5V
PP5V_S0_BKL_VLDO
BKL_FSET
BKL_EN
BKL_PWM
LCD_BKLT_PWM
BKL_ISEN6
BKL_SCL
BKL_SDA
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1 2
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1
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1
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1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
2
1
2
1
1 2
12
5
6
20
3
2
4
7
2
5
1
5 1
18
2
3
82
2
21
24
13
16
17
19
14 10
11
9
2
1
1
2
1
2
2
1
1
2
1 2
1 2
1
2
1
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7
6 67
8 71
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IN
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P-TYPE
43 mOhm @4.5V
MOSFET
CHANNEL
RDS(ON)
LOADING
FDC638APZ
PPBUS S0 LCDBkLT FET
0.65 A (EDP)
F9800
2AMP-32V
0402-HF
R9808
402
MF-LF
1/16W
1%
301K
R9809
402
MF-LF
1/16W
1%
147K
C9802
0.1UF
402
X5R
16V
10%
SSOT6-HF
Q9806
FDC638APZ_SBMS001
CRITICAL
24
Q9807
SOT563
SSM6N15FEAPE
Q9807
SSM6N15FEAPE
SOT563
8
LCD Backlight Support
LCD_BKLT_EN
=PPBUS_S0_LCDBKLT
BKLT_PLT_RST_L
LCDBKLT_EN_DIV
LCDBKLT_DISABLE
LCDBKLT_EN_L
VOLTAGE=12.6V
PPBUS_S0_LCDBKLT_FUSED
VOLTAGE=12.6V
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TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING LAYER SPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH ALLOW ROUTE
ON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
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All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
FSB 2X signals / groups shown in signal table on right.
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
FSB Clock Constraints
CPU Signal Constraints
MCP FSB COMP Signal Constraints
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
Some signals require 27.4-ohm single-ended impedance.
Most CPU signals with impedance requirements are 55-ohm single-ended.
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1
SR DG recommends at least 25 mils, >50 mils preferred
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
FSB (Front-Side Bus) Constraints
PHYSICAL
F
S
B

4
X

S
i
g
n
a
l

G
r
o
u
p
s
ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
S
i
g
n
a
l
s
Signals within each 4x group should be matched within 5 ps of strobe.
F
S
B

2
X
F
S
B

1
X

S
i
g
n
a
l
s
CPU / FSB Net Properties
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
(See above)
(FSB_CPURST_L)
(CPU_VCCSENSE)
(CPU_VCCSENSE) SYNC_DATE=08/03/2009 SYNC_MASTER=T27_MLB
CPU/FSB Constraints
=2x_DIELECTRIC * ? FSB_ADSTB
* ? FSB_1X =STANDARD
=3x_DIELECTRIC * FSB_DSTB ?
=2x_DIELECTRIC ? * FSB_DATA
=3x_DIELECTRIC ? TOP,BOTTOM FSB_1X
=3x_DIELECTRIC ? TOP,BOTTOM FSB_ADDR
=5x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM
=4x_DIELECTRIC FSB_DATA ? TOP,BOTTOM
=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE FSB_50S =STANDARD =STANDARD *
=4x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM
=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE FSB_DSTB_50S * =1:1_DIFFPAIR =1:1_DIFFPAIR
CPU_AGTL ? TOP,BOTTOM =2x_DIELECTRIC
=4x_DIELECTRIC CLK_FSB ? TOP,BOTTOM
=27P4_OHM_SE =27P4_OHM_SE * =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL CPU_27P4S
=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE CPU_50S * =STANDARD =STANDARD
8 MIL CPU_8MIL ? *
? CPU_COMP * 25 MIL
CPU_AGTL ? * =STANDARD
25 MIL CPU_GTLREF * ?
25 MIL * CPU_VCCSENSE ?
MCP_50S =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE * =STANDARD =STANDARD
=3x_DIELECTRIC ? CLK_FSB *
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF * CLK_FSB_100D
8 MIL * ? MCP_FSB_COMP
CPU_ITP * ? =2:1_SPACING
? FSB_ADDR * =STANDARD
CPU_50S CPU_AGTL CPU_STPCLK_L CPU_ASYNC
CPU_50S PM_THRMTRIP_L CPU_8MIL PM_THRMTRIP_L
FSB_CLK_ITP CLK_FSB FSB_CLK_ITP_P CLK_FSB_100D
CPU_50S XDP_TRST_L CPU_ITP XDP_TRST_L
MCP_50S MCP_CPU_COMP_GND MCP_CPU_COMP MCP_FSB_COMP
MCP_50S MCP_CPU_COMP_VCC MCP_CPU_COMP MCP_FSB_COMP
MCP_50S MCP_BCLK_VML_COMP_GND MCP_CPU_COMP MCP_FSB_COMP
MCP_50S MCP_BCLK_VML_COMP_VDD MCP_CPU_COMP MCP_FSB_COMP
CPU_VCCSENSE IMVP6_VSEN_N CPU_27P4S
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P
CPU_50S IMVP6_VID<6..0> CPU_8MIL
CPU_50S CPU_VID<6..0> CPU_8MIL
CPU_50S XDP_BPM_L5 CPU_ITP XDP_BPM_L<5>
CPU_50S XDP_CPURST_L CPU_ITP
CPU_50S XDP_BPM_L XDP_BPM_L<4..0> CPU_ITP
CPU_50S XDP_TCK CPU_ITP XDP_TCK
CPU_50S XDP_TDO CPU_ITP XDP_TDO
CPU_50S XDP_TMS CPU_ITP XDP_TMS
CPU_COMP CPU_COMP CPU_27P4S CPU_COMP<0>
CPU_50S CPU_COMP CPU_COMP<1> CPU_COMP
CPU_COMP CPU_COMP<2> CPU_27P4S CPU_COMP
CPU_50S CPU_COMP CPU_COMP<3> CPU_COMP
CPU_50S CPU_GTLREF CPU_GTLREF CPU_GTLREF
CPU_50S CPU_AGTL IMVP_DPRSLPVR
CPU_50S PM_DPRSLPVR CPU_AGTL PM_DPRSLPVR
CPU_50S CPU_IERR_L CPU_IERR_L
FSB_CLK_MCP CLK_FSB CLK_FSB_100D FSB_CLK_MCP_N
FSB_CLK_MCP CLK_FSB CLK_FSB_100D FSB_CLK_MCP_P
FSB_CLK_CPU FSB_CLK_CPU_N CLK_FSB CLK_FSB_100D
FSB_CLK_CPU FSB_CLK_CPU_P CLK_FSB CLK_FSB_100D
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N
FSB_50S FSB_1X FSB_HIT_L FSB_1X
FSB_50S FSB_HITM_L FSB_1X FSB_1X
CPU_50S CPU_AGTL CPU_IGNNE_L CPU_ASYNC
CPU_50S CPU_INIT_L CPU_INIT_L CPU_AGTL
CPU_50S CPU_INTR CPU_ASYNC_R CPU_AGTL
CPU_50S CPU_AGTL CPU_DPRSTP_L CPU_DPRSTP_L
CPU_50S CPU_AGTL CPU_DPSLP_L CPU_FROM_SB
CPU_50S CPU_SMI_L CPU_ASYNC CPU_AGTL
CPU_50S CPU_AGTL CPU_PWRGD CPU_PWRGD
CPU_50S CPU_PROCHOT_L CPU_PROCHOT_L CPU_AGTL
CPU_50S CPU_NMI CPU_ASYNC_R CPU_AGTL
CPU_50S CPU_FERR_L CPU_FERR_L CPU_8MIL
CPU_50S CPU_AGTL CPU_BSEL<2..0> CPU_BSEL
CPU_50S CPU_AGTL CPU_A20M_L CPU_ASYNC
FSB_50S FSB_TRDY_L FSB_1X FSB_1X
FSB_50S FSB_1X FSB_RS_L<2..0> FSB_1X
FSB_50S FSB_1X FSB_CPURST_L FSB_CPURST_L
FSB_50S FSB_LOCK_L FSB_1X FSB_1X
FSB_50S FSB_1X FSB_DRDY_L FSB_1X
FSB_50S FSB_1X FSB_DEFER_L FSB_1X
FSB_50S FSB_1X FSB_DBSY_L FSB_1X
FSB_50S FSB_BPRI_L FSB_1X FSB_1X
FSB_50S FSB_BNR_L FSB_1X FSB_1X
FSB_50S FSB_ADDR_GROUP1 FSB_ADDR FSB_A_L<35..17>
FSB_DSTB_50S FSB_DSTB0 FSB_DSTB_L_P<0> FSB_DSTB
FSB_50S FSB_DATA_GROUP0 FSB_D_L<15..0> FSB_DATA
FSB_DSTB_50S FSB_DSTB0 FSB_DSTB FSB_DSTB_L_N<0>
FSB_50S FSB_DATA_GROUP1 FSB_D_L<31..16> FSB_DATA
FSB_50S FSB_DATA_GROUP1 FSB_DINV_L<1> FSB_DATA
FSB_DSTB_50S FSB_DSTB1 FSB_DSTB FSB_DSTB_L_P<1>
FSB_DSTB_50S FSB_DSTB_L_P<2> FSB_DSTB FSB_DSTB2
FSB_DSTB_50S FSB_DSTB FSB_DSTB2 FSB_DSTB_L_N<2>
FSB_50S FSB_D_L<63..48> FSB_DATA_GROUP3 FSB_DATA
FSB_DSTB_50S FSB_DSTB_L_P<3> FSB_DSTB FSB_DSTB3
FSB_DSTB_50S FSB_DSTB FSB_DSTB3 FSB_DSTB_L_N<3>
FSB_50S FSB_ADDR FSB_ADDR_GROUP0 FSB_A_L<16..3>
FSB_50S FSB_ADDR_GROUP0 FSB_REQ_L<4..0> FSB_ADDR
FSB_50S FSB_ADSTB FSB_ADSTB_L<1> FSB_ADSTB1
FSB_50S FSB_ADS_L FSB_1X FSB_1X
FSB_50S FSB_BREQ0_L FSB_BREQ0_L FSB_1X
FSB_50S FSB_ADSTB FSB_ADSTB_L<0> FSB_ADSTB0
FSB_DSTB_50S FSB_DSTB_L_N<1> FSB_DSTB FSB_DSTB1
FSB_50S FSB_DATA_GROUP2 FSB_DATA FSB_D_L<47..32>
CPU_50S XDP_TDI CPU_ITP XDP_TDI
CPU_50S CPU_AGTL FSB_DPWR_L CPU_ASYNC
CPU_50S CPU_AGTL FSB_CPUSLP_L FSB_CPUSLP_L
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9 13
9 13 40
12 13
9 12
13
13
13
13
10 61
10 61
10 61
9 12
12
9 12
9 12
9 12
9 12
9
9
9
9
9 28
61
13 61
9
13
13
9 13
9 13
12 13
6 9 13
6 9 13
9 13
9 13
9 13
9 13 61
9 13
9 13
9 12 13
9 13 40 61
9 13
9 13
8 9
9 13
9 13
9 13
9 12 13
6 9 13
9 13
9 13
9 13
9 13
9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
6 9 13
9 13
6 9 13
6 9 13
6 9 13
6 9 13
9 12
9 13
9 13
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
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3 4 5 6 7 8
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8 7 5 4 2 1
Memory Bus Constraints
PHYSICAL SPACING
NET_TYPE
NV DG says 3x inner, 4x outer
Need to support MEM_*-style wildcards!
DQ signals should be matched within 5 ps of associated DQS pair.
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
All memory signals maximum length is 1.030 ps.
CMD/CTRL signals should be matched within 150 ps.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps
Memory Bus Spacing Group Assignments
DDR3:
ELECTRICAL_CONSTRAINT_SET
Memory Net Properties
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MCP MEM COMP Signal Constraints
MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
MEM_DATA * * MEM_2OTHER
MEM_2OTHER MEM_CMD * *
Memory Constraints
MEM_DATA MEM_DATA MEM_DATA2DATA *
MEM_DATA2MEM MEM_DATA * MEM_DQS MEM_CTRL MEM_CTRL2MEM MEM_DQS *
MEM_CTRL MEM_CTRL2MEM MEM_CLK *
MEM_CTRL MEM_CTRL2CTRL MEM_CTRL *
MEM_CTRL MEM_DATA MEM_CTRL2MEM *
MEM_DQS MEM_CLK * MEM_DQS2MEM
MEM_CTRL * MEM_DQS2MEM MEM_DQS
MEM_CMD MEM_DQS MEM_DQS2MEM *
* MEM_CMD MEM_CMD MEM_CMD2CMD
=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD * MCP_MEM_COMP
? * MCP_MEM_COMP =2x_DIELECTRIC
MEM_DQS MEM_DQS MEM_DQS2MEM *
MEM_DATA * MEM_DQS2MEM MEM_DQS
MEM_CTRL MEM_CMD * MEM_CTRL2MEM
MEM_DQS MEM_CLK2MEM MEM_CLK *
MEM_DATA * MEM_CLK MEM_CLK2MEM
MEM_CLK MEM_CLK MEM_CLK2MEM *
MEM_CLK MEM_CTRL MEM_CLK2MEM *
MEM_CMD MEM_CLK2MEM MEM_CLK *
25 MIL MEM_2OTHER * ?
MEM_2OTHER MEM_DQS * *
MEM_2OTHER MEM_CTRL * *
MEM_2OTHER MEM_CLK * *
MEM_DATA * MEM_DATA2MEM MEM_CTRL
MEM_DATA2MEM MEM_DATA * MEM_CMD
* MEM_DATA2MEM MEM_DATA MEM_CLK
MEM_CMD2MEM MEM_CMD * MEM_DQS
* MEM_CMD MEM_CMD2MEM MEM_DATA
* MEM_CMD MEM_CMD2MEM MEM_CTRL
MEM_CMD * MEM_CMD2MEM MEM_CLK
MEM_CTRL2MEM * ? =2.5:1_SPACING
=1.5:1_SPACING MEM_CMD2CMD * ?
MEM_DATA2DATA * ? =1.5:1_SPACING
MEM_CMD2MEM * ? =3:1_SPACING
MEM_DATA2MEM =3:1_SPACING * ?
? =3:1_SPACING MEM_DQS2MEM *
MEM_CTRL2CTRL =2:1_SPACING * ?
MEM_CLK2MEM * ? =4:1_SPACING
MEM_40S =STANDARD * =STANDARD =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE
=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF * =70_OHM_DIFF =70_OHM_DIFF MEM_70D
MEM_A_DQS0 MEM_A_DQS_P<0> MEM_70D MEM_DQS
MEM_40S MEM_A_DQ_BYTE7 MEM_A_DM<7> MEM_DATA
MEM_40S MEM_B_A<15..0> MEM_CMD MEM_B_CMD
MEM_40S MEM_CMD MEM_B_RAS_L MEM_B_CMD
MEM_40S MEM_CMD MEM_B_CAS_L MEM_B_CMD
MCP_MEM_COMP_GND MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMP_VDD MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
MEM_40S MEM_CTRL MEM_B_CNTL MEM_B_ODT<3..0>
MEM_DATA MEM_40S MEM_B_DM<1> MEM_B_DQ_BYTE1
MEM_DQS MEM_70D MEM_B_DQS_N<7> MEM_B_DQS7
MEM_DQS MEM_70D MEM_B_DQS_P<3> MEM_B_DQS3
MEM_DQS MEM_B_DQS_N<4> MEM_70D MEM_B_DQS4
MEM_40S MEM_CMD MEM_B_BA<2..0> MEM_B_CMD
MEM_DATA MEM_40S MEM_B_DQ<7..0> MEM_B_DQ_BYTE0
MEM_40S MEM_CMD MEM_B_WE_L MEM_B_CMD
MEM_DATA MEM_B_DQ<39..32> MEM_40S MEM_B_DQ_BYTE4
MEM_A_DQS6 MEM_DQS MEM_A_DQS_P<6> MEM_70D
MEM_70D MEM_DQS MEM_A_DQS_N<5> MEM_A_DQS5
MEM_70D MEM_DQS MEM_A_DQS_N<3> MEM_A_DQS3
MEM_70D MEM_DQS MEM_A_DQS_P<4> MEM_A_DQS4
MEM_A_DQS2 MEM_DQS MEM_A_DQS_N<2> MEM_70D
MEM_DQS MEM_A_DQS1 MEM_A_DQS_P<1> MEM_70D
MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1>
MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0>
MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DM<5>
MEM_A_DQ_BYTE3 MEM_40S MEM_A_DM<3> MEM_DATA
MEM_70D MEM_CLK MEM_A_CLK MEM_A_CLK_N<5..0>
MEM_70D MEM_CLK MEM_A_CLK MEM_A_CLK_P<5..0>
MEM_B_CLK MEM_70D MEM_B_CLK_P<5..0> MEM_CLK
MEM_A_DQS7 MEM_A_DQS_N<7> MEM_DQS MEM_70D
MEM_DQS MEM_B_DQS_N<0> MEM_B_DQS0 MEM_70D
MEM_DQS MEM_70D MEM_B_DQS0 MEM_B_DQS_P<0>
MEM_A_DQ_BYTE1 MEM_DATA MEM_40S MEM_A_DQ<15..8>
MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ<39..32>
MEM_A_DQ_BYTE0 MEM_40S MEM_A_DQ<7..0> MEM_DATA
MEM_A_CMD MEM_40S MEM_A_WE_L MEM_CMD
MEM_A_CMD MEM_40S MEM_CMD MEM_A_CAS_L
MEM_A_CMD MEM_40S MEM_A_A<15..0> MEM_CMD
MEM_A_CNTL MEM_40S MEM_A_ODT<3..0> MEM_CTRL
MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS_P<3>
MEM_B_CNTL MEM_40S MEM_CTRL MEM_B_CS_L<3..0>
MEM_B_CLK MEM_70D MEM_B_CLK_N<5..0> MEM_CLK
MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS_P<7>
MEM_40S MEM_A_DQ_BYTE6 MEM_A_DM<6> MEM_DATA
MEM_A_DQ_BYTE2 MEM_DATA MEM_40S MEM_A_DQ<23..16>
MEM_A_CMD MEM_40S MEM_CMD MEM_A_RAS_L
MEM_A_CMD MEM_40S MEM_CMD MEM_A_BA<2..0>
MEM_A_CNTL MEM_40S MEM_A_CS_L<3..0> MEM_CTRL
MEM_A_CKE MEM_40S MEM_CTRL MEM_A_CKE<3..0>
MEM_B_CKE MEM_40S MEM_CTRL MEM_B_CKE<3..0>
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14 27
14 27
14 26
14 26
14 26
14
14
14 26
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 26
14 27
14 27
14 27
14 27
14 27
14 26
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 25
14 25
14 26
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 25
14 25
14 25
14 25
14 27
14 27
14 27
14 26
14 26
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 27
14 25
14 25
14 25
14 20 25
14 20 26
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DRAWING NUMBER SIZE
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PCI-Express
PHYSICAL SPACING
NET_TYPE NET_TYPE
MCP89 Net Properties
Analog Video Signal Constraints
- 75-ohm from output of three-pole filter to connector (if possible).
- 37.5-ohm from MCP to first termination resistor.
Digital Video Signal Constraints
NEED PCIe Gen1/Gen2 notes!
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.
- 50-ohm from first to second termination resistor.
CRT signal single-ended impedence varies by location:
R/G/B signals should be matched as close as possible and < 10 inches.
SATA Interface Constraints
LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.
NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm.
SATA intra-pair matching should be 1 ps.
DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max trace length: LVDS 10 inches, DP 8.5 inches.
Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3.
DP_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF *
* Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD MCP_DV_COMP
=3x_DIELECTRIC * ? DISPLAYPORT
* SATA_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
? SATA * =3x_DIELECTRIC
* ? SATA_TERMP 8 MIL
SATA ? TOP,BOTTOM =4x_DIELECTRIC
=100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
? * LVDS =3x_DIELECTRIC
* ? CRT_2SWITCHER 250 MIL
CRT_SYNC ? * =4x_DIELECTRIC
MCP_DAC_COMP * ? =2x_DIELECTRIC
? * CRT_2CLK 50 MIL
CRT_2CRT ? * 15 MIL
? LVDS =4x_DIELECTRIC TOP,BOTTOM
TOP,BOTTOM =4x_DIELECTRIC ? DISPLAYPORT
CRT * ? 20 MIL
CRT_50S =50_OHM_SE =STANDARD * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
CRT_2CRT * CRT CRT
MCP Constraints 1
=100_OHM_DIFF =100_OHM_DIFF CLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF * =100_OHM_DIFF
PCIE =3X_DIELECTRIC ? *
8 MIL MCP_PEX_COMP ? *
20 MIL CLK_PCIE ? *
PCIE ? TOP,BOTTOM =4X_DIELECTRIC
PCIE_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF * =90_OHM_DIFF =90_OHM_DIFF
PCIE_90D PCIE PEG_R2D_P<15..0>
PEG_R2D_N<15..0> PCIE_90D PCIE
PCIE_AP_R2D_C_N PCIE PCIE_90D
PCIE_AP_D2R_P PCIE_AP_D2R PCIE PCIE_90D
PCIE PCIE_90D PCIE_AP_D2R_N
PCIE_CLK100M_AP_P CLK_PCIE CLK_PCIE_100D MCP_PE1_REFCLK
PCIE_FW_R2D_N PCIE PCIE_90D
PCIE PCIE_90D PCIE_ENET_R2D_C_P PCIE_ENET_R2D
CLK_PCIE PCIE_CLK100M_FW_P CLK_PCIE_100D MCP_PE3_REFCLK
LVDS_IG_A_DATA LVDS_100D LVDS_IG_A_DATA_P<2..0> LVDS
LVDS_IG_A_DATA_N<3> LVDS LVDS_IG_A_DATA3 LVDS_100D
LVDS_100D LVDS_IG_A_DATA3 LVDS_IG_A_DATA_P<3> LVDS
MCP_PEX_COMP MCP_PEX0_TERMP MCP_PEX_CLK_COMP
LVDS_100D LVDS_IG_B_DATA LVDS LVDS_IG_B_DATA_N<2..0>
MCP_IFPAB_RSET MCP_IFPAB_RSET MCP_DV_COMP
PCIE PCIE_90D PCIE_AP_R2D_P
PCIE_90D PCIE PEG_R2D_C_N<15..0>
PCIE_AP_R2D_N PCIE PCIE_90D
PEG_D2R_P<15..0> PCIE_90D PCIE PEG_D2R
PEG_R2D_C_P<15..0> PCIE_90D PCIE PEG_R2D
PEG_D2R_C_P<15..0> PCIE PCIE_90D
PCIE PCIE_90D PCIE_ENET_R2D_C_N
PCIE PCIE_90D PCIE_ENET_R2D_P
PCIE PCIE_90D PCIE_ENET_D2R_P PCIE_ENET_D2R
PCIE PCIE_90D PCIE_ENET_R2D_N
DP_90D TMDS_IG_TXD DISPLAYPORT TMDS_IG_TXD_N<5..0>
DP_90D DISPLAYPORT DP_IG_AUX_CH_P DP_EXT_AUX_CH
MCP_TMDS0_VPROBE MCP_TMDS0_VPROBE
LVDS_100D LVDS_IG_A_CLK LVDS_IG_A_CLK_P LVDS
LVDS_IG_A_CLK_N LVDS LVDS_100D LVDS_IG_A_CLK
LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA LVDS_100D LVDS
LVDS LVDS_IG_B_CLK LVDS_IG_B_CLK_P LVDS_100D
LVDS_IG_B_CLK_N LVDS LVDS_100D LVDS_IG_B_CLK
LVDS LVDS_100D LVDS_IG_B_DATA LVDS_IG_B_DATA_P<2..0>
LVDS LVDS_100D LVDS_IG_B_DATA3 LVDS_IG_B_DATA_P<3>
LVDS LVDS_100D LVDS_IG_B_DATA3 LVDS_IG_B_DATA_N<3>
MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE
SATA_HDD_R2D_C_P SATA SATA_HDD_R2D SATA_90D
SATA SATA_HDD_R2D_C_N SATA_90D
SATA_HDD_R2D_P SATA SATA_90D
SATA SATA_HDD_R2D_N SATA_90D
SATA SATA_HDD_D2R_N SATA_90D
SATA SATA_HDD_D2R_P SATA_HDD_D2R SATA_90D
SATA SATA_HDD_D2R_C_P SATA_90D
SATA SATA_HDD_D2R_C_N SATA_90D
SATA_ODD_R2D_C_P SATA SATA_ODD_R2D SATA_90D
SATA SATA_ODD_R2D_P SATA_90D
SATA SATA_ODD_R2D_C_N SATA_90D
SATA SATA_ODD_R2D_N SATA_90D
SATA_ODD_D2R_P SATA SATA_ODD_D2R SATA_90D
SATA SATA_ODD_D2R_N SATA_90D
SATA_ODD_D2R_C_N SATA SATA_90D
SATA SATA_ODD_D2R_C_P SATA_90D
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP
PCIE_AP_R2D_C_P PCIE_AP_R2D PCIE_90D PCIE
PEG_D2R_C_N<15..0> PCIE PCIE_90D
PCIE_90D PCIE PEG_D2R_N<15..0>
PCIE_FW_D2R_C_P PCIE PCIE_90D
PCIE_CLK100M_FW_N CLK_PCIE_100D CLK_PCIE
DP_90D DISPLAYPORT TMDS_IG_TXD_P<5..0> TMDS_IG_TXD
DP_90D DISPLAYPORT TMDS_IG_TXC_N TMDS_IG_TXC
DP_90D TMDS_IG_TXC_P DISPLAYPORT TMDS_IG_TXC
MCP_TMDS0_RSET MCP_TMDS0_RSET MCP_DV_COMP
DP_90D DP_IG_AUX_CH_N DISPLAYPORT DP_EXT_AUX_CH
DP_90D DP_IG_ML_N<3..0> DISPLAYPORT DP_EXT_ML
DP_90D DP_IG_ML_P<3..0> DISPLAYPORT DP_EXT_ML
MCP_TV_DAC_RSET MCP_DAC_COMP MCP_DAC_RSET
MCP_TV_DAC_VREF MCP_DAC_COMP MCP_DAC_VREF
CRT_50S CRT_IG_VSYNC CRT_SYNC CRT_SYNC
CRT_IG_HSYNC CRT_SYNC CRT_50S CRT_SYNC
CRT_50S CRT CRT_IG_B_COMP_PB CRT_BLUE
CRT_50S CRT_IG_G_Y_Y CRT CRT_GREEN
CRT_IG_R_C_PR CRT CRT_50S CRT_RED
CLK_PCIE PCIE_CLK100M_ENET_N CLK_PCIE_100D
CLK_PCIE PCIE_CLK100M_ENET_P CLK_PCIE_100D MCP_PE2_REFCLK
CLK_PCIE PCIE_CLK100M_AP_N CLK_PCIE_100D
PEG_CLK100M_N CLK_PCIE CLK_PCIE_100D
CLK_PCIE PEG_CLK100M_P CLK_PCIE_100D MCP_PE0_REFCLK
PCIE_FW_D2R_C_N PCIE PCIE_90D
PCIE_FW_D2R_N PCIE PCIE_90D
PCIE_FW_D2R PCIE_FW_D2R_P PCIE PCIE_90D
PCIE PCIE_90D PCIE_FW_R2D_C_N
PCIE_FW_R2D PCIE_FW_R2D_C_P PCIE PCIE_90D
PCIE PCIE_90D PCIE_FW_R2D_P
PCIE PCIE_90D PCIE_ENET_D2R_C_N
PCIE PCIE_90D PCIE_ENET_D2R_C_P
PCIE PCIE_90D PCIE_ENET_D2R_N
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15 29
6 15 29
6 15 29
15 29
33
15 31
15 33
6 8 67
15
16 23
6 29
6 29
15 31
31
15 31
31
8 68
16 23
8 67
8 67
6 8 67
16 23
17 36
17 36
6 36
6 36
17 36
17 36
6 36
6 36
17 36
6 36
17 36
6 36
17 36
17 36
36
36
17
15 29
33
15 33
16 23
8 68
8
8
8
8
8
8
8
8
8
15 31
15 31
15 29
8 15
8 15
33
15 33
15 33
15 33
15 33
33
31
31
15 31
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3 4 5 6 7 8
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8 7 5 4 2 1
SIO Signal Constraints
(SMBUS_SMC_MGMT_SDA)
(SMBUS_SMC_MGMT_SCL)
SPACING PHYSICAL
LPC Bus Constraints
HD Audio Interface Constraints
SPI Interface Constraints
USB 2.0 Interface Constraints
SMBus Interface Constraints
NET_TYPE
MCP89 Net Properties
MCP Constraints 2
=4x_DIELECTRIC TOP,BOTTOM ? USB
MCP_USB_RBIAS * =STANDARD 8 MIL =STANDARD =STANDARD =STANDARD 8 MIL
? SPI * =1.5x_DIELECTRIC
=55_OHM_SE SPI_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE * =STANDARD =STANDARD
? CLK_SLOW * =1.5x_DIELECTRIC
* =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE CLK_SLOW_55S =STANDARD =STANDARD
? * HDA =2x_DIELECTRIC
MCP_HDA_COMP 8 MIL * ?
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE HDA_55S =STANDARD =STANDARD *
SMB * ? =2x_DIELECTRIC
=55_OHM_SE =55_OHM_SE =55_OHM_SE SMB_55S =STANDARD =STANDARD * =55_OHM_SE
=2x_DIELECTRIC USB ? *
CLK_LPC * ? =2x_DIELECTRIC
LPC ? * =1.5x_DIELECTRIC
* CLK_LPC_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
=55_OHM_SE =STANDARD =55_OHM_SE =55_OHM_SE =55_OHM_SE LPC_55S * =STANDARD
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF USB_90D
SPI_MLB_MISO SPI_55S SPI
SPI SPI_CLK_R SPI_CLK SPI_55S
USB_WM_P USB_WM USB_90D USB
USB_SDCARD USB_SDCARD_P USB USB_90D
MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS
SMB SMBUS_MCP_0_CLK SMBUS_MCP_0_CLK SMB_55S
SMBUS_MCP_0_DATA SMB SMBUS_MCP_0_DATA SMB_55S
SMBUS_MCP_1_CLK SMB SMB_55S
SMBUS_MCP_1_DATA SMB SMB_55S
HDA_SYNC HDA HDA_SYNC HDA_55S
HDA_BIT_CLK_R HDA HDA_55S
MCP_HDA_COMP MCP_HDA_PULLDN_COMP MCP_HDA_PULLDN_COMP
CLK_SLOW CLK_SLOW_55S PM_CLK32K_SUSCLK
SPI SPI_MISO SPI_55S SPI_MISO
LPC_AD LPC_AD<3..0> LPC_55S LPC
LPC_FRAME_L LPC_FRAME_L LPC LPC_55S
LPC_RESET_L LPC LPC_RESET_L LPC_55S
MCP_LPC_CLK0 CLK_LPC CLK_LPC_55S LPC_CLK33M_SMC_R
CLK_LPC CLK_LPC_55S LPC_CLK33M_SMC
CLK_LPC CLK_LPC_55S LPC_CLK33M_LPCPLUS
USB_EXTA USB USB_90D USB_EXTA_P
USB USB_EXTA_N USB_90D
USB USB_90D USB_EXTA_MUXED_P
USB USB_90D USB_MINI USB_MINI_P
USB_90D USB USB_EXTA_MUXED_N
USB_MINI_N USB USB_90D
USB USB_EXTD_P USB_90D USB_EXTD
USB USB_EXTD_N USB_90D
USB_90D USB USB_BT_N
USB_90D USB_CAMERA USB USB_CAMERA_P
HDA_SDIN0 HDA HDA_55S HDA_SDIN0
HDA_SYNC_R HDA HDA_55S
HDA_BIT_CLK HDA_BIT_CLK HDA HDA_55S
USB_WM_N USB USB_90D
USB_T57_N USB USB_90D
USB_90D USB USB_EXTB_N
USB_90D USB USB_EXTB USB_EXTB_P
USB_90D USB USB_IR_N
USB_IR_P USB USB_90D USB_IR
USB USB_90D USB_TPAD_N
USB USB_90D USB_TPAD_P USB_TPAD
USB_90D USB USB_BT USB_BT_P
USB USB_90D USB_CAMERA_N
USB_T57 USB_T57_P USB_90D USB
USB_EXTC_P USB_EXTC USB USB_90D
USB_SDCARD_N USB_90D USB
USB_90D USB_EXTC_N USB
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R
HDA_55S HDA_SDOUT_R HDA
HDA_SDOUT HDA HDA_SDOUT HDA_55S
HDA HDA_55S HDA_SDIN_CODEC
SPI_CS0_R_L SPI_CS0 SPI_55S SPI
SPI_MOSI_R SPI_MOSI SPI SPI_55S
HDA_RST_L HDA HDA_55S
HDA_RST_L HDA_RST_R_L HDA HDA_55S
SPI_55S SPI SPI_CLK
SPI_MOSI SPI_55S SPI
SPI SPI_55S SPI_CS0_L
SPI_MLB_CLK SPI SPI_55S
SPI_MLB_MOSI SPI_55S SPI
SPI_MLB_CS_L SPI SPI_55S
SPI_ALT_CS_L SPI_55S SPI
SPI_ALT_MOSI SPI SPI_55S
SPI_ALT_MISO SPI SPI_55S
SPI_ALT_CLK SPI_55S SPI
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18 24
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88E1116R (Ethernet PHY) Constraints
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
SD Card Interface Constraints
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
BCM5764M/BCM57765 co-layout.
NET_TYPE
PHYSICAL
NET_TYPE
PHYSICAL
SPACING
NOTE: SD_D<7..5> are different to support
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
SPACING
RGMII Net Properties
SD Card Net Properties
SPACING
Ethernet Net Properties
MCP RGMII (Ethernet) Constraints
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF * =100_OHM_DIFF ENET_MDI_100D
Ethernet Constraints
* =STANDARD =STANDARD ENET_MII_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
ENET_MDI * ? 25 MIL
ENET_MII * ? 12 MIL
SD_INTERFACE * =3X_DIELECTRIC ?
=STANDARD =STANDARD =55_OHM_SE SD_55S =55_OHM_SE =55_OHM_SE * =55_OHM_SE
MCP_MII_COMP * =STANDARD 7.5 MIL =STANDARD =STANDARD 7.5 MIL =STANDARD
MCP_BUF0_CLK ? * =3:1_SPACING
ENET_MII ENET_MDIO ENET_MDIO ENET_MII_55S
ENET_RXCLK ENET_CLK125M_RXCLK_R ENET_MII ENET_MII_55S
ENET_MII ENET_MII_55S ENET_RXD_STRAP ENET_RXD<3..1>
ENET_MII_55S ENET_MII ENET_RXD ENET_RX_CTRL
ENET_MII ENET_RXD_R<3..0> ENET_MII_55S
ENET_CLK125M_RXCLK ENET_MII_55S ENET_MII
ENET_MII ENET_TXD ENET_TXD<0> ENET_MII_55S
ENET_MII_55S ENET_TXD<3..1> ENET_MII ENET_TXD
ENET_INTR_L ENET_MII_55S ENET_INTR_L ENET_MII
RTL8211_CLK25M_CKXTAL1 MCP_BUF0_CLK ENET_MII_55S
MCP_BUF0_CLK MCP_CLK25M_BUF0 MCP_CLK25M_BUF0_R ENET_MII_55S
MCP_MII_COMP_VDD MCP_MII_COMP MCP_MII_COMP
MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP
ENET_MII ENET_MDC ENET_MDC ENET_MII_55S
ENET_MII ENET_PWRDWN_L ENET_PWRDWN_L ENET_MII_55S
ENET_MII_55S ENET_CLK125M_TXCLK ENET_MII ENET_TXCLK
ENET_RESET_L ENET_MII ENET_MII_55S
ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_TXD
ENET_MDI ENET_MDI_100D ENET_MDI_N<3..0>
ENET_MDI ENET_MDI_P<3..0> ENET_MDI ENET_MDI_100D
SD_55S SD_INTERFACE SDCONN_DATA<4..0>
SD_DATA SD_INTERFACE SD_55S SD_D<4..0>
SD_55S SD_INTERFACE BCM57765_CR_DATA<4>
SD_DATA_R SD_INTERFACE SD_55S SD_D<7..5>
SD_INTERFACE SD_55S SDCONN_DATA<7..5>
BCM57765_CR_DATA<7..5> SD_INTERFACE SD_55S
SD_CLK SD_55S SD_INTERFACE SD_CLK
SD_55S SD_INTERFACE SDCONN_CLK
SD_55S SD_INTERFACE SD_CLK_R
SD_55S SD_INTERFACE SDCONN_CMD
SD_INTERFACE SD_55S SD_CMD SD_CMD
BCM57765_CR_CMD SD_INTERFACE SD_55S
ENET_RXD_STRAP ENET_MII ENET_RXD<0> ENET_MII_55S
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FireWire Interface Constraints FireWire Net Properties
NET_TYPE
PHYSICAL
Port 2 Not Used
SPACING ELECTRICAL_CONSTRAINT_SET
* =3:1_SPACING ? FW_TP
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF FW_100D * =100_OHM_DIFF
FireWire Constraints
FW_100D FW_P0_TPA FW_P0_TPA_N FW_TP
FW_100D FW_P0_TPB FW_P0_TPB_P FW_TP
FW_100D FW_P1_TPA FW_TP FW_P1_TPA_N
FW_100D FW_P0_TPA FW_P0_TPA_P FW_TP
FW_100D FW_P0_TPB FW_P0_TPB_N FW_TP
FW_100D FW_P1_TPA FW_TP FW_P1_TPA_P
FW_100D FW_P1_TPB FW_TP FW_P1_TPB_P
FW_100D FW_P1_TPB FW_TP FW_P1_TPB_N
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SMBus Charger Net Properties
NET_TYPE
PHYSICAL SPACING
SMC SMBus Net Properties
SPACING PHYSICAL
NET_TYPE
SMC Constraints
=STANDARD =STANDARD 0.1 MM 0.1 MM * =STANDARD =STANDARD 1TO1_DIFFPAIR
SMB_55S SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL SMB
SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA SMB SMB_55S
SMBUS_SMC_MGMT_SCL SMB SMB_55S SMBUS_SMC_MGMT_SCL
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL SMB SMB_55S
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA SMB SMB_55S
SMB SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL SMB_55S
SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA SMB SMB_55S
SMBUS_SMC_B_S0_SDA SMB SMBUS_SMC_B_S0_SDA SMB_55S
SMBUS_SMC_B_S0_SCL SMB SMBUS_SMC_B_S0_SCL SMB_55S
SMBUS_SMC_A_S3_SDA SMB_55S SMBUS_SMC_A_S3_SDA SMB
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P
1TO1_DIFFPAIR CHGR_CSI_N
CHGR_CSI_R_P 1TO1_DIFFPAIR
CHGR_CSO_R_N 1TO1_DIFFPAIR
CHGR_CSO_N 1TO1_DIFFPAIR
CHGR_CSO_P 1TO1_DIFFPAIR CHGR_CSO
CHGR_CSI_R_N 1TO1_DIFFPAIR
CHGR_CSO_R_P 1TO1_DIFFPAIR
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OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
(DP_EXT_AUX_CH)
(DP_EXT_ML)
NET_TYPE
Graphics Net Properties
SPACING
(USB_TPAD)
(USB_TPAD)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_EXTA)
(USB_CAMERA)
(USB_CAMERA)
Audio Net Properties
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
NET_TYPE
SPACING
NET_TYPE
PHYSICAL ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
(PCIE_AP)
Misc Net Properties Power Net Properties
MCP Fanout Constraint Relaxations
I277
MEM_DQS GND_P2MM * GND
GND_P2MM CLK_PCIE * GND
CPU_GTLREF GND_P2MM * GND
CPU_COMP GND_P2MM * GND
GND_P2MM * GND CLK_FSB
CPU_VCCSENSE GND_P2MM * GND
MCP_DV_COMP TOP 500 MIL 0.1 MM
0.25 MM * 250 MIL MCP_DV_COMP
GND_P2MM GND * LVDS
SB_POWER PWR_P2MM CLK_PCIE *
GND_P2MM USB * GND
PCIE * GND GND_P2MM
GND ? =STANDARD *
MEM_POWER ? * =STANDARD
? =2:1_SPACING * AUDIO
=2:1_SPACING * SENSE ?
? 25 MILS * ENETCONN
1000 0.20 MM * GND_P2MM
1000 0.20 MM * PWR_P2MM
=1:1_DIFFPAIR * =55_OHM_SE SENSE_1TO1_55S =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR * =55_OHM_SE THERM_1TO1_55S =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR =55_OHM_SE
=1:1_DIFFPAIR * DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
? =2:1_SPACING * THERM
MEM_40S 5.8 MM 0.09 MM *
MEM_DATA GND_P2MM * GND
MEM_CTRL GND_P2MM * GND
MEM_CMD GND_P2MM * GND
MEM_CLK GND_P2MM * GND
PWR_P2MM MEM_POWER * MEM_CTRL
GND * GND_P2MM ENET_MDI
GND_P2MM SATA * GND
SB_POWER PWR_P2MM USB *
SB_POWER PWR_P2MM SATA *
PWR_P2MM MEM_POWER * MEM_DQS
PWR_P2MM MEM_POWER * MEM_DATA
PWR_P2MM MEM_POWER * MEM_CMD
PWR_P2MM MEM_POWER * MEM_CLK
TOP 0.1 MM MCP_USB_RBIAS 500 MIL
TOP MCP_MII_COMP 500 MIL 0.1 MM
500 MIL MCP_MEM_COMP TOP 0.1 MM
K6/K69 Specific Constraints
SATA SATA_HDD_D2R_RDRV_OUT_P SATA_90D
SATA SATA_90D SATA_HDD_D2R_RDRV_OUT_N
SATA_90D SATA_HDD_R2D_RDRV_OUT_P SATA
SATA_90D SATA_HDD_R2D_RDRV_OUT_N SATA
SATA_HDD_D2R_NORDRV_P SATA_90D SATA
SATA_HDD_D2R_NORDRV_N SATA_90D SATA
SATA_HDD_R2D_NORDRV_P SATA SATA_90D
SATA_HDD_R2D_NORDRV_N SATA_90D SATA
SATA_ODD_D2R_UF_N SATA SATA_90D
SATA SATA_HDD_R2D_UF_N SATA_90D
SATA SATA_90D SATA_HDD_D2R_RDRV_IN_P
SATA SATA_HDD_R2D_RDRV_IN_N SATA_90D
LVDS_CONN_B_CLK_N LVDS_100D LVDS
DP_90D DP_AUX_CH_SW_N DISPLAYPORT
DP_90D DP_AUX_CH_SW_P DISPLAYPORT
DP_90D DP_EXT_AUX_CH_C_N DISPLAYPORT
DP_90D DP_EXT_AUX_CH_C_P DISPLAYPORT
DP_90D DP_EXT_ML_F_N<3..0> DISPLAYPORT
DP_90D DP_EXT_ML_F_P<3..0> DISPLAYPORT
DP_EXT_ML_C_N<3..0> DP_90D DISPLAYPORT
DP_90D DP_EXT_ML_C_P<3..0> DISPLAYPORT
DP_90D DP_EXT_ML_N<3..0> DISPLAYPORT
DP_90D DP_EXT_ML_P<3..0> DISPLAYPORT
LVDS_100D LVDS_CONN_B_DATA_N<2..0> LVDS
LVDS_100D LVDS_CONN_B_DATA_P<2..0> LVDS
LVDS_CONN_B_CLK_F_N LVDS_100D LVDS
LVDS_CONN_B_CLK_F_P LVDS_100D LVDS
LVDS_100D LVDS_CONN_B_CLK_P LVDS
LVDS_CONN_A_DATA_N<2..0> LVDS_100D LVDS
LVDS_100D LVDS_CONN_A_DATA_P<2..0> LVDS
LVDS_100D LVDS_CONN_A_CLK_F_N LVDS
LVDS_100D LVDS_CONN_A_CLK_F_P LVDS
LVDS_CONN_A_CLK_P LVDS_100D LVDS
LVDS_100D LVDS_CONN_A_CLK_N LVDS
SATA SATA_HDD_R2D_RDRV_IN_P SATA_90D
SATA SATA_HDD_D2R_RDRV_IN_N SATA_90D
SATA_HDD_D2R_UF_N SATA SATA_90D
SATA_ODD_D2R_UF_P SATA SATA_90D
SATA SATA_90D SATA_ODD_R2D_UF_N
SATA SATA_ODD_R2D_UF_P SATA_90D
ENETCONN_P<3..0> ENETCONN ENET_MDI_100D
USB_LT2_N USB USB_90D
USB_90D USB USB_BT_CONN_N
USB_90D USB_LT2_P USB
USB_90D USB USB_BT_CONN_P
USB_90D USB USB_CAMERA_CONN_N
USB_90D USB USB_CAMERA_CONN_P
USB_TPAD_R_P USB USB_90D
USB_90D USB USB_TPAD_R_N
USB_90D USB USB_LT1_P
USB_90D USB USB_LT1_N
USB_90D USB USB_EXTA_MUXED_N
USB USB_90D USB_EXTA_MUXED_P
SENSE_1TO1_55S SENSE_DIFFPAIR SENSE ISNS_LCDBKLT_P
MCPCORES0_VSEN_N SENSE_1TO1_55S SENSE
DIFFPAIR HS_MIC_N AUDIO
DIFFPAIR BI_MIC_N AUDIO
DIFFPAIR HS_MIC_P AUDIO
SPKRCONN_R_OUT_N DIFFPAIR AUDIO
DIFFPAIR BI_MIC_P AUDIO
SPKRCONN_S_OUT_N DIFFPAIR AUDIO
SPK_OUT SPKRCONN_R_OUT_P DIFFPAIR AUDIO
SPK_OUT SPKRCONN_S_OUT_P DIFFPAIR AUDIO
SPK_OUT DIFFPAIR SPKRCONN_L_OUT_P AUDIO
SPKRCONN_L_OUT_N DIFFPAIR AUDIO
DIFFPAIR SSM2315R_P AUDIO
DIFFPAIR SSM2315R_N AUDIO
DIFFPAIR SSM2315S_P AUDIO
DIFFPAIR SSM2315S_N AUDIO
DIFFPAIR SSM2315L_N AUDIO
DIFFPAIR AUD_SPKRAMP_RIN_N AUDIO
DIFFPAIR SSM2315L_P AUDIO
DIFFPAIR AUD_SPKRAMP_SUBIN_N AUDIO
DIFFPAIR AUD_SPKRAMP_RIN_P AUDIO
DIFFPAIR AUD_SPKRAMP_SUBIN_P AUDIO
DIFFPAIR AUD_SPKRAMP_LIN_P AUDIO
DIFFPAIR AUD_SPKRAMP_LIN_N AUDIO
SB_POWER PP1V5_S0
SB_POWER PP3V3_S5
SB_POWER PP3V3_S0
PP1V5R1V35_S3 MEM_POWER
ISNS_HDD_N SENSE_1TO1_55S SENSE
ISNS_CPUVTT_P SENSE SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_ODD_P
SENSE SENSE_1TO1_55S ISNS_LCDBKLT_R_N
SENSE_1TO1_55S SENSE ISNS_ODD_N
SENSE_1TO1_55S SENSE ISNS_ODD_R_P
ISNS_ODD_R_N SENSE SENSE_1TO1_55S
SENSE_1TO1_55S SENSE ISNS_HDD_R_P
SENSE SENSE_1TO1_55S ISNS_HDD_R_N
SENSE_1TO1_55S SENSE ISNS_LCDBKLT_N
THERM_1TO1_55S THERM CPUTHMSNS_D2_N
CPUTHMSNS_D2 THERM_1TO1_55S THERM CPUTHMSNS_D2_P
CPU_THERMD THERM_1TO1_55S THERM CPU_THERMD_P
THERM_1TO1_55S THERM CPU_THERMD_N
MCPTHMSNS_D2 THERM_1TO1_55S THERM MCPTHMSNS_D2_P
THERM_1TO1_55S THERM MCP_THMDIODE MCP_THMDIODE_P
THERM_1TO1_55S THERM MCPTHMSNS_D2_N
THERM_1TO1_55S THERM MCP_THMDIODE_N
SENSE_1TO1_55S SENSE ISNS_1V5_S3_N
SENSE_1TO1_55S SENSE_DIFFPAIR SENSE ISNS_1V5_S3_P
SENSE_1TO1_55S SENSE ISNS_1V5_S3_R_P
ISNS_1V5_S3_R_N SENSE_1TO1_55S SENSE
SENSE_1TO1_55S SENSE_DIFFPAIR SENSE ISNS_AIRPORT_P
SENSE SENSE_1TO1_55S ISNS_AIRPORT_R_P
ISNS_AIRPORT_N SENSE_1TO1_55S SENSE
ISNS_AIRPORT_R_N SENSE SENSE_1TO1_55S
ISNS_HDD_P SENSE_1TO1_55S SENSE_DIFFPAIR SENSE
CLK_PCIE PCIE_CLK100M_AP_CONN_P CLK_PCIE_100D
PCIE_CLK100M_AP_CONN_N CLK_PCIE CLK_PCIE_100D
SENSE_1TO1_55S SENSE ISNS_LCDBKLT_R_P
SENSE_1TO1_55S SENSE ISNS_CPUVTT_N
MCPCORES0_VSEN_P SENSE_DIFFPAIR SENSE SENSE_1TO1_55S
ENETCONN ENET_MDI_100D ENETCONN_N<3..0>
SATA SATA_HDD_D2R_UF_P SATA_90D
SATA_90D SATA SATA_HDD_R2D_UF_P
GND GND
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TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET AREA_TYPE NET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_HEAD MINIMUM LINE WIDTH ALLOW ROUTE
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS BOARD LAYERS BOARD AREAS
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
K6/K69 Board-Specific Physical & Spacing Constraints
* =STANDARD N 110_OHM_DIFF =STANDARD =STANDARD =STANDARD =STANDARD
=STANDARD =STANDARD 0.076 MM =STANDARD 50_OHM_SE Y 0.076 MM *
0.200 MM 0.200 MM 0.185 MM 70_OHM_DIFF Y 0.185 MM TOP,BOTTOM
0.234 MM 0.234 MM 0.095 MM 90_OHM_DIFF Y 0.095 MM ISL3,ISL4,ISL9,ISL10
=STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF N =STANDARD *
0.224 MM =STANDARD 70_OHM_DIFF Y 0.151 MM ISL3,ISL4,ISL9,ISL10 0.109 MM 0.090 MM
0.100 MM 40_OHM_SE Y 0.165 MM TOP,BOTTOM
=DEFAULT =DEFAULT =DEFAULT 12.7 MM STANDARD Y =DEFAULT *
0 MM 0 MM 0.080 MM 12.7 MM DEFAULT Y =50_OHM_SE *
4:1_SPACING * 0.4 MM ?
2.5:1_SPACING * 0.25 MM ?
1.5:1_SPACING * 0.15 MM ?
STANDARD * =DEFAULT ?
BGA MEM_40S STANDARD * BGA BGA_P1MM *
* BGA BGA_P2MM MEM_CLK
NO_TYPE,BGA MM 15.2 TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
BGA_P3MM * 0.3 MM ?
DEFAULT * 0.1 MM ?
* BGA BGA_P2MM CLK_LPC
* BGA BGA_P2MM CLK_FSB 0.1 MM BGA_P1MM * ?
BGA_P2MM * 0.2 MM ?
CLK_PCIE BGA_P2MM BGA *
CLK_SLOW BGA_P2MM BGA *
FSB_DSTB BGA_P3MM BGA FSB_DSTB
=STANDARD =STANDARD =STANDARD 70_OHM_DIFF N =STANDARD * =STANDARD
? 0.210 MM TOP,BOTTOM 3X_DIELECTRIC
2X_DIELECTRIC TOP,BOTTOM 0.140 MM ?
? TOP,BOTTOM 1.5X_DIELECTRIC 0.105 MM
3X_DIELECTRIC * 0.189 MM ?
? 0.126 MM * 2X_DIELECTRIC
* ? 0.095 MM 1.5X_DIELECTRIC
0.310 MM 27P4_OHM_SE Y TOP,BOTTOM 0.310 MM
=STANDARD =STANDARD 0.100 MM =STANDARD 40_OHM_SE Y 0.126 MM *
=STANDARD =STANDARD 0.076 MM =STANDARD 55_OHM_SE Y * 0.076 MM
=STANDARD =STANDARD 0.222 MM 27P4_OHM_SE * =STANDARD 0.222 MM Y
* =STANDARD Y 1:1_DIFFPAIR =STANDARD 0.1 MM 0.1 MM =STANDARD
TOP,BOTTOM 0.077 MM Y 110_OHM_DIFF 0.077 MM 0.330 MM 0.330 MM
ISL3,ISL4,ISL9,ISL10 0.075 MM Y 110_OHM_DIFF 0.075 MM 0.330 MM 0.330 MM
0.244 MM 0.075 MM 100_OHM_DIFF Y ISL3,ISL4,ISL9,ISL10 0.075 MM 0.244 MM
0.091 MM 100_OHM_DIFF Y 0.091 MM TOP,BOTTOM 0.230 MM 0.230 MM
=STANDARD =STANDARD 100_OHM_DIFF N =STANDARD * =STANDARD =STANDARD
0.220 MM 0.220 MM 0.112 MM 90_OHM_DIFF Y 0.112 MM TOP,BOTTOM
K6/K69 PCB Rule Definitions
109 OF 109
A.13.0
051-8563
80 OF 80

Macbook A1278-820-2879 SCH

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