The ARM11 Architecture

Ian Davey
Payton Oliveri
Spring 2009
CS4

Why ARM Matters

Over 90! o" the e#$e%%e% #ar&et i' $a'e% on

the ARM architecture

ARM (t%) #a&e' over *100 #illion +SD

annually in royaltie' an% licen'ing "ee' "or thi'
technology

Over t,o $illion unit' are 'hippe% each year

-e ,ill "ocu' pri#arily on the ARM11./0123S4

,hich i' u'e% in a nu#$er o" '#artphone' a'
,ell a' the iPo% Touch

General Overview

ARM 'tan%' "or A%vance% RISC Machine

The ARM11 i' $a'e% on the ARMv/ in'truction

'et architecture

5i3en%ian 6 can operate in either little3en%ian or

$ig3en%ian "or#at

Mo't %evice' to%ay u'e little3en%ian

Actually u'e' t,o in'truction 'et' 6 the 23$it

ARM an% the 1/3$it Thu#$

ARM and Thumb

Since #any e#$e%%e% %evice' have '#all

a#ount' o" #e#ory4 a '#aller4 1/3$it
in'truction 'et can $e u'e%

Thi' 1/3$it 7Thu#$8 in'truction 'et #a&e' u'e

o" i#plie% operan%' an% re%uce% "unctionality
to re%uce co%e 'i9e

Thu#$ in'truction' are %eco%e% into ARM

in'truction' on the "ly at e:ecution ti#e4 though
con'u#ing one a%%itional cycle

CP+ i' either in 8ARM 'tate8 or 8Thu#$ 'tate8

Registers 32-bit ARM mode

1/ general3purpo'e regi'ter' R03R1;

R1 i' the 'tac& pointer an% i' o"ten calle% SP

R14 hol%' return a%%re''e' an% i' o"ten calle% (R

<"or lin& regi'ter=

R1; i' the progra# counter an% i' o"ten calle% PC

PC i' al,ay' ,or%3aligne%

1. general3purpo'e 8#o%e3'peci"ic8 regi'ter'

<u'e% "or e:ception han%ling4 etc)=

. 'tatu' regi'ter'4 one "or each operating #o%e

Registers 1-bit Thumb mode

. 'et' o" 11 regi'ter' each

> general3purpo'e regi'ter' R03R.

Stac& pointer4 lin& regi'ter4 an% progra# counter

?ach 'et i' "or a %i""erent operating #o%e

More on operating #o%e' later

!tatus Register !"e#i$i#s

5it' 0 through 4 %eter#ine the proce''or

operating #o%e

5it ; in%icate' ,hether the proce''or i' in ARM

or Thu#$ 'tate

5it' / an% . %i'a$le interrupt'

5it' 2> through 1 are A(+ con%ition co%e "lag'

@ "or negative A(+ re'ult

1 "or 9ero A(+ re'ult

C "or over"lo, a"ter 'hi"t operation

A "or over"lo, a"ter 'igne% arith#etic operation

O"erating Modes

A' #entione% $e"ore4 each #o%e ha' it' o,n

#o%e3'peci"ic regi'ter'4 inclu%ing a 'tatu'
regi'ter

The > #o%e' o" operation con'i't o" .

8privile%ge% #o%e'8 3 ,hich are u'e% to han%le
e:ception' an% ea'e nor#al re'ource
re'triction' 6 an% 1 8u'er #o%e8 ,hich i' u'e%
%uring nor#al operation an% ha' all re'triction'
in place

O"erating Modes
1) +'er 6 nor#al operation
2) 2a't interrupt 6 han%ling o" 8"a't8 interrupt'
) Interrupt 6 han%ling o" all other interrupt'
4) Supervi'or 6 operating 'y'te# protecte% #o%e
;) A$ort 6 a$ortion o" #e#ory acce''
/) Sy'te# 6 operating 'y'te# privilege% #o%e
.) +n%e"ine% 6 invali% in'truction in 'trea#
>) Secure #onitor 6 on3chip 'ecurity "eature'

ARM %nstru#tion !et Ar#hite#ture

?ach in'truction i' 2 $it' long

Bighe't "our $it' %eter#ine con%ition <in%icate%

in 'tatu' regi'ter= un%er ,hich the in'truction i'
e:ecute%

Can %i'car% in'truction i##e%iately a"ter %eco%e

Only t,o pipeline 'tage' are ,a'te% <a' 'een ne:t=

2e,er $ranch in'truction' nee%e%4 '#aller co%e

Other "iel%' contain operan%'4 o""'et con'tant'4

an% variou' 13$it "lag'

The &i"eline

> 'tage' in nor#al pipeline

1) 2e1 6 A%%re'' i' 'ent an% in'truction receive%
2) 2e2 6 Much o" the $ranch pre%iction goe' here
) De 6 Deco%e in'truction
4) I'' 6 Rea% regi'ter' an% i''ue in'truction
;) Sh 6 Per"or# 'hi"t operation'
/) A(+ 6 Per"or# integer operation'
.) Sat 6 Saturate re'ult'
>) -5 6 -rite $ac& %ata to regi'ter'

The !hi$t &i"eline !tage

There are no e:plicit 'hi"t in'truction'

?ach arith#etic in'truction ha' a "iel% to 'peci"y

a#ount to 'hi"t one operan%

ARM #icroarchitecture contain' a $arrel 'hi"ter

that can per"or# 'hi"t' an% rotate' on operan%'

Thi' i' ,hy the 'tatu' regi'ter ha' 'eparate

"lag' o" 'hi"t an% arith#etic over"lo,

Alternate &i"eline &aths

Sh4 A(+4 an% Sat can $e replace% ,ith three

MAC 'tage'4 ,hich per"or# #ultiplication
operation'

The'e three 'tage' can al'o $e replace% ,ith

%i""erent 'tage' "or #e#ory operation'C
1) ADD 6 calculate a%%re''
2) DC1 an% DC2 6 Acce'' %ata cache

&arallelism within %nstru#tions

So#e in'truction'4 'uch a' tho'e ,hich acce''

#e#ory an% incre#ent a regi'ter at the 'a#e
ti#e <u'e"ul "or array operation'=4 ,ill u'e $oth
the #e#ory acce'' path,ay an% the arith#etic
path,ay 'i#ultaneou'ly

I" the %ata cache #i''e' an% there i' a 'tall in

the #e#ory acce'' path,ay4 the arith#etic
path,ay ,ill continue e:ecution any,ay

Thi' "ree' up the A(+ an% 'aturation 'tage "or

u'e ,ith other in'truction'

'ran#hes

5ranch in'truction contain' con%ition "iel%4 lin&

"lag4 an% 243$it o""'et "iel%

Target #u't $e ,or%3aligne%4 'o o""'et i'

e""ectively 2/ $it'

Target a%%re'' calculate% $y 'ign3e:ten%ing

PC3>Do""'et <'u$tract > "or pipeline=

Progra# can $ranch to a%%re''e' up to 2

#ega$yte' a,ay "ro# PC

I" the lin& "lag i' 'et4 'tore ol% PC in (R

'ran#h &redi#tion

-hile the con%ition attache% to every

in'truction help' re%uce co'tly e:plicit
$ranche'4 it %oe' not eli#inate the# entirely

@aive approach in ARM9 i' to al,ay' pre%ict

that the $ranch ,ill not $e ta&en

Thi' ri'&' lo'ing D cycle' i" ,rongE

Thi' ,a' #ore accepta$le "or the ARM94 ,hich ha'

a 'horter pipeline

There"ore4 ARM11 i#ple#ent' #ore

aggre''ive techniFue'

'ran#h Target Address (a#he

Direct3#appe%4 12>3entry cache ,hich &eep'

trac& o" previou' $ranch in'truction' <in%e:e%
$y a%%re''= an% their re'ult'

Store' 23$it pre%iction hi'tory4 ,hich it u'e' to

#a&e ne:t pre%iction

(ine' only evicte% "ro# cache in the event o" a

con"lict ,ith another $ranch a%%re''

Aery e""ective "or loop'4 ,here $ranche' have

the 'a#e re'ult #any ti#e' in a ro,

!tati# 'ran#h &redi#tion

+'e% ,hen 5TAC entry not availa$le

Con"igure% in har%,are to ta&e $ranche' ,ith

negative o""'et'4 an% not ta&e $ranche' ,ith
po'itive o""'et'

Once again thi' ,oul% help loop per"or#ance4

'ince Gu#p' $ac&,ar%' ten% to "ollo, the $o%y
o" a loop

The "or,ar%3not3ta&en choice acco##o%ate'

the ,ay co#piler' han%le con%itional'

'ran#h )olding

Re#ove' pre%icte% $ranch in'truction' "ro#

the in'truction 'trea#

5ranche' ,ith 8'i%e e""ect'8 are not 'u$Gect to

thi' opti#i9ation4 'ince tho'e e""ect' <'uch a'
lin&' into ne, proce%ure'= #u't $e carrie% out

5ranche' to $ranche' cannot $e "ol%e%4 "or

rea'on' that ,ill $eco#e clear 'hortly

What ha""ens on mis"redi#tion*

Pipeline i' "lu'he% an% correct in'truction' are

"etche%

In'truction' "ollo,ing "ol%e% $ranche' "ail

-henever there i' a chance a "ol%e% $ranch

ha' $een #i'pre%icte%4 a%%re'' o" the
alternative choice #u't $e re#e#$ere%

The'e alternative' are retrieve% i" it turn' out

the $ranch ,a' in%ee% #i'pre%icte%

Thi' i' ,hy $ranche' to $ranche' cannot $e

"ol%e% 6 ,oul% nee% to 'tore #ultiple
alternative'

Memory A##ess

Data #u't $e #ove% to regi'ter' $e"ore it can

$e #anipulate%

A #e#ory ,or% can $e in%e:e% $y a regi'ter

plu' or #inu' a 123$it o""'et con'tant

A hal",or% or $yte can $e in%e:e% the 'a#e

,ay4 e:cept the o""'et can only $e > $it'

Support "or $loc&3%ata tran'"er 6 can tran'"er

up to 1/ regi'ter' to an% "ro# #e#ory in a
'ingle in'truction

Memory +ierar#hy

(1 cache involve' 'eparate in'truction an% %ata

cache' an% a ,rite $u""er

?ach cache i' 43,ay 'et3a''ociative4 ranging "ro#

4H5 to /4H5 in 'i9e4 ,ith >3,or% cache line'

Cache i' virtually in%e:e%4 virtually tagge%

Data cache #i''e' are non3$loc&ing

+pon eviction4 i" %ata nee%' to $e ,ritten $ac& to

#e#ory4 the line i' a%%e% to the ,rite $u""er

-rite $u""er han%le' all RA- ha9ar%' that #ay

occur ,hen hol%ing nee%e% %ata

Memory +ierar#hy

(2 cache i' o""3chip

In'truction controller4 %ata controller4 an% DMA

har%,are on3chip each ha' it' o,n /43$it ,i%e port4
allo,ing "or 'i#ultaneou' acce''e' to the cache

An a%%itional 23$it peripheral inter"ace connect' to

proce''or peripheral' 'uch a' coproce''or'

Translation ,oo-aside 'u$$er

Actually ha' t,o level'

2ir't level i' &no,n a' Micro3T(5

2 103entry4 "ully a''ociative T(5'4 one "or I3cache4

one "or D3cache

Per"or#' tran'lation in parallel

Secon% level i' calle% the Main T(5

@e:t level up ,hen Micro3T(5 #i''e'

/43entry4 23,ay 'et a''ociative $u""er

Al'o ha' >3entry4 "ully a''ociative 'ection4 u'e%

#ainly in Secure Monitor #o%e

+ardware !ta#-

ARM al'o 'upport' a har%,are 'tac&

5oth up,ar% an% %o,n,ar%3gro,ing 'tac&' are

'upporte%

-hich %irection to gro, i' 'peci"ie% $y the "lag' in

the pu'h an% pop in'truction'

Stac& i' u'e% to 'tore activation recor%'

ARM (alling (onventions

R0 through R hol% the "ir't "our argu#ent'

A%%itional argu#ent' are pa''e% in rever'e or%er

on the 'tac&

Aalue' larger than 2 $it' are pa''e% a' #ultiple

23$it value'

2loating3point value' are pa''e% in regi'ter' on the

"loating3point coproce''or

R4 through R10 hol% local varia$le'

R11 'erve' a' the "ra#e pointer

ARM (alling (onventions

R0 through R hol% return value'

Once again4 %ata type' larger than 2 $it' are

treate% a' #ultiple 23$it value'

R12 hol%' intra3proce%ural inter#e%iate value'

a' ,ell a' 'erve' a' a 'cratchpa% regi'ter
$et,een call'

./#e"tion +andling

+'e' vectore% e:ception han%ling

Ba' a 'eparate 'et o" #o%e3'peci"ic regi'ter'

"or each e:ception #o%e

Special in'truction' e:i't "or 'toring an%

reloa%ing proce''or 'tate to an% "ro# #o%e3
'peci"ic regi'ter'

When an ./#e"tion O##urs

Statu' regi'ter i' copie% into the #o%e3'peci"ic

counterpart

I" proce''or i' in Thu#$ 'tate4 change to ARM

Store return a%%re'' in #o%e3'peci"ic (R

Store appropriate han%ler a%%re'' in PC

Returning $rom ./#e"tions

Copy #o%e3'peci"ic 'tatu' regi'ter $ac& into

u'er 'tatu' regi'ter

Copy return a%%re'' "ro# #o%e3'peci"ic (R

$ac& into PC

!ystem (ontrol (o"ro#essor

A 'et o" 2 rea%a$le an% ,ritea$le regi'ter'

-hich regi'ter' can $e ,ritten %epen%' on

,hether the proce''or i' in the Secure Monitor
operating #o%e

+'e% in con"iguring variou' operation' ranging

"ro# DMA to cache control to per"or#ance
#ea'ure#ent

!%M0 (a"abilities

Aector 2loating3Point coproce''or per"or#'

operation' on > 'ingle3preci'ion or 4 %ou$le3
preci'ion value' 'i#ultaneou'ly4 in parallel ,ith
CP+

Other,i'e co'tly arith#etic operation' 'uch a'

'Fuare root are $uilt into har%,are

De%icate% inter"ace to #ain proce''or

Re'ult' o" co#pare in'truction' are 'tore% in

CP+ 'tatu' regi'ter

Coul% #a&e inter"ace $an%,i%th an% latency a

$ottlenec&

1)& &i"elines

?ach pipeline 'hare' %eco%e an% i''ue 'tage'4

$ut other,i'e ,or&' in%epen%ently an% in
parallel

Multiply an% ACcu#ulate <2MAC= pipeline ha'

. e:ecution 'tage'

Divi%e an% SFuare root <DS= pipeline ha' 4

e:ecution 'tage'

(oa%IStore <(S= pipeline ha' 1 e:ecution an% 2

#e#ory acce'' 'tage'4 an% i' re'pon'i$le "or
co##unicating ,ith the #ain proce''or

1)& Registers and 0ata )ormats

2our $an&' o" > 23$it regi'ter'

?ach in'truction operate' on a $an& o" regi'ter'

Con'ecutive pair' o" regi'ter' can 'tore %ou$le3

preci'ion "loating3point %ata

2loating3point %ata "or#at "ollo,' the I???

'tan%ar%