`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:51:57 10/29/2013
// Design Name: fir
// Module Name: D:/new/fir/fir_tb.v
// Project Name: fir
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fir
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fir_tb;
// Inputs
reg [7:0] data_in;
reg clock;
reg reset;
// Outputs
wire [17:0] data_out;
// Instantiate the Unit Under Test (UUT)
fir uut (
.data_out(data_out),
.data_in(data_in),
.clock(clock),
.reset(reset)
);
initial
clock=1'b0;
always #50 clock=~clock;
initial begin
// Initialize Inputs
data_in = 8'b00000000;
reset = 0;
// Wait
#100;
data_in
reset =
#100;
data_in
reset =
#100;
data_in
reset =
#100;

100 ns for global reset to finish

= 8'b00000001;
1;
= 8'b00000010;
1;
= 8'b00000011;
1;

data_in = 8'b00000100;
reset = 1;
#100;
data_in = 8'b00000101;
reset = 1;
#100;
data_in = 8'b00000110;
reset = 1;
#100;
data_in = 8'b00000111;
reset = 1;
#100;
// Add stimulus here
end
endmodule