ASSIGNMENT-1

1) Develop the verilog code for all gates by using primitives

Ans. Code:- module gate_primitive
(output wire not_o,
output wire and_o,
output wire or_o,
output wire xor_o,
output wire nand_o,
output wire xnor_o,
output wire nor_o,
input wire data1_i,
input wire data2_i
);
not (not_o,data1_i);
and (and_o,data1_i,data2_i);
or (or_o,data1_i,data2_i);
xor (xor_o,data1_i,data2_i);
nand (nand_o,data1_i,data2_i);
nor (nor_o,data1_i,data2_i);
xnor (xnor_o,data1_i,data2_i);
endmodule





Simulation:-

2) Introduce the delay at the output of gates in increasing order
Ans. Code:- module delay_gates
#(parameter period=100)
(output wire not_o,
output wire and_o,
output wire or_o,
output wire xor_o,
output wire nand_o,
output wire xnor_o,
output wire nor_o,
input wire data1_i,
input wire data2_i
);
not #period(not_o,data1_i);
and #(period*2)(and_o,data1_i,data2_i);
or #(period*3)(or_o,data1_i,data2_i);
xor #(period*4)(xor_o,data1_i,data2_i);
nand #(period*5)(nand_o,data1_i,data2_i);
nor #(period*6)(nor_o,data1_i,data2_i);
xnor #(period*7)(xnor_o,data1_i,data2_i);
endmodule
Simulation:-

3) Develop the verilog code for half adder, half subtractor, full adder, full subtractor.
Ans. Code(Half adder and Half subtractor):-
module half_as
(output wire sum_o,
output wire carry_o,
output wire diff_o,
output wire bar_o,
input wire data1_i,
input wire data2_i
);
assign sum_o= (data1_i ^ data2_i);
assign carry_o= (data1_i & data2_i);
assign diff_o= (data1_i ^ data2_i);
assign bar_o= ((~data1_i) & data2_i);
endmodule
Simulation:-

Code(Full adder and full subtractor):-
module full_as
(output wire sum_o,
output wire carry_o,
output wire diff_o,
output wire bar_o,
input wire data1_i,
input wire data2_i,
input wire data3_i
);
assign sum_o = (data1_i ^ data2_i ^ data3_i);
assign carry_o = ((data1_i & data2_i) | (data2_i & data3_i) | (data3_i &
data1_i));
assign diff_o = (data1_i ^ data2_i ^ data3_i);
assign bar_o =
(((~data1_i)&(~data2_i)&data3_i)|((~data1_i)&data2_i&(~data3_i))|((~data1_i)&data2_i
&data3_i)|(data1_i&data2_i&data3_i));
endmodule
Simulation:-

4) Develop the verilog code for 2X4 decoder.
Ans. Code:- module dec_2x4
(output reg [3:0]d,
input wire [1:0]a
);
always @ (a,d)
begin
if (a==2'b00)
d=4'b0001;
else if (a==2'b01)
d=4'b0010;
else if (a==2'b10)
d=4'b0100;
else if (a==2'b11)
d=4'b1000;
end
endmodule
Simulation:-

5) Develop the verilog code for 4X2encoder
Ans. Code:- module en_4x2
(output reg [1:0]data_o,
input wire data1_i,
input wire data2_i,
input wire data3_i,
input wire data4_i
);
always @ (data1_i,data2_i,data3_i,data4_i)
begin
if(data1_i==1 && data2_i==0 && data3_i==0 && data4_i==0)
data_o=2'b00;
else if(data1_i==0 && data2_i==1 && data3_i==0 && data4_i==0)
data_o=2'b01;
else if(data1_i==0 && data2_i==0 && data3_i==1 && data4_i==0)
data_o=2'b10;
else if(data1_i==0 && data2_i==0 && data3_i==0 && data4_i==1)
data_o=2'b11;
end
endmodule
Simulation:-

6) Develop the verilog code for 4-bit binary to gray code conversion.
Ans. Code:-