Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)

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1. Pleasespecifytheinterface(I/O)oftheAMBAAHBMaster,Split-capableSlave,andArbiter.

Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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2. Whyisaburstnotallowedtocrossa1Kbyteboundary?
IfanAHBslavesamplesHSELxatthestartofabursttransaction,itknowsitwillbeselectedforthe
durationoftheburst.Also,aslavewhichisnotselectedatthestartofaburstwillknowthatitwillnot
becomeselecteduntilanewburstisstarted.
1kilobyteisthesmallestareaanAHBslavemayoccupyinthememorymap.Therefore,ifaburstdid
crossa1kilobyteboundary,theaccesscouldstartaccessingoneslaveatthebeginningoftheburst
andthenswitchtoanotherontheboundary,whichmustnothappenfortheabovereason.
The1kilobyteboundaryhasbeenchosenasitislargeenoughtoallowreasonablelengthbursts,but
smallenoughthatperipheralscanbealignedtothe1kilobyteboundarywithoutusinguptoomuchof
theavailablememorymap.

3. Pleasedescribethetwo-cycleresponseanddrawasimpletimingdiagram.
OnlyanOKAYresponsecanbegiveninasinglecycle.TheERROR,SPLITandRETRYresponses
require at least two cycles. To complete with any of these responses then in the penultimate (one
before last) cycle the slave drives HRESP[1:0] to indicate ERROR, RETRY or SPLIT while driving
HREADYLOWtoextendthetransferforanextracycle.InthefinalcycleHREADYisdrivenHIGHto
endthetransfer,whileHRESP[1:0]remainsdriventoindicateERROR,RETRYorSPLIT.
If the slave needs more than two cycles to provide the ERROR, SPLIT or RETRY response then
additionalwaitstatesmaybeinsertedatthestartofthetransfer.DuringthistimetheHREADYsignal
willbeLOWandtheresponsemustbesettoOKAY.
The two-cycle response is required because of the pipelined nature of the bus. By the time a slave
startstoissueeitheranERROR,SPLITorRETRYresponsethentheaddressforthefollowingtransfer
hasalreadybeenbroadcastontothebus.Thetwocycleresponseallowssufficienttimeforthemaster
tocancelthisaddressanddriveHTRANS[1:0]toIDLEbeforethestartofthenexttransfer.

Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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4. SlavesonthebusrequireHREADYasbothaninputandanoutputsignal,why?
AnAHBslavemusthavetheHREADYsignalasbothaninputandanoutput.
HREADY is required as an output from a slave so that the slave can extend the data phase of a
transfer.
HREADY is also required as an input so that the slave can determine when the previously selected
slave has completed its final transfer and the first data phase transfer for this slave is about to
commence.
EachAHBSlaveshouldhaveanHREADYoutputsignal(conventionallynamedHREADYOUT)which
isconnectedtotheSlave-to-MasterMultiplexer.TheoutputofthismultiplexeristheglobalHREADY
signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY
input.
A slave must have the HREADY signal as both an input and an output. The output version of the
HREADYsignalisusedbytheslavetoextendedtransfersandisfedviathebusmultiplexertothebus
masterwhichisperformingthetransfer.
HREADY is also required as an input to slaves and this signal comes from the output of the bus
multiplexer.WhentheslaveisresponsiblefordrivingHREADY(whenitisbeingaccessed)thenthis
signalwillbethesameastheHREADYoutputfromtheslave.However,whenanotherslaveisbeing
accessed, the HREADY signal will indicate if that slave is inserting wait states and this is important
whenamasterchangesfromoneslavetoanother.
ItissuggestedthattheinputversionofthissignaliscalledHREADYandtheoutputisHREADYOUT.

5. OntheAPB,whatisthedifferentbetweenPSELxandPENABLEsignals?
PSELx(APBselect)
A signal from the secondary decoder, within the peripheral bus bridge unit, to each peripheral
busslavex.Thissignalindicatesthattheslavedeviceisselectedandadatatransferisrequired.
ThereisaPSELxsignalforeachbusslave.

PENABLE(APBstrobe)
Thisstrobesignalisusedtotimeallaccessesontheperipheralbus.Theenablesignalisusedto
indicatethesecondcycleofanAPBtransfer.TherisingedgeofPENABLEoccursinthemiddle
oftheAPBtransfer.

Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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6. WhencantheHGRANTsignalchange?
TheHGRANTsignalcanchangeinanycycleandthefollowingcasesarepossible:
It is possible that the HGRANT signal may be asserted and then removed before the current
transfercompletes.ThisisacceptablebecausetheHGRANTsignalisonlysampledbymasters
whenHREADYishigh.
Amastercanbegrantedthebuswithoutrequestingit.
Theabovepointalsomeansthatitispossibletobegrantedthebusinthesamecyclethatitis
requested.Thiscanoccurifthemasteriscoincidentallygrantedthebusinthesamecyclethatit
requestsit.

7. WhencanEarlyBurstTerminationoccur?
BurstscanbeearlyterminatedeitherasaresultoftheArbiterremovingtheHGRANTtoamasterpart
way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note
howeverthatamastercannotdecidetoterminateadefinedlengthburstunlesspromptedtodosoby
theArbiterorSlaveresponses.
AllAHBMasters,SlavesandArbitersmustbedesignedtosupportEarlyBurstTermination.
8. Canamasterchangetheaddress/controlsignalsduringawaitedtransfer?
Yes.Iftheaddress/controlsignalsareindicatinganIDLEtransferthenthemastercanchangetoareal
transfer(NONSEQ)whenHREADYislow.
However,ifamasterisindicatingarealtransfer(NONSEQorSEQ)thenitcannotcancelthisduringa
waitedtransferunlessitreceivesaSPLIT,RETRYorERRORresponse.

9. HowdoestheAHBhandleLOCKedSPLITs?
WhenatransferisSPLITthearbiterdegrantsandremovestheSPLITmasteroutofthearbitrationuntil
theslaveindicatesthatthetransfercancomplete.WhenanaccessisLOCKedtheaccesscannotbe
interruptedbyanaccessfromanothermaster.
The only possible way that an AHB system can handle these two requirements simultaneously is to
grant a "dummy master" when the LOCKed access is SPLIT. The dummy master will only perform
IDLE transactions, which are allowable during a locked transfer. To grant any other master would
violate the LOCK protocol, for the arbiter to ignore the SPLIT would violate the SPLIT protocol - the
dummymasteristheonlyoption.
The dummy masterisalsoused whenallmasters arehavereceivedaSPLITresponse (thedummy
mastercannotreceiveaSPLITresponse).
Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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Itisrecommendedthatthedesignerofthesplit-capableslave(s)makessurethattheslavemonitorsits
HMASTLOCKinputsothatitdoesn'treturnaSPLITonaLOCKedtransfer,asthisservesnopurpose.

10. WhatisthedifferencebetweenSPLITandRETRYresponses?
Both the Split and Retry responses are used by slaves which require a large number of cycles to
complete a transfer. These responses allow a data phase transfer to appear completed to avoid
stallingthebus,butatthesametimeindicatethatthetransfershouldbere-attemptedwhenthemaster
isnextgrantedthebus.
The difference between them is that a SPLIT response tells the Arbiter to give priority to all other
masters until the SPLIT transfer can be completed (effectively ignoring all further requests from this
master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the RETRY
responseonlytellstheArbitertogiveprioritytohigherprioritymasters.
A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it
allowsthemaximumefficiencytobemadeofthebusbandwidth.
ThemasterbehaviorisidenticaltobothSPLITandRETRYresponses,themasterhastocancelthe
nextaccessandre-attemptthecurrentfailedaccess.

11. Whenwillthearbitergrantanothermasterafteralockedtransfer?
The arbiter will always grant the master an extra transfer at the end of a locked sequence, so the
masterisguaranteedtoperformonetransferwiththeHMASTLOCKsignallowattheendofthelocked
sequence.Thiscoincideswiththedataphaseofthelasttransferinthelockedsequence.
DuringthistimethearbitercanchangetheHGRANTsignalstoanewbusmaster,butifthedataphase
of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will drive the
HGRANTsignalstoensurethateitherthemasterperformingthelockedsequenceremainsgrantedon
thebusforaRETRYresponse,ortheDummymasterisgrantedthebusfortheSPLITresponse.

12. Whatisthedifferencebetweenadummybusmasterandadefaultbusmaster?Isadummy
masterreallynecessary?
Thetermdefaultbusmasterisusedtodescribethemasterthatisgrantedwhennoneofthemastersin
thesystemarerequestingaccesstothebus.Usuallythebusmasterwhichismostlikelytorequestthe
busismadethedefaultmaster.
ThedummybusmasterisamasterwhichonlyperformsIDLEtransfers.Itisrequiredinasystemso
the arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases
when the arbiter would need to do this are when a Split response is given to a locked transfer and
whenaSplitresponseisgivenandallothermastershavealreadybeensplit.
Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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AdummymasterisnecessaryinanysystemwhichhasaslavethatcangiveSPLITtransferresponses.
Thedummymasterisrequiredsothatsomethingcanbegrantedthebusifalltheothermastershave
receivedaSPLITresponse.
Nologicisrequiredforthedummymasteranditcanbeimplementedbysimplytyingofftheinputsto
themasteraddress/controlmultiplexerforthedummymasterposition.Therequirementsforadummy
master are that HTRANS is driven to IDLE, HLOCK is driven low, and all other master outputs are
driventolegalvalues.

13. Whenshouldamasterde-assertitsHBUSREQsignal?
For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has
startedtheaddressphaseofthelasttransferintheburst.Thiswillmeanthatifthepenultimatetransfer
intheburstiszerowaitstatethenthemastermaybegrantedthebusforanadditionaltransferatthe
endofanundefinedlengthburst.
For a definedlengthburstthemastercandeasserttheHBUSREQsignaloncethemasterhasbeen
grantedthebusforthefirsttransfer.Thiscanbedonebecausethearbiterisabletocountthetransfers
intheburstandkeepthemastergranteduntiltheburstcompletes.
HoweveritisnotamandatoryrequirementforanArbitertoallowabursttocomplete,sothemasterwill
havetore-assertHBUSREQiftheArbiterremovesHGRANTbeforethebursthasbeencompleted.

14. Whenshouldamasterassertandde-asserttheHLOCKsignalforalockedtransfer?
The HLOCK signal must be asserted at least one cycle before the start of the address phase of a
lockedtransfer.ThisisrequiredsothatthearbitercansampletheHLOCKsignalashighatthestartof
theaddressphase.
The master should deassert the HLOCK signal when the address phase of the last transfer in the
lockedsequencehasstarted.

15. WhatistherelationshipbetweentheHLOCKsignalandtheHMASTLOCKsignal?
At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the
master that is about to start driving the address bus and if HLOCK is asserted at this point then
HMASTLOCKwillbeassertedbythearbiterforthedurationoftheaddressphaseofthetransfer.

Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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16. Whatsequencesoftransferstypes(HTRANS)canoccuronthebus?
(Note:WedonotaskyoutheHBURSTsignal)
ThefollowingexamplesshowsomeofthesequencesofHTRANSthatcanoccuronthebus:
AnormalburstoffourtransfersfollowedbyanIDLE.
N-S-S-S-I
AnormalburstoffourtransferswhichincludesBUSYtransfers.
N-S-B-S-B-S-I
Aburstoffourtransfersfollowedbyanotherburst.
N-S-S-S-N-S-S-S-I
Asingletransferfollowedbyaburstoffourtransfers.
N-N-S-S-S-I
AsingletransferfollowedbyanIDLE
N-I
AnundefinedlengthburstwhichconcludeswithaBUSYtransfer.
N-B-S-B-S-B-I
An undefined length burst which concludes with a BUSY transfer and is followed immediately by
anotherburst.
N-B-S-B-S-B-NS

Quiz:AdvancedMicrocontrollerBusArchitecture(AMBA)
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17. Pleasefillouttheaddress(HADDR)sequence.

18. DrawthetimingdiagramofAPBback-to-backtransfer.Thatmeansthetransfersequence
startswithawrite,whichisthenfollowedbyaread,thenawrite,thenaread.